From: Stephen Boyd <sboyd@kernel.org>
To: Abel Vesa <abel.vesa@nxp.com>
Cc: Andrey Smirnov <andrew.smirnov@gmail.com>,
Anson Huang <anson.huang@nxp.com>,
"A.s. Dong" <aisheng.dong@nxp.com>,
Fabio Estevam <fabio.estevam@nxp.com>,
Lucas Stach <l.stach@pengutronix.de>,
Rob Herring <robh@kernel.org>,
Sascha Hauer <kernel@pengutronix.de>,
dl-linux-imx <linux-imx@nxp.com>, Abel Vesa <abelvesa@linux.com>,
Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Michael Turquette <mturquette@baylibre.com>,
open list <linux-kernel@vger.kernel.org>,
"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
<linux-arm-kernel@lists.infradead.org>,
"open list:COMMON CLK FRAMEWORK" <linux-clk@vger.kernel.org>
Subject: Re: [PATCH v9 3/5] clk: imx: add SCCG PLL type
Date: Wed, 07 Nov 2018 11:01:02 -0800 [thread overview]
Message-ID: <154161726247.88331.15629902810537417880@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <20181107115444.gscxwud7e57nx3c7@fsr-ub1664-175>
Quoting Abel Vesa (2018-11-07 03:54:45)
> On Wed, Oct 17, 2018 at 12:55:52PM -0700, Stephen Boyd wrote:
> > Quoting Abel Vesa (2018-09-24 03:39:55)
> > > +static unsigned long clk_pll2_recalc_rate(struct clk_hw *hw,
> > > + unsigned long parent_rate)
> > > +{
> > > + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
> > > + u32 val, ref, divr1, divf1, divr2, divf2;
> > > + u64 temp64;
> > > +
> > > + val = readl_relaxed(pll->base + PLL_CFG0);
> > > + switch (FIELD_GET(PLL_REF_MASK, val)) {
> > > + case 0:
> > > + ref = OSC_25M;
> > > + break;
> > > + case 1:
> > > + ref = OSC_27M;
> > > + break;
> > > + default:
> > > + ref = OSC_25M;
> >
> > Does this information not come through 'parent_rate'?
> >
>
> No. So basically both pll1 and pll2 and the divider after it form together this SCCG:
>
> https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=834
>
> See: Figure 5-8. SSCG PLL Block Diagram
Thanks for the link!
>
> We're basically reading the input of the pll 1 in order to compute the output of the entire SCCG.
>
> I know it's a mess. I'm working on cleaning it up, but for now we need this in in order to boot up.
What's the plan to clean it up?
>
> > > + break;
> > > + }
> > > +
> > > + val = readl_relaxed(pll->base + PLL_CFG2);
> > > + divr1 = FIELD_GET(PLL_DIVR1_MASK, val);
> > > + divr2 = FIELD_GET(PLL_DIVR2_MASK, val);
> > > + divf1 = FIELD_GET(PLL_DIVF1_MASK, val);
> > > + divf2 = FIELD_GET(PLL_DIVF2_MASK, val);
> > > +
> > > + temp64 = ref * 2;
> > > + temp64 *= (divf1 + 1) * (divf2 + 1);
> > > +
> > > + do_div(temp64, (divr1 + 1) * (divr2 + 1));
> >
> > Nitpicks: A comment with the equation may be helpful to newcomers.
>
> Since the SCCG is contructed by multiple different types of clocks here, the equation doesn't help
> since it is spread in all constructing blocks.
Ok.
next prev parent reply other threads:[~2018-11-07 19:01 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1537785597-26499-1-git-send-email-abel.vesa@nxp.com>
2018-09-24 10:39 ` [PATCH v9 1/5] dt-bindings: add binding for i.MX8MQ CCM Abel Vesa
2018-10-17 20:00 ` Stephen Boyd
2018-09-24 10:39 ` [PATCH v9 2/5] clk: imx: add fractional PLL output clock Abel Vesa
2018-10-17 19:59 ` Stephen Boyd
2018-11-07 12:25 ` Abel Vesa
2018-09-24 10:39 ` [PATCH v9 3/5] clk: imx: add SCCG PLL type Abel Vesa
2018-10-17 19:55 ` Stephen Boyd
2018-11-07 11:54 ` Abel Vesa
2018-11-07 19:01 ` Stephen Boyd [this message]
2018-11-07 20:26 ` Abel Vesa
2018-11-08 0:18 ` Stephen Boyd
2018-11-08 12:29 ` Abel Vesa
2018-11-08 18:28 ` Stephen Boyd
2018-11-10 16:05 ` A.s. Dong
2018-11-13 14:25 ` Shawn Guo
2018-11-14 23:21 ` Stephen Boyd
2018-09-24 10:39 ` [PATCH v9 4/5] clk: imx: add imx composite clock Abel Vesa
2018-09-25 16:42 ` Fabio Estevam
2018-09-26 6:47 ` Sascha Hauer
2018-09-26 12:02 ` Fabio Estevam
2018-10-17 19:51 ` Stephen Boyd
2018-10-18 9:57 ` Abel Vesa
2018-09-24 10:39 ` [PATCH v9 5/5] clk: imx: add clock driver for i.MX8MQ CCM Abel Vesa
2018-10-17 19:44 ` Stephen Boyd
2018-11-07 12:09 ` Abel Vesa
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