* [PATCH] x86/cpufeatures: Add WBNOINVD feature definition
@ 2018-11-07 20:59 Natarajan, Janakarajan
2018-11-07 21:27 ` [tip:x86/cpu] " tip-bot for Janakarajan Natarajan
0 siblings, 1 reply; 2+ messages in thread
From: Natarajan, Janakarajan @ 2018-11-07 20:59 UTC (permalink / raw)
To: x86, linux-kernel
Cc: Thomas Gleixner, Ingo Molnar, Borislav Petkov, H . Peter Anvin,
Konrad Rzeszutek Wilk, David Woodhouse, Fenghua Yu, Natarajan,
Janakarajan
Add a new cpufeature definition for the WBNOINVD instruction.
The WBNOINVD instruction writes all modified line in all levels of
cache associated with a processor to main memory while retaining the
cached values.
Both AMD and Intel support this instruction.
Signed-off-by: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com>
---
arch/x86/include/asm/cpufeatures.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 28c4a50..39a48f0 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -281,6 +281,7 @@
#define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
#define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */
#define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */
+#define X86_FEATURE_WBNOINVD (13*32+ 9) /* WBNOINVD instruction */
#define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch Prediction Barrier */
#define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */
#define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect Branch Predictors */
--
2.7.4
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [tip:x86/cpu] x86/cpufeatures: Add WBNOINVD feature definition
2018-11-07 20:59 [PATCH] x86/cpufeatures: Add WBNOINVD feature definition Natarajan, Janakarajan
@ 2018-11-07 21:27 ` tip-bot for Janakarajan Natarajan
0 siblings, 0 replies; 2+ messages in thread
From: tip-bot for Janakarajan Natarajan @ 2018-11-07 21:27 UTC (permalink / raw)
To: linux-tip-commits
Cc: tglx, mingo, bp, mingo, linux-kernel, hpa, dwmw, r.marek,
Janakarajan.Natarajan, fenghua.yu, konrad.wilk, x86
Commit-ID: 08e823c2c5899ef2de3aa1727233f1f19e8c1cc1
Gitweb: https://git.kernel.org/tip/08e823c2c5899ef2de3aa1727233f1f19e8c1cc1
Author: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com>
AuthorDate: Wed, 7 Nov 2018 20:59:07 +0000
Committer: Borislav Petkov <bp@suse.de>
CommitDate: Wed, 7 Nov 2018 22:21:03 +0100
x86/cpufeatures: Add WBNOINVD feature definition
Add a new cpufeature definition for the WBNOINVD instruction.
The WBNOINVD instruction writes all modified cache lines in all levels of
the cache associated with a processor to main memory while retaining the
cached values.
Both AMD and Intel support this instruction.
Signed-off-by: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
CC: David Woodhouse <dwmw@amazon.co.uk>
CC: Fenghua Yu <fenghua.yu@intel.com>
CC: "H. Peter Anvin" <hpa@zytor.com>
CC: Ingo Molnar <mingo@redhat.com>
CC: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
CC: Rudolf Marek <r.marek@assembler.cz>
CC: Thomas Gleixner <tglx@linutronix.de>
CC: x86-ml <x86@kernel.org>
Link: http://lkml.kernel.org/r/1541624211-32196-1-git-send-email-Janakarajan.Natarajan@amd.com
---
arch/x86/include/asm/cpufeatures.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 28c4a502b419..39a48f06d39d 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -281,6 +281,7 @@
#define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
#define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */
#define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */
+#define X86_FEATURE_WBNOINVD (13*32+ 9) /* WBNOINVD instruction */
#define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch Prediction Barrier */
#define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */
#define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect Branch Predictors */
^ permalink raw reply related [flat|nested] 2+ messages in thread
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