* [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core
@ 2018-11-16 23:56 Jolly Shah
2018-11-16 23:56 ` [PATCH 1/9] dt-bindings: power: Add ZynqMP power domain bindings Jolly Shah
` (10 more replies)
0 siblings, 11 replies; 15+ messages in thread
From: Jolly Shah @ 2018-11-16 23:56 UTC (permalink / raw)
To: robh+dt, mark.rutland
Cc: michal.simek, rajanv, nava.manne, linux-arm-kernel, linux-kernel,
devicetree, Jolly Shah
Base firmware node and clock child node binding are part of mainline kernel. This patchset adds documentation to describe rest of the firmware child node bindings.
Complete firmware DT node example is shown below for ease of understanding:
firmware {
zynqmp_firmware: zynqmp-firmware {
compatible = "xlnx,zynqmp-firmware";
method = "smc";
#power-domain-cells = <1>;
#reset-cells = <1>;
zynqmp_clk: clock-controller {
#clock-cells = <1>;
compatible = "xlnx,zynqmp-clk";
clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>;
clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
};
zynqmp_power: zynqmp-power {
compatible = "xlnx,zynqmp-power";
interrupts = <0 35 4>;
};
nvmem_firmware {
compatible = "xlnx,zynqmp-nvmem-fw";
#address-cells = <1>;
#size-cells = <1>;
/* Data cells */
soc_revision: soc_revision {
reg = <0x0 0x4>;
};
};
afi0: afi0 {
compatible = "xlnx,afi-fpga";
config-afi = <0 2>, <1 1>, <2 1>;
};
qspi: spi@ff0f0000 {
compatible = "xlnx,zynqmp-qspi-1.0";
clock-names = "ref_clk", "pclk";
clocks = <&misc_clk &misc_clk>;
interrupts = <0 15 4>;
interrupt-parent = <&gic>;
num-cs = <1>;
reg = <0x0 0xff0f0000 0x1000>,<0x0 0xc0000000 0x8000000>;
};
serdes: zynqmp_phy@fd400000 {
compatible = "xlnx,zynqmp-psgtr";
status = "okay";
reg = <0x0 0xfd400000 0x0 0x40000>, <0x0 0xfd3d0000 0x0 0x1000>,
<0x0 0xff5e0000 0x0 0x1000>;
reg-names = "serdes", "siou", "lpd";
lane0: lane@0 {
#phy-cells = <4>;
};
lane1: lane@1 {
#phy-cells = <4>;
};
lane2: lane@2 {
#phy-cells = <4>;
};
lane3: lane@3 {
#phy-cells = <4>;
};
};
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart0_4_grp";
function = "uart0";
};
conf {
groups = "uart0_4_grp";
slew-rate = <SLEW_RATE_SLOW>;
io-standard = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO18";
bias-high-impedance;
};
conf-tx {
pins = "MIO19";
bias-disable;
schmitt-cmos = <PIN_INPUT_TYPE_CMOS>;
};
};
zynqmp-r5-remoteproc@0 {
compatible = "xlnx,zynqmp-r5-remoteproc-1.0";
reg = <0x0 0xFFE00000 0x0 0x10000>,
<0x0 0xFFE20000 0x0 0x10000>,
<0x0 0xff340000 0x0 0x100>;
reg-names = "tcm_a", "tcm_b", "ipi";
dma-ranges;
core_conf = "split0";
memory-region = <&rproc_0_fw_reserved>,
<&rproc_0_dma_reserved>;
tcm-pnode-id = <0xf>, <0x10>;
rpu-pnode-id = <0x7>;
interrupt-parent = <&gic>;
interrupts = <0 29 4>;
};
};
};
Jolly Shah (2):
dt-bindings: phy: Add dt bindings for ZynqMP PHY
dt-bindings: fpga: Add binding doc for the afi config driver
Nava kishore Manne (2):
dt-bindings: reset: Add bindings for ZynqMP reset driver
dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver
Rajan Vaja (4):
dt-bindings: power: Add ZynqMP power domain bindings
dt-bindings: soc: Add ZynqMP PM bindings
dt-bindings: pinctrl: Add ZynqMP pin controller bindings
dt-bindings: spi: zynqmp: Move SPI node under zynqmp firmware
Wendy Liang (1):
dt-bindings: remoteproc: Add Xilinx R5 rproc binding
.../devicetree/bindings/fpga/xlnx,afi-fpga.txt | 67 +++++
.../bindings/nvmem/xlnx,zynqmp-nvmem.txt | 44 ++++
.../devicetree/bindings/phy/phy-zynqmp.txt | 126 ++++++++++
.../bindings/pinctrl/xlnx,zynqmp-pinctrl.txt | 272 +++++++++++++++++++++
.../bindings/power/reset/xlnx,zynqmp-power.txt | 25 ++
.../bindings/power/xlnx,zynqmp-genpd.txt | 34 +++
.../remoteproc/xlnx,zynqmp-r5-remoteproc.txt | 81 ++++++
.../bindings/reset/xlnx,zynqmp-reset.txt | 148 +++++++++++
.../devicetree/bindings/spi/spi-zynqmp-qspi.txt | 22 +-
include/dt-bindings/power/xlnx-zynqmp-power.h | 39 +++
10 files changed, 850 insertions(+), 8 deletions(-)
create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,afi-fpga.txt
create mode 100644 Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
create mode 100644 Documentation/devicetree/bindings/phy/phy-zynqmp.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.txt
create mode 100644 Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt
create mode 100644 Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt
create mode 100644 Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5-remoteproc.txt
create mode 100644 Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
create mode 100644 include/dt-bindings/power/xlnx-zynqmp-power.h
--
2.7.4
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 1/9] dt-bindings: power: Add ZynqMP power domain bindings 2018-11-16 23:56 [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core Jolly Shah @ 2018-11-16 23:56 ` Jolly Shah 2018-11-16 23:56 ` [PATCH 2/9] dt-bindings: soc: Add ZynqMP PM bindings Jolly Shah ` (9 subsequent siblings) 10 siblings, 0 replies; 15+ messages in thread From: Jolly Shah @ 2018-11-16 23:56 UTC (permalink / raw) To: robh+dt, mark.rutland Cc: michal.simek, rajanv, nava.manne, linux-arm-kernel, linux-kernel, devicetree, Rajan Vaja, Jolly Shah From: Rajan Vaja <rajan.vaja@xilinx.com> Add documentation to describe ZynqMP power domain bindings. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com> --- .../bindings/power/xlnx,zynqmp-genpd.txt | 34 +++++++++++++++++++ include/dt-bindings/power/xlnx-zynqmp-power.h | 39 ++++++++++++++++++++++ 2 files changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt create mode 100644 include/dt-bindings/power/xlnx-zynqmp-power.h diff --git a/Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt b/Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt new file mode 100644 index 0000000..3c7f237 --- /dev/null +++ b/Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt @@ -0,0 +1,34 @@ +----------------------------------------------------------- +Device Tree Bindings for the Xilinx Zynq MPSoC PM domains +----------------------------------------------------------- +The binding for zynqmp-power-controller follow the common +generic PM domain binding[1]. + +[1] Documentation/devicetree/bindings/power/power_domain.txt + +== Zynq MPSoC Generic PM Domain Node == + +Required property: + - Below property should be in zynqmp-firmware node. + - #power-domain-cells: Number of cells in a PM domain specifier. Must be 1. + +Power domain ID indexes are mentioned in +include/dt-bindings/power/xlnx-zynqmp-power.h. + +------- +Example +------- + +firmware { + zynqmp_firmware: zynqmp-firmware { + ... + #power-domain-cells = <1>; + ... + }; +}; + +sata { + ... + power-domains = <&zynqmp_firmware 2>; + ... +}; diff --git a/include/dt-bindings/power/xlnx-zynqmp-power.h b/include/dt-bindings/power/xlnx-zynqmp-power.h new file mode 100644 index 0000000..1bc9636 --- /dev/null +++ b/include/dt-bindings/power/xlnx-zynqmp-power.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Xilinx, Inc. + */ + +#ifndef _DT_BINDINGS_ZYNQMP_POWER_H +#define _DT_BINDINGS_ZYNQMP_POWER_H + +#define PD_USB_0 0 +#define PD_USB_1 1 +#define PD_SATA 2 +#define PD_SPI_0 3 +#define PD_SPI_1 4 +#define PD_UART_0 5 +#define PD_UART_1 6 +#define PD_ETH_0 7 +#define PD_ETH_1 8 +#define PD_ETH_2 9 +#define PD_ETH_3 10 +#define PD_I2C_0 11 +#define PD_I2C_1 12 +#define PD_DP 13 +#define PD_GDMA 14 +#define PD_ADMA 15 +#define PD_TTC_0 16 +#define PD_TTC_1 17 +#define PD_TTC_2 18 +#define PD_TTC_3 19 +#define PD_SD_0 20 +#define PD_SD_1 21 +#define PD_NAND 22 +#define PD_QSPI 23 +#define PD_GPIO 24 +#define PD_CAN_0 25 +#define PD_CAN_1 26 +#define PD_PCIE 27 +#define PD_GPU 28 + +#endif -- 2.7.4 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 2/9] dt-bindings: soc: Add ZynqMP PM bindings 2018-11-16 23:56 [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core Jolly Shah 2018-11-16 23:56 ` [PATCH 1/9] dt-bindings: power: Add ZynqMP power domain bindings Jolly Shah @ 2018-11-16 23:56 ` Jolly Shah 2018-11-16 23:56 ` [PATCH 3/9] dt-bindings: reset: Add bindings for ZynqMP reset driver Jolly Shah ` (8 subsequent siblings) 10 siblings, 0 replies; 15+ messages in thread From: Jolly Shah @ 2018-11-16 23:56 UTC (permalink / raw) To: robh+dt, mark.rutland Cc: michal.simek, rajanv, nava.manne, linux-arm-kernel, linux-kernel, devicetree, Rajan Vaja, Jolly Shah From: Rajan Vaja <rajan.vaja@xilinx.com> Add documentation to describe Xilinx ZynqMP power management bindings. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com> --- .../bindings/power/reset/xlnx,zynqmp-power.txt | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt diff --git a/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt b/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt new file mode 100644 index 0000000..d366f1e --- /dev/null +++ b/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt @@ -0,0 +1,25 @@ +-------------------------------------------------------------------- +Device Tree Bindings for the Xilinx Zynq MPSoC Power Management +-------------------------------------------------------------------- +The zynqmp-power node describes the power management configurations. +It will control remote suspend/shutdown interfaces. + +Required properties: + - compatible: Must contain: "xlnx,zynqmp-power" + - interrupts: Interrupt specifier + +------- +Example +------- + +firmware { + zynqmp_firmware: zynqmp-firmware { + compatible = "xlnx,zynqmp-firmware"; + method = "smc"; + + zynqmp_power: zynqmp-power { + compatible = "xlnx,zynqmp-power"; + interrupts = <0 35 4>; + }; + }; +}; -- 2.7.4 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 3/9] dt-bindings: reset: Add bindings for ZynqMP reset driver 2018-11-16 23:56 [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core Jolly Shah 2018-11-16 23:56 ` [PATCH 1/9] dt-bindings: power: Add ZynqMP power domain bindings Jolly Shah 2018-11-16 23:56 ` [PATCH 2/9] dt-bindings: soc: Add ZynqMP PM bindings Jolly Shah @ 2018-11-16 23:56 ` Jolly Shah 2018-11-16 23:56 ` [PATCH 4/9] dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver Jolly Shah ` (7 subsequent siblings) 10 siblings, 0 replies; 15+ messages in thread From: Jolly Shah @ 2018-11-16 23:56 UTC (permalink / raw) To: robh+dt, mark.rutland Cc: michal.simek, rajanv, nava.manne, linux-arm-kernel, linux-kernel, devicetree, Jolly Shah From: Nava kishore Manne <nava.manne@xilinx.com> Add documentation to describe Xilinx ZynqMP reset driver bindings. Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com> --- .../bindings/reset/xlnx,zynqmp-reset.txt | 148 +++++++++++++++++++++ 1 file changed, 148 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt diff --git a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt new file mode 100644 index 0000000..e9c1af8 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt @@ -0,0 +1,148 @@ +-------------------------------------------------------------------------- + = Zynq UltraScale+ MPSoC reset driver binding = +-------------------------------------------------------------------------- +The Zynq UltraScale+ MPSoC has several different resets. + +See Chapter 36 of the Zynq UltraScale+ MPSoC TRM (UG) for more information +about zynqmp resets. + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +Required Properties: +- #reset-cells: Specifies the number of cells needed to encode reset + line, should be 1 + +Reset outputs: + 0 :PCIE config reset. + 1 :PCIE bridge block level reset (AXI interface). + 2 :PCIE control block level,reset. + 3 :Display Port block level reset (includes DPDMA). + 4 :FPD WDT reset. + 5 :AF_FM5 block level reset. + 6 :AF_FM4 block level reset. + 7 :AF_FM3 block level reset. + 8 :AF_FM2 block level reset. + 9 :AF_FM1 block level reset. + 10 :AF_FM0 block level reset. + 11 :GDMA block level reset. + 12 :Pixel Processor (GPU_PP1) block level reset. + 13 :Pixel Processor (GPU_PP0) block level reset. + 14 :GPU block level reset. + 15 :GT block level reset. + 16 :Sata block level reset. + 17 :ACPU3 power on reset. + 18 :ACPU2 power on reset. + 19 :ACPU1 power on reset. + 20 :ACPU0 power on reset. + 21 :APU L2 reset. + 22 :ACPU3 reset. + 23 :ACPU2 reset. + 24 :ACPU1 reset. + 25 :ACPU0 reset. + 26 :DDR block level reset inside of the DDR Sub System. + 27 :APM block level reset inside of the DDR Sub System. + 28 :soft reset. + 29 :GEM 0 reset. + 30 :GEM 1 reset. + 31 :GEM 2 reset. + 32 :GEM 3 reset. + 33 :qspi reset. + 34 :uart0 reset. + 35 :uart1 reset. + 36 :spi0 reset. + 37 :spi1 reset. + 38 :sdio0 reset. + 39 :sdio1 reset. + 40 :can0 reset. + 41 :can1 reset. + 42 :i2c0 reset. + 43 :i2c1 reset. + 44 :ttc0 reset. + 45 :ttc1 reset. + 46 :ttc2 reset. + 47 :ttc3 reset. + 48 :swdt reset. + 49 :nand reset. + 50 :adma reset. + 51 :gpio reset. + 52 :iou_cc reset. + 53 :timestamp reset. + 54 :rpu_r50 reset. + 55 :rpu r51 reset. + 56 :rpu_amba reset. + 57 :ocm reset. + 58 :rpu_pge reset. + 59 :usb0_core reset. + 60 :usb1_core reset. + 61 :usb0_hiber reset. + 62 :usb1_hiber reset. + 63 :usb0_apb reset. + 64 :usb1_apb reset. + 65 :ipi reset. + 66 :apm reset. + 67 :rtc reset. + 68 :sysmon reset. + 69 :afi_fm6 reset. + 70 :lpd_swdt reset. + 71 :fpd_reset. + 72 :rpu_dbg1 reset. + 73 :rpu_dbg0 reset. + 74 :dbg_lpd reset. + 75 :dbg_fpd reset. + 76 :apll reset. + 77 :dpll reset. + 78 :vpll reset. + 79 :iopll reset. + 80 :rpll reset. + 81 :gpio_pl_0 reset. + 82 :gpio_pl_1 reset. + 83 :gpio_pl_2 reset. + 84 :gpio_pl_3 reset. + 85 :gpio_pl_4 reset. + 86 :gpio_pl_5 reset. + 87 :gpio_pl_6 reset. + 88 :gpio_pl_7 reset. + 89 :gpio_pl_8 reset. + 90 :gpio_pl_9 reset. + 91 :gpio_pl_10 reset. + 92 :gpio_pl_11 reset. + 93 :gpio_pl_12 reset. + 94 :gpio_pl_13 reset. + 95 :gpio_pl_14 reset. + 96 :gpio_pl_15 reset. + 97 :gpio_pl_16 reset. + 98 :gpio_pl_17 reset. + 99 :gpio_pl_18 reset. + 100 :gpio_pl_19 reset. + 101 :gpio_pl_20 reset. + 102 :gpio_pl_21 reset. + 103 :gpio_pl_22 reset. + 104 :gpio_pl_23 reset. + 105 :gpio_pl_24 reset. + 106 :gpio_pl_25 reset. + 107 :gpio_pl_26 reset. + 108 :gpio_pl_27 reset. + 109 :gpio_pl_28 reset. + 110 :gpio_pl_29 reset. + 111 :gpio_pl_30 reset. + 112 :gpio_pl_31 reset. + 113 :rpu_ls reset. + 114 :ps_only reset. + 115 :pl reset. + 116 :ps_pl0 reset + 117 :ps_pl1 reset + 118 :ps_pl2 reset + 119 :ps_pl3 reset + +------- +Example +------- + +firmware { + zynqmp_firmware: zynqmp-firmware { + ... + #reset-cells = <1>; + ... + }; +}; -- 2.7.4 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 4/9] dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver 2018-11-16 23:56 [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core Jolly Shah ` (2 preceding siblings ...) 2018-11-16 23:56 ` [PATCH 3/9] dt-bindings: reset: Add bindings for ZynqMP reset driver Jolly Shah @ 2018-11-16 23:56 ` Jolly Shah 2018-11-16 23:56 ` [PATCH 5/9] dt-bindings: pinctrl: Add ZynqMP pin controller bindings Jolly Shah ` (6 subsequent siblings) 10 siblings, 0 replies; 15+ messages in thread From: Jolly Shah @ 2018-11-16 23:56 UTC (permalink / raw) To: robh+dt, mark.rutland Cc: michal.simek, rajanv, nava.manne, linux-arm-kernel, linux-kernel, devicetree, Jolly Shah From: Nava kishore Manne <nava.manne@xilinx.com> Add documentation to describe Xilinx ZynqMP nvmem driver bindings. Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com> --- .../bindings/nvmem/xlnx,zynqmp-nvmem.txt | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt diff --git a/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt new file mode 100644 index 0000000..090ba08 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt @@ -0,0 +1,44 @@ +-------------------------------------------------------------------------- += Zynq UltraScale+ MPSoC nvmem firmware driver binding = +-------------------------------------------------------------------------- +The nvmem_firmware node provides access to the hardware related data +like soc revision, IDCODE... etc, By using the firmware interface. + +Required properties: +- compatible: should be "xlnx,zynqmp-nvmem-fw" + += Data cells = +Are child nodes of silicon id, bindings of which as described in +bindings/nvmem/nvmem.txt + +------- + Example +------- +firmware { + zynqmp_firmware: zynqmp-firmware { + compatible = "xlnx,zynqmp-firmware"; + method = "smc"; + + nvmem_firmware { + compatible = "xlnx,zynqmp-nvmem-fw"; + #address-cells = <1>; + #size-cells = <1>; + + /* Data cells */ + soc_revision: soc_revision { + reg = <0x0 0x4>; + }; + }; + }; +}; + += Data consumers = +Are device nodes which consume nvmem data cells. + +For example: + pcap { + ... + nvmem-cells = <&soc_revision>; + nvmem-cell-names = "soc_revision"; + }; + -- 2.7.4 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 5/9] dt-bindings: pinctrl: Add ZynqMP pin controller bindings 2018-11-16 23:56 [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core Jolly Shah ` (3 preceding siblings ...) 2018-11-16 23:56 ` [PATCH 4/9] dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver Jolly Shah @ 2018-11-16 23:56 ` Jolly Shah 2018-11-16 23:56 ` [PATCH 6/9] dt-bindings: spi: zynqmp: Move SPI node under zynqmp firmware Jolly Shah ` (5 subsequent siblings) 10 siblings, 0 replies; 15+ messages in thread From: Jolly Shah @ 2018-11-16 23:56 UTC (permalink / raw) To: robh+dt, mark.rutland Cc: michal.simek, rajanv, nava.manne, linux-arm-kernel, linux-kernel, devicetree, Rajan Vaja, Jolly Shah From: Rajan Vaja <rajan.vaja@xilinx.com> Add documentation to describe Xilinx ZynqMP pin controller bindings. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com> --- .../bindings/pinctrl/xlnx,zynqmp-pinctrl.txt | 272 +++++++++++++++++++++ 1 file changed, 272 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.txt diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.txt new file mode 100644 index 0000000..0d54b40 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.txt @@ -0,0 +1,272 @@ + Binding for Xilinx ZynqMP Pinctrl + +Required properties: +ZynqMP pin control driver is populated by ZynqMP firmware and doesn't need +any separate property. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +ZynqMP's pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, slew rate, etc. + +Each configuration node can consist of multiple nodes describing the pinmux and +pinconf options. Those nodes can be pinmux nodes or pinconf nodes. + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Required properties for pinmux nodes are: + - groups: A list of pinmux groups. + - function: The name of a pinmux function to activate for the specified set + of groups. + +Required properties for configuration nodes: +One of: + - pins: A list of pin names + - groups: A list of pinmux groups. + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pinmux subnode: + groups, function + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pinconf subnode: + groups, pins, bias-disable, bias-pull-up, bias-pull-down, slew-rate + + Valid arguments for 'slew-rate' are 'SLEW_RATE_SLOW' and 'SLEW_RATE_FAST' to + select between slow and fast respectively. + + Valid values for groups are: + ethernet0_0_grp, ethernet1_0_grp, ethernet2_0_grp, + ethernet3_0_grp, gemtsu0_0_grp, gemtsu0_1_grp, + gemtsu0_2_grp, mdio0_0_grp, mdio1_0_grp, + mdio1_1_grp, mdio2_0_grp, mdio3_0_grp, + qspi0_0_grp, qspi_ss_0_grp, qspi_fbclk_0_grp, + spi0_0_grp, spi0_ss_0_grp, spi0_ss_1_grp, + spi0_ss_2_grp, spi0_1_grp, spi0_ss_3_grp, + spi0_ss_4_grp, spi0_ss_5_grp, spi0_2_grp, + spi0_ss_6_grp, spi0_ss_7_grp, spi0_ss_8_grp, + spi0_3_grp, spi0_ss_9_grp, spi0_ss_10_grp, + spi0_ss_11_grp, spi0_4_grp, spi0_ss_12_grp, + spi0_ss_13_grp, spi0_ss_14_grp, spi0_5_grp, + spi0_ss_15_grp, spi0_ss_16_grp, spi0_ss_17_grp, + spi1_0_grp, spi1_ss_0_grp, spi1_ss_1_grp, + spi1_ss_2_grp, spi1_1_grp, spi1_ss_3_grp, + spi1_ss_4_grp, spi1_ss_5_grp, spi1_2_grp, + spi1_ss_6_grp, spi1_ss_7_grp, spi1_ss_8_grp, + spi1_3_grp, spi1_ss_9_grp, spi1_ss_10_grp, + spi1_ss_11_grp, spi1_4_grp, spi1_ss_12_grp, + spi1_ss_13_grp, spi1_ss_14_grp, spi1_5_grp, + spi1_ss_15_grp, spi1_ss_16_grp, spi1_ss_17_grp, + sdio0_0_grp, sdio0_1_grp, sdio0_2_grp, + sdio0_3_grp, sdio0_4_grp, sdio0_5_grp, + sdio0_6_grp, sdio0_7_grp, sdio0_8_grp, + sdio0_9_grp, sdio0_10_grp, sdio0_11_grp, + sdio0_12_grp, sdio0_13_grp, sdio0_14_grp, + sdio0_15_grp, sdio0_16_grp, sdio0_17_grp, + sdio0_18_grp, sdio0_19_grp, sdio0_20_grp, + sdio0_21_grp, sdio0_22_grp, sdio0_23_grp, + sdio0_24_grp, sdio0_25_grp, sdio0_26_grp, + sdio0_27_grp, sdio0_28_grp, sdio0_29_grp, + sdio0_30_grp, sdio0_31_grp, sdio0_32_grp, + sdio0_pc_0_grp, sdio0_cd_0_grp, sdio0_wp_0_grp, + sdio0_pc_1_grp, sdio0_cd_1_grp, sdio0_wp_1_grp, + sdio0_pc_2_grp, sdio0_cd_2_grp, sdio0_wp_2_grp, + sdio1_0_grp, sdio1_1_grp, sdio1_2_grp, + sdio1_3_grp, sdio1_4_grp, sdio1_5_grp, + sdio1_6_grp, sdio1_7_grp, sdio1_8_grp, + sdio1_9_grp, sdio1_10_grp, sdio1_11_grp, + sdio1_12_grp, sdio1_13_grp, sdio1_14_grp, + sdio1_15_grp, sdio1_pc_0_grp, sdio1_cd_0_grp, + sdio1_wp_0_grp, sdio1_pc_1_grp, sdio1_cd_1_grp, + sdio1_wp_1_grp, nand0_0_grp, nand0_ce_0_grp, + nand0_rb_0_grp, nand0_dqs_0_grp, nand0_ce_1_grp, + nand0_rb_1_grp, nand0_dqs_1_grp, can0_0_grp, + can0_1_grp, can0_2_grp, can0_3_grp, + can0_4_grp, can0_5_grp, can0_6_grp, + can0_7_grp, can0_8_grp, can0_9_grp, + can0_10_grp, can0_11_grp, can0_12_grp, + can0_13_grp, can0_14_grp, can0_15_grp, + can0_16_grp, can0_17_grp, can0_18_grp, + can1_0_grp, can1_1_grp, can1_2_grp, + can1_3_grp, can1_4_grp, can1_5_grp, + can1_6_grp, can1_7_grp, can1_8_grp, + can1_9_grp, can1_10_grp, can1_11_grp, + can1_12_grp, can1_13_grp, can1_14_grp, + can1_15_grp, can1_16_grp, can1_17_grp, + can1_18_grp, can1_19_grp, uart0_0_grp, + uart0_1_grp, uart0_2_grp, uart0_3_grp, + uart0_4_grp, uart0_5_grp, uart0_6_grp, + uart0_7_grp, uart0_8_grp, uart0_9_grp, + uart0_10_grp, uart0_11_grp, uart0_12_grp, + uart0_13_grp, uart0_14_grp, uart0_15_grp, + uart0_16_grp, uart0_17_grp, uart0_18_grp, + uart1_0_grp, uart1_1_grp, uart1_2_grp, + uart1_3_grp, uart1_4_grp, uart1_5_grp, + uart1_6_grp, uart1_7_grp, uart1_8_grp, + uart1_9_grp, uart1_10_grp, uart1_11_grp, + uart1_12_grp, uart1_13_grp, uart1_14_grp, + uart1_15_grp, uart1_16_grp, uart1_17_grp, + uart1_18_grp, i2c0_0_grp, i2c0_1_grp, + i2c0_2_grp, i2c0_3_grp, i2c0_4_grp, + i2c0_5_grp, i2c0_6_grp, i2c0_7_grp, + i2c0_8_grp, i2c0_9_grp, i2c0_10_grp, + i2c0_11_grp, i2c0_12_grp, i2c0_13_grp, + i2c0_14_grp, i2c0_15_grp, i2c0_16_grp, + i2c0_17_grp, i2c0_18_grp, i2c1_0_grp, + i2c1_1_grp, i2c1_2_grp, i2c1_3_grp, + i2c1_4_grp, i2c1_5_grp, i2c1_6_grp, + i2c1_7_grp, i2c1_8_grp, i2c1_9_grp, + i2c1_10_grp, i2c1_11_grp, i2c1_12_grp, + i2c1_13_grp, i2c1_14_grp, i2c1_15_grp, + i2c1_16_grp, i2c1_17_grp, i2c1_18_grp, + i2c1_19_grp, ttc0_clk_0_grp, ttc0_wav_0_grp, + ttc0_clk_1_grp, ttc0_wav_1_grp, ttc0_clk_2_grp, + ttc0_wav_2_grp, ttc0_clk_3_grp, ttc0_wav_3_grp, + ttc0_clk_4_grp, ttc0_wav_4_grp, ttc0_clk_5_grp, + ttc0_wav_5_grp, ttc0_clk_6_grp, ttc0_wav_6_grp, + ttc0_clk_7_grp, ttc0_wav_7_grp, ttc0_clk_8_grp, + ttc0_wav_8_grp, ttc1_clk_0_grp, ttc1_wav_0_grp, + ttc1_clk_1_grp, ttc1_wav_1_grp, ttc1_clk_2_grp, + ttc1_wav_2_grp, ttc1_clk_3_grp, ttc1_wav_3_grp, + ttc1_clk_4_grp, ttc1_wav_4_grp, ttc1_clk_5_grp, + ttc1_wav_5_grp, ttc1_clk_6_grp, ttc1_wav_6_grp, + ttc1_clk_7_grp, ttc1_wav_7_grp, ttc1_clk_8_grp, + ttc1_wav_8_grp, ttc2_clk_0_grp, ttc2_wav_0_grp, + ttc2_clk_1_grp, ttc2_wav_1_grp, ttc2_clk_2_grp, + ttc2_wav_2_grp, ttc2_clk_3_grp, ttc2_wav_3_grp, + ttc2_clk_4_grp, ttc2_wav_4_grp, ttc2_clk_5_grp, + ttc2_wav_5_grp, ttc2_clk_6_grp, ttc2_wav_6_grp, + ttc2_clk_7_grp, ttc2_wav_7_grp, ttc2_clk_8_grp, + ttc2_wav_8_grp, ttc3_clk_0_grp, ttc3_wav_0_grp, + ttc3_clk_1_grp, ttc3_wav_1_grp, ttc3_clk_2_grp, + ttc3_wav_2_grp, ttc3_clk_3_grp, ttc3_wav_3_grp, + ttc3_clk_4_grp, ttc3_wav_4_grp, ttc3_clk_5_grp, + ttc3_wav_5_grp, ttc3_clk_6_grp, ttc3_wav_6_grp, + ttc3_clk_7_grp, ttc3_wav_7_grp, ttc3_clk_8_grp, + ttc3_wav_8_grp, swdt0_clk_0_grp, swdt0_rst_0_grp, + swdt0_clk_1_grp, swdt0_rst_1_grp, swdt0_clk_2_grp, + swdt0_rst_2_grp, swdt0_clk_3_grp, swdt0_rst_3_grp, + swdt0_clk_4_grp, swdt0_rst_4_grp, swdt0_clk_5_grp, + swdt0_rst_5_grp, swdt0_clk_6_grp, swdt0_rst_6_grp, + swdt0_clk_7_grp, swdt0_rst_7_grp, swdt0_clk_8_grp, + swdt0_rst_8_grp, swdt0_clk_9_grp, swdt0_rst_9_grp, + swdt0_clk_10_grp, swdt0_rst_10_grp, swdt0_clk_11_grp, + swdt0_rst_11_grp, swdt0_clk_12_grp, swdt0_rst_12_grp, + swdt1_clk_0_grp, swdt1_rst_0_grp, swdt1_clk_1_grp, + swdt1_rst_1_grp, swdt1_clk_2_grp, swdt1_rst_2_grp, + swdt1_clk_3_grp, swdt1_rst_3_grp, swdt1_clk_4_grp, + swdt1_rst_4_grp, swdt1_clk_5_grp, swdt1_rst_5_grp, + swdt1_clk_6_grp, swdt1_rst_6_grp, swdt1_clk_7_grp, + swdt1_rst_7_grp, swdt1_clk_8_grp, swdt1_rst_8_grp, + swdt1_clk_9_grp, swdt1_rst_9_grp, swdt1_clk_10_grp, + swdt1_rst_10_grp, swdt1_clk_11_grp, swdt1_rst_11_grp, + swdt1_clk_12_grp, swdt1_rst_12_grp, gpio0_0_grp, + gpio0_1_grp, gpio0_2_grp, gpio0_3_grp, + gpio0_4_grp, gpio0_5_grp, gpio0_6_grp, + gpio0_7_grp, gpio0_8_grp, gpio0_9_grp, + gpio0_10_grp, gpio0_11_grp, gpio0_12_grp, + gpio0_13_grp, gpio0_14_grp, gpio0_15_grp, + gpio0_16_grp, gpio0_17_grp, gpio0_18_grp, + gpio0_19_grp, gpio0_20_grp, gpio0_21_grp, + gpio0_22_grp, gpio0_23_grp, gpio0_24_grp, + gpio0_25_grp, gpio0_26_grp, gpio0_27_grp, + gpio0_28_grp, gpio0_29_grp, gpio0_30_grp, + gpio0_31_grp, gpio0_32_grp, gpio0_33_grp, + gpio0_34_grp, gpio0_35_grp, gpio0_36_grp, + gpio0_37_grp, gpio0_38_grp, gpio0_39_grp, + gpio0_40_grp, gpio0_41_grp, gpio0_42_grp, + gpio0_43_grp, gpio0_44_grp, gpio0_45_grp, + gpio0_46_grp, gpio0_47_grp, gpio0_48_grp, + gpio0_49_grp, gpio0_50_grp, gpio0_51_grp, + gpio0_52_grp, gpio0_53_grp, gpio0_54_grp, + gpio0_55_grp, gpio0_56_grp, gpio0_57_grp, + gpio0_58_grp, gpio0_59_grp, gpio0_60_grp, + gpio0_61_grp, gpio0_62_grp, gpio0_63_grp, + gpio0_64_grp, gpio0_65_grp, gpio0_66_grp, + gpio0_67_grp, gpio0_68_grp, gpio0_69_grp, + gpio0_70_grp, gpio0_71_grp, gpio0_72_grp, + gpio0_73_grp, gpio0_74_grp, gpio0_75_grp, + gpio0_76_grp, gpio0_77_grp, usb0_0_grp, + usb1_0_grp, pmu0_0_grp, pmu0_1_grp, + pmu0_2_grp, pmu0_3_grp, pmu0_4_grp, + pmu0_5_grp, pmu0_6_grp, pmu0_7_grp, + pmu0_8_grp, pmu0_9_grp, pmu0_10_grp, + pmu0_11_grp, pcie0_0_grp, pcie0_1_grp, + pcie0_2_grp, pcie0_3_grp, pcie0_4_grp, + pcie0_5_grp, pcie0_6_grp, pcie0_7_grp, + csu0_0_grp, csu0_1_grp, csu0_2_grp, + csu0_3_grp, csu0_4_grp, csu0_5_grp, + csu0_6_grp, csu0_7_grp, csu0_8_grp, + csu0_9_grp, csu0_10_grp, csu0_11_grp, + dpaux0_0_grp, dpaux0_1_grp, dpaux0_2_grp, + dpaux0_3_grp, pjtag0_0_grp, pjtag0_1_grp, + pjtag0_2_grp, pjtag0_3_grp, pjtag0_4_grp, + pjtag0_5_grp, trace0_0_grp, trace0_clk_0_grp, + trace0_1_grp, trace0_clk_1_grp, trace0_2_grp, + trace0_clk_2_grp, testscan0_0_grp + + Valid values for pins are: + MIO0 - MIO77 + + Valid values for function are: + ethernet0, ethernet1, ethernet2, ethernet3, gemtsu0, usb0, usb1, mdio0, + mdio1, mdio2, mdio3, qspi0, qspi_fbclk, qspi_ss, spi0, spi1, spi0_ss, + spi1_ss, sdio0, sdio0_pc, sdio0_wp, sdio0_cd, sdio1, sdio1_pc, sdio1_wp, + sdio1_cd, nand0, nand0_ce, nand0_rb, nand0_dqs, can0, can1, uart0, uart1, + i2c0, i2c1, ttc0_clk, ttc0_wav, ttc1_clk, ttc1_wav, ttc2_clk, ttc2_wav, + ttc3_clk, ttc3_wav, swdt0_clk, swdt0_rst, swdt1_clk, swdt1_rst, gpio0, pmu0, + pcie0, csu0, dpaux0, pjtag0, trace0, trace0_clk, testscan0 + +The following driver-specific properties as defined here are valid to specify in +a pin configuration subnode: + - io-standard: Configure the pin to use the selected IO standard. Valid + arguments are 'IO_STANDARD_LVCMOS33' and 'IO_STANDARD_LVCMOS18'. + - schmitt-cmos: Selects either Schmitt or CMOS input for MIO pins. Valid + arguments are 'PIN_INPUT_TYPE_SCHMITT' and 'PIN_INPUT_TYPE_CMOS'. + +Example: + +firmware { + zynqmp_firmware: zynqmp-firmware { + compatible = "xlnx,zynqmp-firmware"; + method = "smc"; + + pinctrl_uart1_default: uart1-default { + mux { + groups = "uart0_4_grp"; + function = "uart0"; + }; + + conf { + groups = "uart0_4_grp"; + slew-rate = <SLEW_RATE_SLOW>; + io-standard = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO18"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO19"; + bias-disable; + schmitt-cmos = <PIN_INPUT_TYPE_CMOS>; + }; + }; + }; +}; + +uart1 { + ... + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; + ... + +}; -- 2.7.4 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 6/9] dt-bindings: spi: zynqmp: Move SPI node under zynqmp firmware 2018-11-16 23:56 [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core Jolly Shah ` (4 preceding siblings ...) 2018-11-16 23:56 ` [PATCH 5/9] dt-bindings: pinctrl: Add ZynqMP pin controller bindings Jolly Shah @ 2018-11-16 23:56 ` Jolly Shah 2018-11-16 23:56 ` [PATCH 7/9] dt-bindings: phy: Add dt bindings for ZynqMP PHY Jolly Shah ` (4 subsequent siblings) 10 siblings, 0 replies; 15+ messages in thread From: Jolly Shah @ 2018-11-16 23:56 UTC (permalink / raw) To: robh+dt, mark.rutland Cc: michal.simek, rajanv, nava.manne, linux-arm-kernel, linux-kernel, devicetree, Rajan Vaja, Jolly Shah From: Rajan Vaja <rajan.vaja@xilinx.com> SPI driver uses ZynqMP firmware interface and so it should be populated by firmware driver. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com> --- .../devicetree/bindings/spi/spi-zynqmp-qspi.txt | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt index 0f6d37f..767bb8e 100644 --- a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt +++ b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt @@ -14,12 +14,18 @@ Optional properties: - num-cs : Number of chip selects used. Example: - qspi: spi@ff0f0000 { - compatible = "xlnx,zynqmp-qspi-1.0"; - clock-names = "ref_clk", "pclk"; - clocks = <&misc_clk &misc_clk>; - interrupts = <0 15 4>; - interrupt-parent = <&gic>; - num-cs = <1>; - reg = <0x0 0xff0f0000 0x1000>,<0x0 0xc0000000 0x8000000>; +firmware { + zynqmp_firmware: zynqmp-firmware { + compatible = "xlnx,zynqmp-firmware"; + method = "smc"; + qspi: spi@ff0f0000 { + compatible = "xlnx,zynqmp-qspi-1.0"; + clock-names = "ref_clk", "pclk"; + clocks = <&misc_clk &misc_clk>; + interrupts = <0 15 4>; + interrupt-parent = <&gic>; + num-cs = <1>; + reg = <0x0 0xff0f0000 0x1000>,<0x0 0xc0000000 0x8000000>; + }; }; +}; -- 2.7.4 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 7/9] dt-bindings: phy: Add dt bindings for ZynqMP PHY 2018-11-16 23:56 [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core Jolly Shah ` (5 preceding siblings ...) 2018-11-16 23:56 ` [PATCH 6/9] dt-bindings: spi: zynqmp: Move SPI node under zynqmp firmware Jolly Shah @ 2018-11-16 23:56 ` Jolly Shah 2018-11-16 23:56 ` [PATCH 8/9] dt-bindings: remoteproc: Add Xilinx R5 rproc binding Jolly Shah ` (3 subsequent siblings) 10 siblings, 0 replies; 15+ messages in thread From: Jolly Shah @ 2018-11-16 23:56 UTC (permalink / raw) To: robh+dt, mark.rutland Cc: michal.simek, rajanv, nava.manne, linux-arm-kernel, linux-kernel, devicetree, Jolly Shah, Anurag Kumar Vulisha This patch adds the document describing dt bindings for ZynqMP PHY. ZynqMP SOC has a High Speed Processing System Gigabit Transceiver which provides PHY capabilties to USB, SATA, PCIE, Display Port and Ehernet SGMII controllers. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> --- .../devicetree/bindings/phy/phy-zynqmp.txt | 126 +++++++++++++++++++++ 1 file changed, 126 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-zynqmp.txt diff --git a/Documentation/devicetree/bindings/phy/phy-zynqmp.txt b/Documentation/devicetree/bindings/phy/phy-zynqmp.txt new file mode 100644 index 0000000..21cb722 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-zynqmp.txt @@ -0,0 +1,126 @@ +Xilinx ZynqMP PHY binding + +This binding describes a ZynqMP PHY device that is used to control ZynqMP +High Speed Gigabit Transceiver(GT). ZynqMP PS GTR provides four lanes +and are used by USB, SATA, PCIE, Display port and Ethernet SGMMI controllers. + +Required properties (controller (parent) node): +- compatible : Can be "xlnx,zynqmp-psgtr-v1.1" or "xlnx,zynqmp-psgtr" + "xlnx,zynqmp-psgtr-v1.1" has the lpd address mapping removed + +- reg : Address and length of register sets for each device in + "reg-names" +- reg-names : The names of the register addresses corresponding to the + registers filled in "reg": + - serdes: SERDES block register set + - siou: SIOU block register set + - lpd: Low power domain peripherals reset control + +Required nodes : A sub-node is required for each lane the controller + provides. + +Required properties (port (child) nodes): +lane0: +- #phy-cells : Should be 4 + Cell after port phandle is device type from: + - <PHY_TYPE_PCIE 0 LANE_NUM FREQUENCY> + - <PHY_TYPE_SATA 0 LANE_NUM FREQUENCY> + - <PHY_TYPE_USB3 0 LANE_NUM FREQUENCY> + - <PHY_TYPE_DP 1 LANE_NUM FREQUENCY> + - <PHY_TYPE_SGMII 0 LANE_NUM FREQUENCY> +lane1: +- #phy-cells : Should be 4 + Cell after port phandle is device type from: + - <PHY_TYPE_PCIE 1 LANE_NUM FREQUENCY> + - <PHY_TYPE_SATA 1 LANE_NUM FREQUENCY> + - <PHY_TYPE_USB3 0 LANE_NUM FREQUENCY> + - <PHY_TYPE_DP 0 LANE_NUM FREQUENCY> + - <PHY_TYPE_SGMII 1 LANE_NUM FREQUENCY> +lane2: +- #phy-cells : Should be 4 + Cell after port phandle is device type from: + - <PHY_TYPE_PCIE 2 LANE_NUM FREQUENCY> + - <PHY_TYPE_SATA 0 LANE_NUM FREQUENCY> + - <PHY_TYPE_USB3 0 LANE_NUM FREQUENCY> + - <PHY_TYPE_DP 1 LANE_NUM FREQUENC> + - <PHY_TYPE_SGMII 2 LANE_NUM FREQUENCY> +lane3: +- #phy-cells : Should be 4 + Cell after port phandle is device type from: + - <PHY_TYPE_PCIE 3 LANE_NUM FREQUENCY> + - <PHY_TYPE_SATA 1 LANE_NUM FREQUENCY> + - <PHY_TYPE_USB3 1 LANE_NUM FREQUENCY > + - <PHY_TYPE_DP 0 LANE_NUM FREQUENCY> + - <PHY_TYPE_SGMII 3 LANE_NUM FREQUENCY> + +Note: LANE_NUM : This determines which lane's reference clock is shared by controller. + FREQUENCY: This the clock frequency at which controller wants to operate. + + +Example: +firmware { + zynqmp_firmware: zynqmp-firmware { + compatible = "xlnx,zynqmp-firmware"; + method = "smc"; + + serdes: zynqmp_phy@fd400000 { + compatible = "xlnx,zynqmp-psgtr"; + status = "okay"; + reg = <0x0 0xfd400000 0x0 0x40000>, <0x0 0xfd3d0000 0x0 0x1000>, + <0x0 0xff5e0000 0x0 0x1000>; + reg-names = "serdes", "siou", "lpd"; + + lane0: lane@0 { + #phy-cells = <4>; + }; + lane1: lane@1 { + #phy-cells = <4>; + }; + lane2: lane@2 { + #phy-cells = <4>; + }; + lane3: lane@3 { + #phy-cells = <4>; + }; + }; + }; +}; + +Specifying phy control of devices +================================= + +Device nodes should specify the configuration required in their "phys" +property, containing a phandle to the phy port node and a device type. + +phys = <PHANDLE CONTROLLER_TYPE CONTROLLER_INSTANCE LANE_NUM LANE_FREQ>; + +PHANDLE = &lane0 or &lane1 or &lane2 or &lane3 +CONTROLLER_TYPE = PHY_TYPE_PCIE or PHY_TYPE_SATA or PHY_TYPE_USB + or PHY_TYPE_DP or PHY_TYPE_SGMII +CONTROLLER_INSTANCE = Depends on controller type used, can be any of + PHY_TYPE_PCIE : 0 or 1 or 2 or 3 + PHY_TYPE_SATA : 0 or 1 + PHY_TYPE_USB : 0 or 1 + PHY_TYPE_DP : 0 or 1 + PHY_TYPE_SGMII: 0 or 1 or 2 or 3 +LANE_NUM = Depends on which lane clock is used as ref clk, can be + 0 or 1 or 2 or 3 +LANE_FREQ = Frequency that controller can operate, can be any of + 19.2Mhz,20Mhz,24Mhz,26Mhz,27Mhz,28.4Mhz,40Mhz,52Mhz, + 100Mhz,108Mhz,125Mhz,135Mhz,150Mhz + +Example: + +#include <dt-bindings/phy/phy.h> + + usb@fe200000 { + ... + phys = <&lane2 PHY_TYPE_USB3 0 2 2600000>; + ... + }; + + ahci@fd0c0000 { + ... + phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; + ... + }; -- 2.7.4 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 8/9] dt-bindings: remoteproc: Add Xilinx R5 rproc binding 2018-11-16 23:56 [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core Jolly Shah ` (6 preceding siblings ...) 2018-11-16 23:56 ` [PATCH 7/9] dt-bindings: phy: Add dt bindings for ZynqMP PHY Jolly Shah @ 2018-11-16 23:56 ` Jolly Shah 2018-11-16 23:56 ` [PATCH 9/9] dt-bindings: fpga: Add binding doc for the afi config driver Jolly Shah ` (2 subsequent siblings) 10 siblings, 0 replies; 15+ messages in thread From: Jolly Shah @ 2018-11-16 23:56 UTC (permalink / raw) To: robh+dt, mark.rutland Cc: michal.simek, rajanv, nava.manne, linux-arm-kernel, linux-kernel, devicetree, Wendy Liang, Wendy Liang, Jolly Shah From: Wendy Liang <wendy.liang@xilinx.com> Add device tree binding for Xilinx Cortex-r5 remoteproc. Signed-off-by: Wendy Liang <jliang@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com> --- .../remoteproc/xlnx,zynqmp-r5-remoteproc.txt | 81 ++++++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5-remoteproc.txt diff --git a/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5-remoteproc.txt b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5-remoteproc.txt new file mode 100644 index 0000000..4831350 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5-remoteproc.txt @@ -0,0 +1,81 @@ +Xilinx ARM Cortex A53-R5 remoteproc driver +========================================== + +ZynqMP family of devices use two Cortex R5 processors to help with various +low power / real time tasks. + +This driver requires specific ZynqMP hardware design. + +ZynqMP R5 RemoteProc Device Node: +================================= +A zynqmp_r5_remoteproc device node is used to represent a R5 IP instance +within ZynqMP SoC. + +Required properties: +-------------------- + - compatible : Should be "xlnx,zynqmp-r5-remoteproc-1.0" + - reg : Address and length of the register set for the device. It + contains in the same order as described reg-names + - reg-names: Contain the register set names. + "tcm_a" and "tcm_b" for TCM memories. + If the user uses the remoteproc driver with the RPMsg kernel + driver,"ipi" for the IPI register used to communicate with RPU + is also required. + Otherwise, if user only uses the remoteproc driver to boot RPU + firmware, "ipi" is not required. + - tcm-pnode-id: TCM resources power nodes IDs which are used to request TCM + resources for the remoteproc driver to access. + - rpu-pnode-id : RPU power node id which is used by the remoteproc driver + to start RPU or shut it down. + +Optional properties: +-------------------- + - core_conf : R5 core configuration (valid string - split0 or split1 or + lock-step), default is lock-step. + - memory-region: memories regions for RPU executable and DMA memory. + - interrupts : Interrupt mapping for remoteproc IPI. It is required if the + user uses the remoteproc driver with the RPMsg kernel driver. + - interrupt-parent : Phandle for the interrupt controller. It is required if + the user uses the remoteproc driver with the RPMsg kernel + kernel driver. + +Example: +-------- + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + rproc_0_fw_reserved: rproc@3ed000000 { + compatible = "rproc-prog-memory"; + no-map; + reg = <0x0 0x3ed00000 0x0 0x40000>; + }; + rproc_0_dma_reserved: rproc@3ed400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0x0 0x3ed40000 0x0 0x80000>; + }; + }; + + firmware { + zynqmp_firmware: zynqmp-firmware { + compatible = "xlnx,zynqmp-firmware"; + method = "smc"; + + zynqmp-r5-remoteproc@0 { + compatible = "xlnx,zynqmp-r5-remoteproc-1.0"; + reg = <0x0 0xFFE00000 0x0 0x10000>, + <0x0 0xFFE20000 0x0 0x10000>, + <0x0 0xff340000 0x0 0x100>; + reg-names = "tcm_a", "tcm_b", "ipi"; + dma-ranges; + core_conf = "split0"; + memory-region = <&rproc_0_fw_reserved>, + <&rproc_0_dma_reserved>; + tcm-pnode-id = <0xf>, <0x10>; + rpu-pnode-id = <0x7>; + interrupt-parent = <&gic>; + interrupts = <0 29 4>; + } ; + }; + }; -- 2.7.4 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 9/9] dt-bindings: fpga: Add binding doc for the afi config driver 2018-11-16 23:56 [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core Jolly Shah ` (7 preceding siblings ...) 2018-11-16 23:56 ` [PATCH 8/9] dt-bindings: remoteproc: Add Xilinx R5 rproc binding Jolly Shah @ 2018-11-16 23:56 ` Jolly Shah 2018-11-26 21:39 ` [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core Jolly Shah 2018-12-04 22:06 ` Rob Herring 10 siblings, 0 replies; 15+ messages in thread From: Jolly Shah @ 2018-11-16 23:56 UTC (permalink / raw) To: robh+dt, mark.rutland Cc: michal.simek, rajanv, nava.manne, linux-arm-kernel, linux-kernel, devicetree, Jolly Shah, Shubhrajyoti Datta Add the binding document for the afi config driver. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com> --- .../devicetree/bindings/fpga/xlnx,afi-fpga.txt | 67 ++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,afi-fpga.txt diff --git a/Documentation/devicetree/bindings/fpga/xlnx,afi-fpga.txt b/Documentation/devicetree/bindings/fpga/xlnx,afi-fpga.txt new file mode 100644 index 0000000..9006e72 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/xlnx,afi-fpga.txt @@ -0,0 +1,67 @@ +Xilinx ZynqMp AFI interface Manager + +The Zynq UltraScale+ MPSoC Processing System core provides access from PL +masters to PS internal peripherals, and memory through AXI FIFO interface +(AFI) interfaces. + +Required properties: +-compatible: Should contain "xlnx,afi-fpga" +-config-afi: Pairs of <regid value > + +The possible values of regid and values are + regid: Regids of the register to be written possible values + 0- AFIFM0_RDCTRL + 1- AFIFM0_WRCTRL + 2- AFIFM1_RDCTRL + 3- AFIFM1_WRCTRL + 4- AFIFM2_RDCTRL + 5- AFIFM2_WRCTRL + 6- AFIFM3_RDCTRL + 7- AFIFM3_WRCTRL + 8- AFIFM4_RDCTRL + 9- AFIFM4_WRCTRL + 10- AFIFM5_RDCTRL + 11- AFIFM5_WRCTRL + 12- AFIFM6_RDCTRL + 13- AFIFM6_WRCTRL + 14- AFIFS + 15- AFIFS_SS2 +- value: Array of values to be written. + for FM0_RDCTRL(0) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled + for FM0_WRCTRL(1) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled + for FM1_RDCTRL(2) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled + for FM1_WRCTRL(3) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled + for FM2_RDCTRL(4) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled + for FM2_WRCTRL(5) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled + for FM3_RDCTRL(6) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled + for FM3_WRCTRL(7) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled + for FM4_RDCTRL(8) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled + for FM4_WRCTRL(9) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled + for FM5_RDCTRL(10) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled + for FM5_WRCTRL(11) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled + for FM6_RDCTRL(12) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled + for FM6_WRCTRL(13) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled + for AFI_FA(14) + dw_ss1_sel bits (11:10) + dw_ss0_sel bits (9:8) + 0x0: 32-bit AXI data width), + 0x1: 64-bit AXI data width, + 0x2: 128-bit AXI data + All other bits are 0 write ignored. + + for AFI_FA(15) selects for ss2AXI data width valid values + 0x000: 32-bit AXI data width), + 0x100: 64-bit AXI data width, + 0x200: 128-bit AXI data + +Example: +firmware { + zynqmp_firmware: zynqmp-firmware { + compatible = "xlnx,zynqmp-firmware"; + method = "smc"; + afi0: afi0 { + compatible = "xlnx,afi-fpga"; + config-afi = <0 2>, <1 1>, <2 1>; + }; + }; +}; -- 2.7.4 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* RE: [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core 2018-11-16 23:56 [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core Jolly Shah ` (8 preceding siblings ...) 2018-11-16 23:56 ` [PATCH 9/9] dt-bindings: fpga: Add binding doc for the afi config driver Jolly Shah @ 2018-11-26 21:39 ` Jolly Shah 2018-12-04 22:06 ` Rob Herring 10 siblings, 0 replies; 15+ messages in thread From: Jolly Shah @ 2018-11-26 21:39 UTC (permalink / raw) To: Jolly Shah, robh+dt, mark.rutland Cc: Michal Simek, Rajan Vaja, Nava kishore Manne, linux-arm-kernel, linux-kernel, devicetree Ping for comments > -----Original Message----- > From: Jolly Shah [mailto:jolly.shah@xilinx.com] > Sent: Friday, November 16, 2018 3:57 PM > To: robh+dt@kernel.org; mark.rutland@arm.com > Cc: Michal Simek <michals@xilinx.com>; Rajan Vaja <RAJANV@xilinx.com>; > Nava kishore Manne <navam@xilinx.com>; linux-arm- > kernel@lists.infradead.org; linux-kernel@vger.kernel.org; > devicetree@vger.kernel.org; Jolly Shah <JOLLYS@xilinx.com> > Subject: [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core > > Base firmware node and clock child node binding are part of mainline kernel. > This patchset adds documentation to describe rest of the firmware child node > bindings. > Complete firmware DT node example is shown below for ease of understanding: > > firmware { > zynqmp_firmware: zynqmp-firmware { > compatible = "xlnx,zynqmp-firmware"; > method = "smc"; > #power-domain-cells = <1>; > #reset-cells = <1>; > > zynqmp_clk: clock-controller { > #clock-cells = <1>; > compatible = "xlnx,zynqmp-clk"; > clocks = <&pss_ref_clk>, <&video_clk>, > <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>; > clock-names = "pss_ref_clk", "video_clk", > "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk"; > }; > > zynqmp_power: zynqmp-power { > compatible = "xlnx,zynqmp-power"; > interrupts = <0 35 4>; > }; > > nvmem_firmware { > compatible = "xlnx,zynqmp-nvmem-fw"; > #address-cells = <1>; > #size-cells = <1>; > > /* Data cells */ > soc_revision: soc_revision { > reg = <0x0 0x4>; > }; > }; > > afi0: afi0 { > compatible = "xlnx,afi-fpga"; > config-afi = <0 2>, <1 1>, <2 1>; > }; > > qspi: spi@ff0f0000 { > compatible = "xlnx,zynqmp-qspi-1.0"; > clock-names = "ref_clk", "pclk"; > clocks = <&misc_clk &misc_clk>; > interrupts = <0 15 4>; > interrupt-parent = <&gic>; > num-cs = <1>; > reg = <0x0 0xff0f0000 0x1000>,<0x0 0xc0000000 > 0x8000000>; > }; > > serdes: zynqmp_phy@fd400000 { > compatible = "xlnx,zynqmp-psgtr"; > status = "okay"; > reg = <0x0 0xfd400000 0x0 0x40000>, <0x0 0xfd3d0000 > 0x0 0x1000>, > <0x0 0xff5e0000 0x0 0x1000>; > reg-names = "serdes", "siou", "lpd"; > > lane0: lane@0 { > #phy-cells = <4>; > }; > lane1: lane@1 { > #phy-cells = <4>; > }; > lane2: lane@2 { > #phy-cells = <4>; > }; > lane3: lane@3 { > #phy-cells = <4>; > }; > }; > > pinctrl_uart1_default: uart1-default { > mux { > groups = "uart0_4_grp"; > function = "uart0"; > }; > > conf { > groups = "uart0_4_grp"; > slew-rate = <SLEW_RATE_SLOW>; > io-standard = <IO_STANDARD_LVCMOS18>; > }; > > conf-rx { > pins = "MIO18"; > bias-high-impedance; > }; > > conf-tx { > pins = "MIO19"; > bias-disable; > schmitt-cmos = <PIN_INPUT_TYPE_CMOS>; > }; > }; > zynqmp-r5-remoteproc@0 { > compatible = "xlnx,zynqmp-r5-remoteproc-1.0"; > reg = <0x0 0xFFE00000 0x0 0x10000>, > <0x0 0xFFE20000 0x0 0x10000>, > <0x0 0xff340000 0x0 0x100>; > reg-names = "tcm_a", "tcm_b", "ipi"; > dma-ranges; > core_conf = "split0"; > memory-region = <&rproc_0_fw_reserved>, > <&rproc_0_dma_reserved>; > tcm-pnode-id = <0xf>, <0x10>; > rpu-pnode-id = <0x7>; > interrupt-parent = <&gic>; > interrupts = <0 29 4>; > }; > }; > }; > > Jolly Shah (2): > dt-bindings: phy: Add dt bindings for ZynqMP PHY > dt-bindings: fpga: Add binding doc for the afi config driver > > Nava kishore Manne (2): > dt-bindings: reset: Add bindings for ZynqMP reset driver > dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver > > Rajan Vaja (4): > dt-bindings: power: Add ZynqMP power domain bindings > dt-bindings: soc: Add ZynqMP PM bindings > dt-bindings: pinctrl: Add ZynqMP pin controller bindings > dt-bindings: spi: zynqmp: Move SPI node under zynqmp firmware > > Wendy Liang (1): > dt-bindings: remoteproc: Add Xilinx R5 rproc binding > > .../devicetree/bindings/fpga/xlnx,afi-fpga.txt | 67 +++++ > .../bindings/nvmem/xlnx,zynqmp-nvmem.txt | 44 ++++ > .../devicetree/bindings/phy/phy-zynqmp.txt | 126 ++++++++++ > .../bindings/pinctrl/xlnx,zynqmp-pinctrl.txt | 272 +++++++++++++++++++++ > .../bindings/power/reset/xlnx,zynqmp-power.txt | 25 ++ > .../bindings/power/xlnx,zynqmp-genpd.txt | 34 +++ > .../remoteproc/xlnx,zynqmp-r5-remoteproc.txt | 81 ++++++ > .../bindings/reset/xlnx,zynqmp-reset.txt | 148 +++++++++++ > .../devicetree/bindings/spi/spi-zynqmp-qspi.txt | 22 +- > include/dt-bindings/power/xlnx-zynqmp-power.h | 39 +++ > 10 files changed, 850 insertions(+), 8 deletions(-) create mode 100644 > Documentation/devicetree/bindings/fpga/xlnx,afi-fpga.txt > create mode 100644 Documentation/devicetree/bindings/nvmem/xlnx,zynqmp- > nvmem.txt > create mode 100644 Documentation/devicetree/bindings/phy/phy-zynqmp.txt > create mode 100644 Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp- > pinctrl.txt > create mode 100644 > Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt > create mode 100644 Documentation/devicetree/bindings/power/xlnx,zynqmp- > genpd.txt > create mode 100644 > Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5- > remoteproc.txt > create mode 100644 Documentation/devicetree/bindings/reset/xlnx,zynqmp- > reset.txt > create mode 100644 include/dt-bindings/power/xlnx-zynqmp-power.h > > -- > 2.7.4 ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core 2018-11-16 23:56 [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core Jolly Shah ` (9 preceding siblings ...) 2018-11-26 21:39 ` [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core Jolly Shah @ 2018-12-04 22:06 ` Rob Herring 2018-12-05 20:29 ` Jolly Shah 10 siblings, 1 reply; 15+ messages in thread From: Rob Herring @ 2018-12-04 22:06 UTC (permalink / raw) To: Jolly Shah Cc: mark.rutland, michal.simek, rajanv, nava.manne, linux-arm-kernel, linux-kernel, devicetree, Jolly Shah On Fri, Nov 16, 2018 at 03:56:50PM -0800, Jolly Shah wrote: > Base firmware node and clock child node binding are part of mainline kernel. This patchset adds documentation to describe rest of the firmware child node bindings. > Complete firmware DT node example is shown below for ease of understanding: Shouldn't there be a fpga mgr node too? Called pcap IIRC. > > firmware { > zynqmp_firmware: zynqmp-firmware { > compatible = "xlnx,zynqmp-firmware"; > method = "smc"; > #power-domain-cells = <1>; > #reset-cells = <1>; > > zynqmp_clk: clock-controller { > #clock-cells = <1>; > compatible = "xlnx,zynqmp-clk"; > clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>; > clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk"; > }; > > zynqmp_power: zynqmp-power { > compatible = "xlnx,zynqmp-power"; > interrupts = <0 35 4>; > }; > > nvmem_firmware { > compatible = "xlnx,zynqmp-nvmem-fw"; > #address-cells = <1>; > #size-cells = <1>; > > /* Data cells */ > soc_revision: soc_revision { > reg = <0x0 0x4>; > }; > }; > > afi0: afi0 { > compatible = "xlnx,afi-fpga"; > config-afi = <0 2>, <1 1>, <2 1>; > }; > > qspi: spi@ff0f0000 { Why is this under firmware node? > compatible = "xlnx,zynqmp-qspi-1.0"; > clock-names = "ref_clk", "pclk"; > clocks = <&misc_clk &misc_clk>; > interrupts = <0 15 4>; > interrupt-parent = <&gic>; > num-cs = <1>; > reg = <0x0 0xff0f0000 0x1000>,<0x0 0xc0000000 0x8000000>; > }; > > serdes: zynqmp_phy@fd400000 { And this? > compatible = "xlnx,zynqmp-psgtr"; > status = "okay"; > reg = <0x0 0xfd400000 0x0 0x40000>, <0x0 0xfd3d0000 0x0 0x1000>, > <0x0 0xff5e0000 0x0 0x1000>; > reg-names = "serdes", "siou", "lpd"; > > lane0: lane@0 { > #phy-cells = <4>; > }; > lane1: lane@1 { > #phy-cells = <4>; > }; > lane2: lane@2 { > #phy-cells = <4>; > }; > lane3: lane@3 { > #phy-cells = <4>; > }; > }; > > pinctrl_uart1_default: uart1-default { This goes under a pinctrl node. > mux { > groups = "uart0_4_grp"; > function = "uart0"; > }; > > conf { > groups = "uart0_4_grp"; > slew-rate = <SLEW_RATE_SLOW>; > io-standard = <IO_STANDARD_LVCMOS18>; > }; > > conf-rx { > pins = "MIO18"; > bias-high-impedance; > }; > > conf-tx { > pins = "MIO19"; > bias-disable; > schmitt-cmos = <PIN_INPUT_TYPE_CMOS>; > }; > }; > zynqmp-r5-remoteproc@0 { Wrong unit-address and this doesn't belong here. > compatible = "xlnx,zynqmp-r5-remoteproc-1.0"; 'remoteproc' is what the h/w block is called? > reg = <0x0 0xFFE00000 0x0 0x10000>, > <0x0 0xFFE20000 0x0 0x10000>, > <0x0 0xff340000 0x0 0x100>; > reg-names = "tcm_a", "tcm_b", "ipi"; > dma-ranges; > core_conf = "split0"; > memory-region = <&rproc_0_fw_reserved>, > <&rproc_0_dma_reserved>; > tcm-pnode-id = <0xf>, <0x10>; > rpu-pnode-id = <0x7>; > interrupt-parent = <&gic>; > interrupts = <0 29 4>; > }; > }; > }; ^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core 2018-12-04 22:06 ` Rob Herring @ 2018-12-05 20:29 ` Jolly Shah 2018-12-05 22:20 ` Rob Herring 0 siblings, 1 reply; 15+ messages in thread From: Jolly Shah @ 2018-12-05 20:29 UTC (permalink / raw) To: Rob Herring Cc: mark.rutland, Michal Simek, Rajan Vaja, Nava kishore Manne, linux-arm-kernel, linux-kernel, devicetree Hi Rob, Thanks for the review. Please find my responses inline. Thanks, Jolly Shah > -----Original Message----- > From: Rob Herring [mailto:robh@kernel.org] > Sent: Tuesday, December 04, 2018 2:06 PM > To: Jolly Shah <JOLLYS@xilinx.com> > Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan Vaja > <RAJANV@xilinx.com>; Nava kishore Manne <navam@xilinx.com>; linux-arm- > kernel@lists.infradead.org; linux-kernel@vger.kernel.org; > devicetree@vger.kernel.org; Jolly Shah <JOLLYS@xilinx.com> > Subject: Re: [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core > > On Fri, Nov 16, 2018 at 03:56:50PM -0800, Jolly Shah wrote: > > Base firmware node and clock child node binding are part of mainline kernel. > This patchset adds documentation to describe rest of the firmware child node > bindings. > > Complete firmware DT node example is shown below for ease of > understanding: > > Shouldn't there be a fpga mgr node too? Called pcap IIRC. > [Jolly] As you suggested, we only added child nodes if the sub-functions have their own resources (clks, irqs, etc.). FPGA doesn't have any resources so not added . Firmware driver would still register it as mfd device to instantiate the driver. > > > > firmware { > > zynqmp_firmware: zynqmp-firmware { > > compatible = "xlnx,zynqmp-firmware"; > > method = "smc"; > > #power-domain-cells = <1>; > > #reset-cells = <1>; > > > > zynqmp_clk: clock-controller { > > #clock-cells = <1>; > > compatible = "xlnx,zynqmp-clk"; > > clocks = <&pss_ref_clk>, <&video_clk>, > <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>; > > clock-names = "pss_ref_clk", "video_clk", > "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk"; > > }; > > > > zynqmp_power: zynqmp-power { > > compatible = "xlnx,zynqmp-power"; > > interrupts = <0 35 4>; > > }; > > > > nvmem_firmware { > > compatible = "xlnx,zynqmp-nvmem-fw"; > > #address-cells = <1>; > > #size-cells = <1>; > > > > /* Data cells */ > > soc_revision: soc_revision { > > reg = <0x0 0x4>; > > }; > > }; > > > > afi0: afi0 { > > compatible = "xlnx,afi-fpga"; > > config-afi = <0 2>, <1 1>, <2 1>; > > }; > > > > qspi: spi@ff0f0000 { > > Why is this under firmware node? [Jolly] Qspi is a user of eemi API provided by firmware node to perform privileged register writes. Alternatively, we can keep such user nodes outside of firmware node and keep nodes which firmware is provider for like clock, reset, pins and power. Please suggest. > > > compatible = "xlnx,zynqmp-qspi-1.0"; > > clock-names = "ref_clk", "pclk"; > > clocks = <&misc_clk &misc_clk>; > > interrupts = <0 15 4>; > > interrupt-parent = <&gic>; > > num-cs = <1>; > > reg = <0x0 0xff0f0000 0x1000>,<0x0 0xc0000000 > 0x8000000>; > > }; > > > > serdes: zynqmp_phy@fd400000 { > > And this? [Jolly] Same as above. > > > compatible = "xlnx,zynqmp-psgtr"; > > status = "okay"; > > reg = <0x0 0xfd400000 0x0 0x40000>, <0x0 0xfd3d0000 > 0x0 0x1000>, > > <0x0 0xff5e0000 0x0 0x1000>; > > reg-names = "serdes", "siou", "lpd"; > > > > lane0: lane@0 { > > #phy-cells = <4>; > > }; > > lane1: lane@1 { > > #phy-cells = <4>; > > }; > > lane2: lane@2 { > > #phy-cells = <4>; > > }; > > lane3: lane@3 { > > #phy-cells = <4>; > > }; > > }; > > > > pinctrl_uart1_default: uart1-default { > > This goes under a pinctrl node. [Jolly] Pincontrol node is not added as it doesn't have any resources. As I understand, you suggest to still add pincontrol node and this under pincontrol node. > > > mux { > > groups = "uart0_4_grp"; > > function = "uart0"; > > }; > > > > conf { > > groups = "uart0_4_grp"; > > slew-rate = <SLEW_RATE_SLOW>; > > io-standard = <IO_STANDARD_LVCMOS18>; > > }; > > > > conf-rx { > > pins = "MIO18"; > > bias-high-impedance; > > }; > > > > conf-tx { > > pins = "MIO19"; > > bias-disable; > > schmitt-cmos = <PIN_INPUT_TYPE_CMOS>; > > }; > > }; > > zynqmp-r5-remoteproc@0 { > > Wrong unit-address and this doesn't belong here. [Jolly] Again as it is one of the user of firmware APIs, its kept here. Alternatively, we can keep such user nodes outside of firmware node and keep nodes which firmware is provider for like clock, reset, pins and power. Please suggest. > > > compatible = "xlnx,zynqmp-r5-remoteproc-1.0"; > > 'remoteproc' is what the h/w block is called? [Jolly] The hw block is called rpu. Thanks, Jolly Shah > > > reg = <0x0 0xFFE00000 0x0 0x10000>, > > <0x0 0xFFE20000 0x0 0x10000>, > > <0x0 0xff340000 0x0 0x100>; > > reg-names = "tcm_a", "tcm_b", "ipi"; > > dma-ranges; > > core_conf = "split0"; > > memory-region = <&rproc_0_fw_reserved>, > > <&rproc_0_dma_reserved>; > > tcm-pnode-id = <0xf>, <0x10>; > > rpu-pnode-id = <0x7>; > > interrupt-parent = <&gic>; > > interrupts = <0 29 4>; > > }; > > }; > > }; ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core 2018-12-05 20:29 ` Jolly Shah @ 2018-12-05 22:20 ` Rob Herring 2018-12-06 23:08 ` Jolly Shah 0 siblings, 1 reply; 15+ messages in thread From: Rob Herring @ 2018-12-05 22:20 UTC (permalink / raw) To: Jolly Shah Cc: mark.rutland, devicetree, Nava kishore Manne, linux-kernel, Rajan Vaja, Michal Simek, linux-arm-kernel On Wed, Dec 05, 2018 at 08:29:36PM +0000, Jolly Shah wrote: > Hi Rob, > > Thanks for the review. Please find my responses inline. You need to fix your mail client to wrap lines. > Thanks, > Jolly Shah > > > -----Original Message----- > > From: Rob Herring [mailto:robh@kernel.org] > > Sent: Tuesday, December 04, 2018 2:06 PM > > To: Jolly Shah <JOLLYS@xilinx.com> > > Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan Vaja > > <RAJANV@xilinx.com>; Nava kishore Manne <navam@xilinx.com>; linux-arm- > > kernel@lists.infradead.org; linux-kernel@vger.kernel.org; > > devicetree@vger.kernel.org; Jolly Shah <JOLLYS@xilinx.com> > > Subject: Re: [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core > > > > On Fri, Nov 16, 2018 at 03:56:50PM -0800, Jolly Shah wrote: > > > Base firmware node and clock child node binding are part of mainline kernel. > > This patchset adds documentation to describe rest of the firmware child node > > bindings. > > > Complete firmware DT node example is shown below for ease of > > understanding: > > > > Shouldn't there be a fpga mgr node too? Called pcap IIRC. > > > [Jolly] As you suggested, we only added child nodes if the > sub-functions have their own resources (clks, irqs, etc.). FPGA doesn't > have any resources so not added . Firmware driver would still register > it as mfd device to instantiate the driver. Okay, but won't their need to be child devices for > > > > > > > firmware { > > > zynqmp_firmware: zynqmp-firmware { > > > compatible = "xlnx,zynqmp-firmware"; > > > method = "smc"; > > > #power-domain-cells = <1>; > > > #reset-cells = <1>; > > > > > > zynqmp_clk: clock-controller { > > > #clock-cells = <1>; > > > compatible = "xlnx,zynqmp-clk"; > > > clocks = <&pss_ref_clk>, <&video_clk>, > > <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>; > > > clock-names = "pss_ref_clk", "video_clk", > > "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk"; > > > }; > > > > > > zynqmp_power: zynqmp-power { > > > compatible = "xlnx,zynqmp-power"; > > > interrupts = <0 35 4>; > > > }; > > > > > > nvmem_firmware { > > > compatible = "xlnx,zynqmp-nvmem-fw"; > > > #address-cells = <1>; > > > #size-cells = <1>; > > > > > > /* Data cells */ > > > soc_revision: soc_revision { > > > reg = <0x0 0x4>; > > > }; > > > }; > > > > > > afi0: afi0 { > > > compatible = "xlnx,afi-fpga"; > > > config-afi = <0 2>, <1 1>, <2 1>; > > > }; > > > > > > qspi: spi@ff0f0000 { > > > > Why is this under firmware node? > [Jolly] Qspi is a user of eemi API provided by firmware node to > perform privileged register writes. Alternatively, we can keep such > user nodes outside of firmware node and keep nodes which firmware is > provider for like clock, reset, pins and power. > Please suggest. Child nodes of the firmware should be providers, not consumers (of the firmware). If you had a firmware interface to that provided a SPI interface, then it would be here. But just having a special mechanism to access the registers. > > > > > compatible = "xlnx,zynqmp-qspi-1.0"; If this same block works with unprivileged accesses, then you will need some way to distinguish that. > > > clock-names = "ref_clk", "pclk"; > > > clocks = <&misc_clk &misc_clk>; > > > interrupts = <0 15 4>; > > > interrupt-parent = <&gic>; > > > num-cs = <1>; > > > reg = <0x0 0xff0f0000 0x1000>,<0x0 0xc0000000 > > 0x8000000>; > > > }; > > > > > > serdes: zynqmp_phy@fd400000 { > > > > And this? > > [Jolly] Same as above. > > > > > > compatible = "xlnx,zynqmp-psgtr"; > > > status = "okay"; > > > reg = <0x0 0xfd400000 0x0 0x40000>, <0x0 0xfd3d0000 > > 0x0 0x1000>, > > > <0x0 0xff5e0000 0x0 0x1000>; > > > reg-names = "serdes", "siou", "lpd"; > > > > > > lane0: lane@0 { > > > #phy-cells = <4>; > > > }; > > > lane1: lane@1 { > > > #phy-cells = <4>; > > > }; > > > lane2: lane@2 { > > > #phy-cells = <4>; > > > }; > > > lane3: lane@3 { > > > #phy-cells = <4>; > > > }; > > > }; > > > > > > pinctrl_uart1_default: uart1-default { > > > > This goes under a pinctrl node. > [Jolly] Pincontrol node is not added as it doesn't have any > resources. As I understand, you suggest to still add pincontrol node > and this under pincontrol node. These nodes are resources, so yes you should have a child here. > > > > > > mux { > > > groups = "uart0_4_grp"; > > > function = "uart0"; > > > }; > > > > > > conf { > > > groups = "uart0_4_grp"; > > > slew-rate = <SLEW_RATE_SLOW>; > > > io-standard = <IO_STANDARD_LVCMOS18>; > > > }; > > > > > > conf-rx { > > > pins = "MIO18"; > > > bias-high-impedance; > > > }; > > > > > > conf-tx { > > > pins = "MIO19"; > > > bias-disable; > > > schmitt-cmos = <PIN_INPUT_TYPE_CMOS>; > > > }; > > > }; > > > zynqmp-r5-remoteproc@0 { > > > > Wrong unit-address and this doesn't belong here. > [Jolly] Again as it is one of the user of firmware APIs, its kept > here. Alternatively, we can keep such user nodes outside of firmware > node and keep nodes which firmware is provider for like clock, reset, > pins and power. > Please suggest. Yes, it should be outside this. > > > > > compatible = "xlnx,zynqmp-r5-remoteproc-1.0"; > > > > 'remoteproc' is what the h/w block is called? > > [Jolly] The hw block is called rpu. Then call it that in the DT. Rob ^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core 2018-12-05 22:20 ` Rob Herring @ 2018-12-06 23:08 ` Jolly Shah 0 siblings, 0 replies; 15+ messages in thread From: Jolly Shah @ 2018-12-06 23:08 UTC (permalink / raw) To: Rob Herring Cc: mark.rutland, devicetree, Nava kishore Manne, linux-kernel, Rajan Vaja, Michal Simek, linux-arm-kernel Hi Rob, > -----Original Message----- > From: Rob Herring [mailto:robh@kernel.org] > Sent: Wednesday, December 05, 2018 2:21 PM > To: Jolly Shah <JOLLYS@xilinx.com> > Cc: mark.rutland@arm.com; devicetree@vger.kernel.org; Nava kishore Manne > <navam@xilinx.com>; linux-kernel@vger.kernel.org; Rajan Vaja > <RAJANV@xilinx.com>; Michal Simek <michals@xilinx.com>; linux-arm- > kernel@lists.infradead.org > Subject: Re: [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core > > On Wed, Dec 05, 2018 at 08:29:36PM +0000, Jolly Shah wrote: > > Hi Rob, > > > > Thanks for the review. Please find my responses inline. > > You need to fix your mail client to wrap lines. Thanks I will. > > > Thanks, > > Jolly Shah > > > > > -----Original Message----- > > > From: Rob Herring [mailto:robh@kernel.org] > > > Sent: Tuesday, December 04, 2018 2:06 PM > > > To: Jolly Shah <JOLLYS@xilinx.com> > > > Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan Vaja > > > <RAJANV@xilinx.com>; Nava kishore Manne <navam@xilinx.com>; linux- > arm- > > > kernel@lists.infradead.org; linux-kernel@vger.kernel.org; > > > devicetree@vger.kernel.org; Jolly Shah <JOLLYS@xilinx.com> > > > Subject: Re: [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP > core > > > > > > On Fri, Nov 16, 2018 at 03:56:50PM -0800, Jolly Shah wrote: > > > > Base firmware node and clock child node binding are part of mainline > kernel. > > > This patchset adds documentation to describe rest of the firmware child > node > > > bindings. > > > > Complete firmware DT node example is shown below for ease of > > > understanding: > > > > > > Shouldn't there be a fpga mgr node too? Called pcap IIRC. > > > > > [Jolly] As you suggested, we only added child nodes if the > > sub-functions have their own resources (clks, irqs, etc.). FPGA doesn't > > have any resources so not added . Firmware driver would still register > > it as mfd device to instantiate the driver. > > Okay, but won't their need to be child devices for There are no fpga child devices. Should it be moved out? > > > > > > > > > > > > firmware { > > > > zynqmp_firmware: zynqmp-firmware { > > > > compatible = "xlnx,zynqmp-firmware"; > > > > method = "smc"; > > > > #power-domain-cells = <1>; > > > > #reset-cells = <1>; > > > > > > > > zynqmp_clk: clock-controller { > > > > #clock-cells = <1>; > > > > compatible = "xlnx,zynqmp-clk"; > > > > clocks = <&pss_ref_clk>, <&video_clk>, > > > <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>; > > > > clock-names = "pss_ref_clk", "video_clk", > > > "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk"; > > > > }; > > > > > > > > zynqmp_power: zynqmp-power { > > > > compatible = "xlnx,zynqmp-power"; > > > > interrupts = <0 35 4>; > > > > }; > > > > > > > > nvmem_firmware { > > > > compatible = "xlnx,zynqmp-nvmem-fw"; > > > > #address-cells = <1>; > > > > #size-cells = <1>; > > > > > > > > /* Data cells */ > > > > soc_revision: soc_revision { > > > > reg = <0x0 0x4>; > > > > }; > > > > }; > > > > > > > > afi0: afi0 { > > > > compatible = "xlnx,afi-fpga"; > > > > config-afi = <0 2>, <1 1>, <2 1>; > > > > }; > > > > > > > > qspi: spi@ff0f0000 { > > > > > > Why is this under firmware node? > > [Jolly] Qspi is a user of eemi API provided by firmware node to > > perform privileged register writes. Alternatively, we can keep such > > user nodes outside of firmware node and keep nodes which firmware is > > provider for like clock, reset, pins and power. > > Please suggest. > > Child nodes of the firmware should be providers, not consumers (of the > firmware). If you had a firmware interface to that provided a SPI > interface, then it would be here. But just having a special mechanism to > access the registers. Ok got it. So will move it out. > > > > > > > > compatible = "xlnx,zynqmp-qspi-1.0"; > > If this same block works with unprivileged accesses, then you will need > some way to distinguish that. > > > > > clock-names = "ref_clk", "pclk"; > > > > clocks = <&misc_clk &misc_clk>; > > > > interrupts = <0 15 4>; > > > > interrupt-parent = <&gic>; > > > > num-cs = <1>; > > > > reg = <0x0 0xff0f0000 0x1000>,<0x0 0xc0000000 > > > 0x8000000>; > > > > }; > > > > > > > > serdes: zynqmp_phy@fd400000 { > > > > > > And this? > > > > [Jolly] Same as above. > > > > > > > > > compatible = "xlnx,zynqmp-psgtr"; > > > > status = "okay"; > > > > reg = <0x0 0xfd400000 0x0 0x40000>, <0x0 0xfd3d0000 > > > 0x0 0x1000>, > > > > <0x0 0xff5e0000 0x0 0x1000>; > > > > reg-names = "serdes", "siou", "lpd"; > > > > > > > > lane0: lane@0 { > > > > #phy-cells = <4>; > > > > }; > > > > lane1: lane@1 { > > > > #phy-cells = <4>; > > > > }; > > > > lane2: lane@2 { > > > > #phy-cells = <4>; > > > > }; > > > > lane3: lane@3 { > > > > #phy-cells = <4>; > > > > }; > > > > }; > > > > > > > > pinctrl_uart1_default: uart1-default { > > > > > > This goes under a pinctrl node. > > [Jolly] Pincontrol node is not added as it doesn't have any > > resources. As I understand, you suggest to still add pincontrol node > > and this under pincontrol node. > > These nodes are resources, so yes you should have a child here. Got it. Will add pinctrl node along with below resources. > > > > > > > > > mux { > > > > groups = "uart0_4_grp"; > > > > function = "uart0"; > > > > }; > > > > > > > > conf { > > > > groups = "uart0_4_grp"; > > > > slew-rate = <SLEW_RATE_SLOW>; > > > > io-standard = <IO_STANDARD_LVCMOS18>; > > > > }; > > > > > > > > conf-rx { > > > > pins = "MIO18"; > > > > bias-high-impedance; > > > > }; > > > > > > > > conf-tx { > > > > pins = "MIO19"; > > > > bias-disable; > > > > schmitt-cmos = <PIN_INPUT_TYPE_CMOS>; > > > > }; > > > > }; > > > > zynqmp-r5-remoteproc@0 { > > > > > > Wrong unit-address and this doesn't belong here. > > [Jolly] Again as it is one of the user of firmware APIs, its kept > > here. Alternatively, we can keep such user nodes outside of firmware > > node and keep nodes which firmware is provider for like clock, reset, > > pins and power. > > Please suggest. > > Yes, it should be outside this. Ok. > > > > > > > > compatible = "xlnx,zynqmp-r5-remoteproc-1.0"; > > > > > > 'remoteproc' is what the h/w block is called? > > > > [Jolly] The hw block is called rpu. > > Then call it that in the DT. Ok. Thanks, Jolly Shah > > Rob ^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2018-12-06 23:08 UTC | newest] Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-11-16 23:56 [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core Jolly Shah 2018-11-16 23:56 ` [PATCH 1/9] dt-bindings: power: Add ZynqMP power domain bindings Jolly Shah 2018-11-16 23:56 ` [PATCH 2/9] dt-bindings: soc: Add ZynqMP PM bindings Jolly Shah 2018-11-16 23:56 ` [PATCH 3/9] dt-bindings: reset: Add bindings for ZynqMP reset driver Jolly Shah 2018-11-16 23:56 ` [PATCH 4/9] dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver Jolly Shah 2018-11-16 23:56 ` [PATCH 5/9] dt-bindings: pinctrl: Add ZynqMP pin controller bindings Jolly Shah 2018-11-16 23:56 ` [PATCH 6/9] dt-bindings: spi: zynqmp: Move SPI node under zynqmp firmware Jolly Shah 2018-11-16 23:56 ` [PATCH 7/9] dt-bindings: phy: Add dt bindings for ZynqMP PHY Jolly Shah 2018-11-16 23:56 ` [PATCH 8/9] dt-bindings: remoteproc: Add Xilinx R5 rproc binding Jolly Shah 2018-11-16 23:56 ` [PATCH 9/9] dt-bindings: fpga: Add binding doc for the afi config driver Jolly Shah 2018-11-26 21:39 ` [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core Jolly Shah 2018-12-04 22:06 ` Rob Herring 2018-12-05 20:29 ` Jolly Shah 2018-12-05 22:20 ` Rob Herring 2018-12-06 23:08 ` Jolly Shah
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