[PATCH v4 0/8] drm/msm/dsi: Get PHY ref clocks from the DT

[PATCH v4 0/8] drm/msm/dsi: Get PHY ref clocks from the DT

[Matthias Kaehlcke]

The MSM DSI PHY drivers currently hardcode the name and the rate of
the PHY ref clock. Get the ref clock from the device tree instead.

Note: testing of this series was limited to SDM845 and the 10nm PHY

Major changes in v4:
- always use parent rate for 28nm and 28nm 8960 PHYs

Major changes in v3:
- keep supporting DTs without ref clock for the 28nm and the 28nm
  8960 PHYs
- added patch to add ref clock to qcom-apq8064.dtsi

Major changes in v2:
- apply to all MSM DSI PHY drivers, not only 10nm

Matthias Kaehlcke (8):
  dt-bindings: msm/dsi: Add ref clock for PHYs
  drm/msm/dsi: 28nm 8960 PHY: Get ref clock from the DT
  drm/msm/dsi: 28nm PHY: Get ref clock from the DT
  drm/msm/dsi: 14nm PHY: Get ref clock from the DT
  drm/msm/dsi: 10nm PHY: Get ref clock from the DT
  arm64: dts: qcom: msm8916: Set 'xo_board' as ref clock of the DSI PHY
  arm64: dts: sdm845: Set 'bi_tcxo' as ref clock of the DSI PHYs
  ARM: dts: qcom-apq8064: Set 'xo_board' as ref clock of the DSI PHY

 .../devicetree/bindings/display/msm/dsi.txt   |  1 +
 arch/arm/boot/dts/qcom-apq8064.dtsi           |  5 +--
 arch/arm64/boot/dts/qcom/msm8916.dtsi         |  5 +--
 arch/arm64/boot/dts/qcom/sdm845.dtsi          | 10 +++---
 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c    | 13 ++++++-
 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c    | 16 +++++++--
 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c    | 36 +++++++++++++------
 .../gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c   | 24 ++++++++++---
 8 files changed, 82 insertions(+), 28 deletions(-)

-- 
2.20.0.rc1.387.gf8505762e3-goog

[PATCH v4 1/8] dt-bindings: msm/dsi: Add ref clock for PHYs

[Matthias Kaehlcke]

Allow the PHY drivers to get the ref clock from the DT.

Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
---
Chnages in v4:
- added "Reviewed-by" tags from Stephen and Doug

Changes in v3:
- added note that the ref clock is only required for new DTS
  files/entries

Changes in v2:
- add the ref clock for all PHYs, not only the 10nm one
- updated commit message
---
 Documentation/devicetree/bindings/display/msm/dsi.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt
index dfc743219bd88..9ae9469427207 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi.txt
+++ b/Documentation/devicetree/bindings/display/msm/dsi.txt
@@ -106,6 +106,7 @@ Required properties:
 - clocks: Phandles to device clocks. See [1] for details on clock bindings.
 - clock-names: the following clocks are required:
   * "iface"
+  * "ref" (only required for new DTS files/entries)
   For 28nm HPM/LP, 28nm 8960 PHYs:
 - vddio-supply: phandle to vdd-io regulator device node
   For 20nm PHY:
-- 
2.20.0.rc1.387.gf8505762e3-goog

[PATCH v4 2/8] drm/msm/dsi: 28nm 8960 PHY: Get ref clock from the DT

[Matthias Kaehlcke]

Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.

Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
---
Changes in v4:
- always use parent rate in dsi_pll_28nm_clk_set_rate()
- pass name of VCO ref clock to pll_28nm_register() instead of
  storing it in a struct field
- updated commit message

Changes in v3:
- use default name and rate if the ref clock is not specified
  in the DT
- store vco_ref_clk_name instead of vco_ref_clk
- fixed check for EPROBE_DEFER
- renamed VCO_REF_CLK_RATE to VCO_REF_CLK_DEFAULT_RATE

Changes in v2:
- patch added to the series
---
 .../gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c   | 24 +++++++++++++++----
 1 file changed, 19 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
index 49008451085b8..76e5188169b91 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
@@ -47,7 +47,6 @@
 
 #define NUM_PROVIDED_CLKS	2
 
-#define VCO_REF_CLK_RATE	27000000
 #define VCO_MIN_RATE		600000000
 #define VCO_MAX_RATE		1200000000
 
@@ -125,7 +124,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
 	DBG("rate=%lu, parent's=%lu", rate, parent_rate);
 
 	temp = rate / 10;
-	val = VCO_REF_CLK_RATE / 10;
+	val = parent_rate / 10;
 	fb_divider = (temp * VCO_PREF_DIV_RATIO) / val;
 	fb_divider = fb_divider / 2 - 1;
 	pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1,
@@ -406,11 +405,12 @@ static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll)
 					pll_28nm->clks, pll_28nm->num_clks);
 }
 
-static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
+static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm,
+			     const char *ref_clk_name)
 {
 	char *clk_name, *parent_name, *vco_name;
 	struct clk_init_data vco_init = {
-		.parent_names = (const char *[]){ "pxo" },
+		.parent_names = &ref_clk_name,
 		.num_parents = 1,
 		.flags = CLK_IGNORE_UNUSED,
 		.ops = &clk_ops_dsi_pll_28nm_vco,
@@ -494,6 +494,8 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct platform_device *pdev,
 {
 	struct dsi_pll_28nm *pll_28nm;
 	struct msm_dsi_pll *pll;
+	struct clk *vco_ref_clk;
+	const char *vco_ref_clk_name;
 	int ret;
 
 	if (!pdev)
@@ -506,6 +508,18 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct platform_device *pdev,
 	pll_28nm->pdev = pdev;
 	pll_28nm->id = id + 1;
 
+	vco_ref_clk = devm_clk_get(&pdev->dev, "ref");
+	if (!IS_ERR(vco_ref_clk)) {
+		vco_ref_clk_name = __clk_get_name(vco_ref_clk);
+	} else {
+		ret = PTR_ERR(vco_ref_clk);
+		if (ret == -EPROBE_DEFER)
+			return ERR_PTR(ret);
+
+		dev_warn(&pdev->dev, "'ref' clock is not specified, using default name\n");
+		vco_ref_clk_name = "pxo";
+	}
+
 	pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
 	if (IS_ERR_OR_NULL(pll_28nm->mmio)) {
 		dev_err(&pdev->dev, "%s: failed to map pll base\n", __func__);
@@ -524,7 +538,7 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct platform_device *pdev,
 	pll->en_seq_cnt = 1;
 	pll->enable_seqs[0] = dsi_pll_28nm_enable_seq;
 
-	ret = pll_28nm_register(pll_28nm);
+	ret = pll_28nm_register(pll_28nm, vco_ref_clk_name);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to register PLL: %d\n", ret);
 		return ERR_PTR(ret);
-- 
2.20.0.rc1.387.gf8505762e3-goog

[PATCH v4 3/8] drm/msm/dsi: 28nm PHY: Get ref clock from the DT

[Matthias Kaehlcke]

Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.

Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
---
Changes in v4:
- always use parent rate in dsi_pll_28nm_clk_set_rate() and
   dsi_pll_28nm_clk_recalc_rate()
- pass name of VCO ref clock to pll_28nm_register() instead of
  storing it in a struct field
- updated commit message

Changes in v3:
- use default name and rate if the ref clock is not specified
  in the DT
- store vco_ref_clk_name instead of vco_ref_clk
- dsi_pll_28nm_clk_set_rate: changed data type of ref_clk_rate to
  unsigned long
- fixed check for EPROBE_DEFER
- renamed VCO_REF_CLK_RATE to VCO_REF_CLK_DEFAULT_RATE

Changes in v2:
- patch added to the series
---
 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c | 36 +++++++++++++++-------
 1 file changed, 25 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
index 26e3a01a99c2b..7777340b03e8d 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
@@ -40,7 +40,6 @@
 
 #define NUM_PROVIDED_CLKS		2
 
-#define VCO_REF_CLK_RATE		19200000
 #define VCO_MIN_RATE			350000000
 #define VCO_MAX_RATE			750000000
 
@@ -166,17 +165,17 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
 	pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70);
 	pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15);
 
-	rem = rate % VCO_REF_CLK_RATE;
+	rem = rate % parent_rate;
 	if (rem) {
 		refclk_cfg = DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR;
 		frac_n_mode = 1;
-		div_fbx1000 = rate / (VCO_REF_CLK_RATE / 500);
-		gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 500);
+		div_fbx1000 = rate / (parent_rate / 500);
+		gen_vco_clk = div_fbx1000 * (parent_rate / 500);
 	} else {
 		refclk_cfg = 0x0;
 		frac_n_mode = 0;
-		div_fbx1000 = rate / (VCO_REF_CLK_RATE / 1000);
-		gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 1000);
+		div_fbx1000 = rate / (parent_rate / 1000);
+		gen_vco_clk = div_fbx1000 * (parent_rate / 1000);
 	}
 
 	DBG("refclk_cfg = %d", refclk_cfg);
@@ -265,7 +264,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
 	void __iomem *base = pll_28nm->mmio;
 	u32 sdm0, doubler, sdm_byp_div;
 	u32 sdm_dc_off, sdm_freq_seed, sdm2, sdm3;
-	u32 ref_clk = VCO_REF_CLK_RATE;
+	u32 ref_clk = parent_rate;
 	unsigned long vco_rate;
 
 	VERB("parent_rate=%lu", parent_rate);
@@ -273,7 +272,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
 	/* Check to see if the ref clk doubler is enabled */
 	doubler = pll_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) &
 			DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR;
-	ref_clk += (doubler * VCO_REF_CLK_RATE);
+	ref_clk += (doubler * ref_clk);
 
 	/* see if it is integer mode or sdm mode */
 	sdm0 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0);
@@ -514,11 +513,12 @@ static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll)
 	pll_28nm->clk_data.clk_num = 0;
 }
 
-static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
+static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm,
+			     const char *ref_clk_name)
 {
 	char clk_name[32], parent1[32], parent2[32], vco_name[32];
 	struct clk_init_data vco_init = {
-		.parent_names = (const char *[]){ "xo" },
+		.parent_names = &ref_clk_name,
 		.num_parents = 1,
 		.name = vco_name,
 		.flags = CLK_IGNORE_UNUSED,
@@ -593,6 +593,8 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev,
 {
 	struct dsi_pll_28nm *pll_28nm;
 	struct msm_dsi_pll *pll;
+	struct clk *vco_ref_clk;
+	const char *vco_ref_clk_name;
 	int ret;
 
 	if (!pdev)
@@ -605,6 +607,18 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev,
 	pll_28nm->pdev = pdev;
 	pll_28nm->id = id;
 
+	vco_ref_clk = devm_clk_get(&pdev->dev, "ref");
+	if (!IS_ERR(vco_ref_clk)) {
+		vco_ref_clk_name = __clk_get_name(vco_ref_clk);
+	} else {
+		ret = PTR_ERR(vco_ref_clk);
+		if (ret == -EPROBE_DEFER)
+			ERR_PTR(ret);
+
+		dev_warn(&pdev->dev, "'ref' clock is not specified, using default name\n");
+		vco_ref_clk_name = "xo";
+	}
+
 	pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
 	if (IS_ERR_OR_NULL(pll_28nm->mmio)) {
 		dev_err(&pdev->dev, "%s: failed to map pll base\n", __func__);
@@ -637,7 +651,7 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev,
 		return ERR_PTR(-EINVAL);
 	}
 
-	ret = pll_28nm_register(pll_28nm);
+	ret = pll_28nm_register(pll_28nm, vco_ref_clk_name);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to register PLL: %d\n", ret);
 		return ERR_PTR(ret);
-- 
2.20.0.rc1.387.gf8505762e3-goog

[PATCH v4 4/8] drm/msm/dsi: 14nm PHY: Get ref clock from the DT

[Matthias Kaehlcke]

Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.

Note: This change could break old out-of-tree DTS files that
use the 14nm PHY.

Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
---
Changes in v4:
- none

Changes in v3:
- fixed check for EPROBE_DEFER
- added note to commit message about breaking old DTS files
- added 'Reviewed-by: Douglas Anderson <dianders@chromium.org>' tag

Changes in v2:
- patch added to the series
---
 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
index 71fe60e5f01f1..032bf3e8614bd 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
@@ -40,7 +40,6 @@
 
 #define NUM_PROVIDED_CLKS		2
 
-#define VCO_REF_CLK_RATE		19200000
 #define VCO_MIN_RATE			1300000000UL
 #define VCO_MAX_RATE			2600000000UL
 
@@ -139,6 +138,7 @@ struct dsi_pll_14nm {
 	/* protects REG_DSI_14nm_PHY_CMN_CLK_CFG0 register */
 	spinlock_t postdiv_lock;
 
+	struct clk *vco_ref_clk;
 	u64 vco_current_rate;
 	u64 vco_ref_clk_rate;
 
@@ -591,7 +591,7 @@ static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
 	    parent_rate);
 
 	pll_14nm->vco_current_rate = rate;
-	pll_14nm->vco_ref_clk_rate = VCO_REF_CLK_RATE;
+	pll_14nm->vco_ref_clk_rate = parent_rate;
 
 	dsi_pll_14nm_input_init(pll_14nm);
 
@@ -950,8 +950,9 @@ static struct clk_hw *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm,
 static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm)
 {
 	char clk_name[32], parent[32], vco_name[32];
+	const char *ref_clk_name = __clk_get_name(pll_14nm->vco_ref_clk);
 	struct clk_init_data vco_init = {
-		.parent_names = (const char *[]){ "xo" },
+		.parent_names = &ref_clk_name,
 		.num_parents = 1,
 		.name = vco_name,
 		.flags = CLK_IGNORE_UNUSED,
@@ -1065,6 +1066,15 @@ struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct platform_device *pdev, int id)
 	pll_14nm->id = id;
 	pll_14nm_list[id] = pll_14nm;
 
+	pll_14nm->vco_ref_clk = devm_clk_get(&pdev->dev, "ref");
+	if (IS_ERR(pll_14nm->vco_ref_clk)) {
+		ret = PTR_ERR(pll_14nm->vco_ref_clk);
+		if (ret != -EPROBE_DEFER)
+			dev_err(&pdev->dev, "couldn't get 'ref' clock: %d\n",
+				ret);
+		return ERR_PTR(ret);
+	}
+
 	pll_14nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
 	if (IS_ERR_OR_NULL(pll_14nm->phy_cmn_mmio)) {
 		dev_err(&pdev->dev, "failed to map CMN PHY base\n");
-- 
2.20.0.rc1.387.gf8505762e3-goog

[PATCH v4 5/8] drm/msm/dsi: 10nm PHY: Get ref clock from the DT

[Matthias Kaehlcke]

Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.

Note: This change could break old out-of-tree DTS files that
use the 10nm PHY

Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
---
Changes in v4:
- none

Changes in v3:
- fixed check for EPROBE_DEFER
- added note to commit message about breaking old DTS files
- added 'Reviewed-by: Douglas Anderson <dianders@chromium.org>' tag

Changes in v2:
- remove anonymous array in clk_init_data assignment
- log error code if devm_clk_get() fails
- don't log devm_clk_get() failures for -EPROBE_DEFER
- updated commit message
---
 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
index 4c03f0b7343ed..2d23372acd20d 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
@@ -91,6 +91,7 @@ struct dsi_pll_10nm {
 	void __iomem *phy_cmn_mmio;
 	void __iomem *mmio;
 
+	struct clk *vco_ref_clk;
 	u64 vco_ref_clk_rate;
 	u64 vco_current_rate;
 
@@ -629,8 +630,9 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm)
 {
 	char clk_name[32], parent[32], vco_name[32];
 	char parent2[32], parent3[32], parent4[32];
+	const char *ref_clk_name = __clk_get_name(pll_10nm->vco_ref_clk);
 	struct clk_init_data vco_init = {
-		.parent_names = (const char *[]){ "xo" },
+		.parent_names = &ref_clk_name,
 		.num_parents = 1,
 		.name = vco_name,
 		.flags = CLK_IGNORE_UNUSED,
@@ -786,6 +788,15 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct platform_device *pdev, int id)
 	pll_10nm->id = id;
 	pll_10nm_list[id] = pll_10nm;
 
+	pll_10nm->vco_ref_clk = devm_clk_get(&pdev->dev, "ref");
+	if (IS_ERR(pll_10nm->vco_ref_clk)) {
+		ret = PTR_ERR(pll_10nm->vco_ref_clk);
+		if (ret != -EPROBE_DEFER)
+			dev_err(&pdev->dev, "couldn't get 'ref' clock: %d\n",
+				ret);
+		return ERR_PTR(ret);
+	}
+
 	pll_10nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
 	if (IS_ERR_OR_NULL(pll_10nm->phy_cmn_mmio)) {
 		dev_err(&pdev->dev, "failed to map CMN PHY base\n");
-- 
2.20.0.rc1.387.gf8505762e3-goog

[PATCH v4 6/8] arm64: dts: qcom: msm8916: Set 'xo_board' as ref clock of the DSI PHY

[Matthias Kaehlcke]

Add 'xo_board' as ref clock for the DSI PHYs, it was previously
hardcoded in the PLL 'driver' for the 28nm PHY.

Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
Changes in v4:
- added 'Reviewed-by: Stephen Boyd <swboyd@chromium.org>' tag

Changes in v3:
- added 'Reviewed-by: Douglas Anderson <dianders@chromium.org>' tag

Changes in v2:
- patch added to the series
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index d302d8d639a12..89f30f34ff896 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -959,8 +959,9 @@
 				#clock-cells = <1>;
 				#phy-cells = <0>;
 
-				clocks = <&gcc GCC_MDSS_AHB_CLK>;
-				clock-names = "iface";
+				clocks = <&gcc GCC_MDSS_AHB_CLK>,
+					 <&xo_board>;
+				clock-names = "iface", "ref";
 			};
 		};
 
-- 
2.20.0.rc1.387.gf8505762e3-goog

[PATCH v4 7/8] arm64: dts: sdm845: Set 'bi_tcxo' as ref clock of the DSI PHYs

[Matthias Kaehlcke]

Add 'bi_tcxo' as ref clock for the DSI PHYs, it was previously
hardcoded in the PLL 'driver' for the 10nm PHY.

Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
based on "[v4,1/3] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file"
  (https://patchwork.kernel.org/patch/10666253/)

Changes in v4:
- added 'Reviewed-by: Stephen Boyd <swboyd@chromium.org>' tag

Changes in v3:
- added 'Reviewed-by: Douglas Anderson <dianders@chromium.org>' tag

Changes in v2:
- patch added to the series
---
 arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 5728b4cfae269..cdb5a9bb23e69 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -1372,8 +1372,9 @@
 				#clock-cells = <1>;
 				#phy-cells = <0>;
 
-				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
-				clock-names = "iface";
+				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+					 <&rpmhcc RPMH_CXO_CLK>;
+				clock-names = "iface", "ref";
 			};
 
 			dsi1: dsi@ae96000 {
@@ -1434,8 +1435,9 @@
 				#clock-cells = <1>;
 				#phy-cells = <0>;
 
-				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
-				clock-names = "iface";
+				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+					 <&rpmhcc RPMH_CXO_CLK>;
+				clock-names = "iface", "ref";
 			};
 		};
 
-- 
2.20.0.rc1.387.gf8505762e3-goog

[PATCH v4 8/8] ARM: dts: qcom-apq8064: Set 'xo_board' as ref clock of the DSI PHY

[Matthias Kaehlcke]

Add 'xo_board' as ref clock for the DSI PHY, it was previously
hardcoded in the PLL 'driver' for the 28nm 8960 PHY.

Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
Changes in v4:
- added 'Reviewed-by: Stephen Boyd <swboyd@chromium.org>' tag

Changes in v3:
- patch added to the series
---
 arch/arm/boot/dts/qcom-apq8064.dtsi | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 48c3cf4276101..d337ae9326cd8 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -1338,8 +1338,9 @@
 				<0x04700300 0x200>,
 				<0x04700500 0x5c>;
 			reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
-			clock-names = "iface_clk";
-			clocks = <&mmcc DSI_M_AHB_CLK>;
+			clock-names = "iface_clk", "ref";
+			clocks = <&mmcc DSI_M_AHB_CLK>,
+				 <&xo_board>;
 		};
 
 
-- 
2.20.0.rc1.387.gf8505762e3-goog

Re: [PATCH v4 1/8] dt-bindings: msm/dsi: Add ref clock for PHYs

[Rob Herring]

On Tue,  4 Dec 2018 14:42:27 -0800, Matthias Kaehlcke wrote:
> Allow the PHY drivers to get the ref clock from the DT.
> 
> Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
> Reviewed-by: Stephen Boyd <swboyd@chromium.org>
> Reviewed-by: Douglas Anderson <dianders@chromium.org>
> ---
> Chnages in v4:
> - added "Reviewed-by" tags from Stephen and Doug
> 
> Changes in v3:
> - added note that the ref clock is only required for new DTS
>   files/entries
> 
> Changes in v2:
> - add the ref clock for all PHYs, not only the 10nm one
> - updated commit message
> ---
>  Documentation/devicetree/bindings/display/msm/dsi.txt | 1 +
>  1 file changed, 1 insertion(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH v4 2/8] drm/msm/dsi: 28nm 8960 PHY: Get ref clock from the DT

[Stephen Boyd]

Quoting Matthias Kaehlcke (2018-12-04 14:42:28)
> Get the ref clock of the PHY from the device tree instead of
> hardcoding its name and rate.
> 
> Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>

Re: [PATCH v4 3/8] drm/msm/dsi: 28nm PHY: Get ref clock from the DT

[Stephen Boyd]

Quoting Matthias Kaehlcke (2018-12-04 14:42:29)
> Get the ref clock of the PHY from the device tree instead of
> hardcoding its name and rate.
> 
> Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>

Re: [PATCH v4 4/8] drm/msm/dsi: 14nm PHY: Get ref clock from the DT

[Stephen Boyd]

Quoting Matthias Kaehlcke (2018-12-04 14:42:30)
> diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
> index 71fe60e5f01f1..032bf3e8614bd 100644
> --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
> +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
> @@ -40,7 +40,6 @@
>  
>  #define NUM_PROVIDED_CLKS              2
>  
> -#define VCO_REF_CLK_RATE               19200000
>  #define VCO_MIN_RATE                   1300000000UL
>  #define VCO_MAX_RATE                   2600000000UL
>  
> @@ -139,6 +138,7 @@ struct dsi_pll_14nm {
>         /* protects REG_DSI_14nm_PHY_CMN_CLK_CFG0 register */
>         spinlock_t postdiv_lock;
>  
> +       struct clk *vco_ref_clk;

Is there any need to keep it in the struct? Or just get the clk, find
the rate, and then put the clk and call pll_14nm_postdiv_register()?

>         u64 vco_current_rate;
>         u64 vco_ref_clk_rate;
>  

Re: [PATCH v4 5/8] drm/msm/dsi: 10nm PHY: Get ref clock from the DT

[Stephen Boyd]

Quoting Matthias Kaehlcke (2018-12-04 14:42:31)
> Get the ref clock of the PHY from the device tree instead of
> hardcoding its name and rate.
> 
> Note: This change could break old out-of-tree DTS files that
> use the 10nm PHY
> 
> Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
> Reviewed-by: Douglas Anderson <dianders@chromium.org>
> ---
> Changes in v4:
> - none
> 
> Changes in v3:
> - fixed check for EPROBE_DEFER
> - added note to commit message about breaking old DTS files
> - added 'Reviewed-by: Douglas Anderson <dianders@chromium.org>' tag
> 
> Changes in v2:
> - remove anonymous array in clk_init_data assignment
> - log error code if devm_clk_get() fails
> - don't log devm_clk_get() failures for -EPROBE_DEFER
> - updated commit message
> ---
>  drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
> index 4c03f0b7343ed..2d23372acd20d 100644
> --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
> +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
> @@ -91,6 +91,7 @@ struct dsi_pll_10nm {
>         void __iomem *phy_cmn_mmio;
>         void __iomem *mmio;
>  
> +       struct clk *vco_ref_clk;

Same comment, and also get the name in probe or pass the clk pointer
around instead of storing it forever.

>         u64 vco_ref_clk_rate;
>         u64 vco_current_rate;
>  

Re: [PATCH v4 3/8] drm/msm/dsi: 28nm PHY: Get ref clock from the DT

[Niklas Cassel]

On Tue, Dec 04, 2018 at 02:42:29PM -0800, Matthias Kaehlcke wrote:
> Get the ref clock of the PHY from the device tree instead of
> hardcoding its name and rate.
> 
> Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
> ---
> Changes in v4:
> - always use parent rate in dsi_pll_28nm_clk_set_rate() and
>    dsi_pll_28nm_clk_recalc_rate()
> - pass name of VCO ref clock to pll_28nm_register() instead of
>   storing it in a struct field
> - updated commit message
> 
> Changes in v3:
> - use default name and rate if the ref clock is not specified
>   in the DT
> - store vco_ref_clk_name instead of vco_ref_clk
> - dsi_pll_28nm_clk_set_rate: changed data type of ref_clk_rate to
>   unsigned long
> - fixed check for EPROBE_DEFER
> - renamed VCO_REF_CLK_RATE to VCO_REF_CLK_DEFAULT_RATE
> 
> Changes in v2:
> - patch added to the series
> ---
>  drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c | 36 +++++++++++++++-------
>  1 file changed, 25 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
> index 26e3a01a99c2b..7777340b03e8d 100644
> --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
> +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
> @@ -40,7 +40,6 @@
>  
>  #define NUM_PROVIDED_CLKS		2
>  
> -#define VCO_REF_CLK_RATE		19200000
>  #define VCO_MIN_RATE			350000000
>  #define VCO_MAX_RATE			750000000
>  
> @@ -166,17 +165,17 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
>  	pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70);
>  	pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15);
>  
> -	rem = rate % VCO_REF_CLK_RATE;
> +	rem = rate % parent_rate;
>  	if (rem) {
>  		refclk_cfg = DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR;
>  		frac_n_mode = 1;
> -		div_fbx1000 = rate / (VCO_REF_CLK_RATE / 500);
> -		gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 500);
> +		div_fbx1000 = rate / (parent_rate / 500);
> +		gen_vco_clk = div_fbx1000 * (parent_rate / 500);
>  	} else {
>  		refclk_cfg = 0x0;
>  		frac_n_mode = 0;
> -		div_fbx1000 = rate / (VCO_REF_CLK_RATE / 1000);
> -		gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 1000);
> +		div_fbx1000 = rate / (parent_rate / 1000);
> +		gen_vco_clk = div_fbx1000 * (parent_rate / 1000);
>  	}
>  
>  	DBG("refclk_cfg = %d", refclk_cfg);
> @@ -265,7 +264,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
>  	void __iomem *base = pll_28nm->mmio;
>  	u32 sdm0, doubler, sdm_byp_div;
>  	u32 sdm_dc_off, sdm_freq_seed, sdm2, sdm3;
> -	u32 ref_clk = VCO_REF_CLK_RATE;
> +	u32 ref_clk = parent_rate;
>  	unsigned long vco_rate;
>  
>  	VERB("parent_rate=%lu", parent_rate);
> @@ -273,7 +272,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
>  	/* Check to see if the ref clk doubler is enabled */
>  	doubler = pll_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) &
>  			DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR;
> -	ref_clk += (doubler * VCO_REF_CLK_RATE);
> +	ref_clk += (doubler * ref_clk);
>  
>  	/* see if it is integer mode or sdm mode */
>  	sdm0 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0);
> @@ -514,11 +513,12 @@ static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll)
>  	pll_28nm->clk_data.clk_num = 0;
>  }
>  
> -static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
> +static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm,
> +			     const char *ref_clk_name)
>  {
>  	char clk_name[32], parent1[32], parent2[32], vco_name[32];
>  	struct clk_init_data vco_init = {
> -		.parent_names = (const char *[]){ "xo" },
> +		.parent_names = &ref_clk_name,
>  		.num_parents = 1,
>  		.name = vco_name,
>  		.flags = CLK_IGNORE_UNUSED,
> @@ -593,6 +593,8 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev,
>  {
>  	struct dsi_pll_28nm *pll_28nm;
>  	struct msm_dsi_pll *pll;
> +	struct clk *vco_ref_clk;
> +	const char *vco_ref_clk_name;
>  	int ret;
>  
>  	if (!pdev)
> @@ -605,6 +607,18 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev,
>  	pll_28nm->pdev = pdev;
>  	pll_28nm->id = id;
>  
> +	vco_ref_clk = devm_clk_get(&pdev->dev, "ref");
> +	if (!IS_ERR(vco_ref_clk)) {
> +		vco_ref_clk_name = __clk_get_name(vco_ref_clk);
> +	} else {
> +		ret = PTR_ERR(vco_ref_clk);
> +		if (ret == -EPROBE_DEFER)
> +			ERR_PTR(ret);

It looks like you are missing the return keyword here.

> +
> +		dev_warn(&pdev->dev, "'ref' clock is not specified, using default name\n");
> +		vco_ref_clk_name = "xo";
> +	}
> +
>  	pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
>  	if (IS_ERR_OR_NULL(pll_28nm->mmio)) {
>  		dev_err(&pdev->dev, "%s: failed to map pll base\n", __func__);
> @@ -637,7 +651,7 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev,
>  		return ERR_PTR(-EINVAL);
>  	}
>  
> -	ret = pll_28nm_register(pll_28nm);
> +	ret = pll_28nm_register(pll_28nm, vco_ref_clk_name);
>  	if (ret) {
>  		dev_err(&pdev->dev, "failed to register PLL: %d\n", ret);
>  		return ERR_PTR(ret);
> -- 
> 2.20.0.rc1.387.gf8505762e3-goog
> 

Re: [PATCH v4 3/8] drm/msm/dsi: 28nm PHY: Get ref clock from the DT

[Matthias Kaehlcke]

Hi Niklas,

On Wed, Dec 12, 2018 at 11:07:17PM +0100, Niklas Cassel wrote:
> On Tue, Dec 04, 2018 at 02:42:29PM -0800, Matthias Kaehlcke wrote:
> > Get the ref clock of the PHY from the device tree instead of
> > hardcoding its name and rate.
> > 
> > Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
> > ---
> > Changes in v4:
> > - always use parent rate in dsi_pll_28nm_clk_set_rate() and
> >    dsi_pll_28nm_clk_recalc_rate()
> > - pass name of VCO ref clock to pll_28nm_register() instead of
> >   storing it in a struct field
> > - updated commit message
> > 
> > Changes in v3:
> > - use default name and rate if the ref clock is not specified
> >   in the DT
> > - store vco_ref_clk_name instead of vco_ref_clk
> > - dsi_pll_28nm_clk_set_rate: changed data type of ref_clk_rate to
> >   unsigned long
> > - fixed check for EPROBE_DEFER
> > - renamed VCO_REF_CLK_RATE to VCO_REF_CLK_DEFAULT_RATE
> > 
> > Changes in v2:
> > - patch added to the series
> > ---
> >  drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c | 36 +++++++++++++++-------
> >  1 file changed, 25 insertions(+), 11 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
> > index 26e3a01a99c2b..7777340b03e8d 100644
> > --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
> > +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
> > @@ -40,7 +40,6 @@
> >  
> >  #define NUM_PROVIDED_CLKS		2
> >  
> > -#define VCO_REF_CLK_RATE		19200000
> >  #define VCO_MIN_RATE			350000000
> >  #define VCO_MAX_RATE			750000000
> >  
> > @@ -166,17 +165,17 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
> >  	pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70);
> >  	pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15);
> >  
> > -	rem = rate % VCO_REF_CLK_RATE;
> > +	rem = rate % parent_rate;
> >  	if (rem) {
> >  		refclk_cfg = DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR;
> >  		frac_n_mode = 1;
> > -		div_fbx1000 = rate / (VCO_REF_CLK_RATE / 500);
> > -		gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 500);
> > +		div_fbx1000 = rate / (parent_rate / 500);
> > +		gen_vco_clk = div_fbx1000 * (parent_rate / 500);
> >  	} else {
> >  		refclk_cfg = 0x0;
> >  		frac_n_mode = 0;
> > -		div_fbx1000 = rate / (VCO_REF_CLK_RATE / 1000);
> > -		gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 1000);
> > +		div_fbx1000 = rate / (parent_rate / 1000);
> > +		gen_vco_clk = div_fbx1000 * (parent_rate / 1000);
> >  	}
> >  
> >  	DBG("refclk_cfg = %d", refclk_cfg);
> > @@ -265,7 +264,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
> >  	void __iomem *base = pll_28nm->mmio;
> >  	u32 sdm0, doubler, sdm_byp_div;
> >  	u32 sdm_dc_off, sdm_freq_seed, sdm2, sdm3;
> > -	u32 ref_clk = VCO_REF_CLK_RATE;
> > +	u32 ref_clk = parent_rate;
> >  	unsigned long vco_rate;
> >  
> >  	VERB("parent_rate=%lu", parent_rate);
> > @@ -273,7 +272,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
> >  	/* Check to see if the ref clk doubler is enabled */
> >  	doubler = pll_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) &
> >  			DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR;
> > -	ref_clk += (doubler * VCO_REF_CLK_RATE);
> > +	ref_clk += (doubler * ref_clk);
> >  
> >  	/* see if it is integer mode or sdm mode */
> >  	sdm0 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0);
> > @@ -514,11 +513,12 @@ static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll)
> >  	pll_28nm->clk_data.clk_num = 0;
> >  }
> >  
> > -static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
> > +static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm,
> > +			     const char *ref_clk_name)
> >  {
> >  	char clk_name[32], parent1[32], parent2[32], vco_name[32];
> >  	struct clk_init_data vco_init = {
> > -		.parent_names = (const char *[]){ "xo" },
> > +		.parent_names = &ref_clk_name,
> >  		.num_parents = 1,
> >  		.name = vco_name,
> >  		.flags = CLK_IGNORE_UNUSED,
> > @@ -593,6 +593,8 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev,
> >  {
> >  	struct dsi_pll_28nm *pll_28nm;
> >  	struct msm_dsi_pll *pll;
> > +	struct clk *vco_ref_clk;
> > +	const char *vco_ref_clk_name;
> >  	int ret;
> >  
> >  	if (!pdev)
> > @@ -605,6 +607,18 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev,
> >  	pll_28nm->pdev = pdev;
> >  	pll_28nm->id = id;
> >  
> > +	vco_ref_clk = devm_clk_get(&pdev->dev, "ref");
> > +	if (!IS_ERR(vco_ref_clk)) {
> > +		vco_ref_clk_name = __clk_get_name(vco_ref_clk);
> > +	} else {
> > +		ret = PTR_ERR(vco_ref_clk);
> > +		if (ret == -EPROBE_DEFER)
> > +			ERR_PTR(ret);
> 
> It looks like you are missing the return keyword here.

Indeed, thanks for pointing that out!

Cheers

Matthias

Re: [PATCH v4 4/8] drm/msm/dsi: 14nm PHY: Get ref clock from the DT

[Matthias Kaehlcke]

On Mon, Dec 10, 2018 at 07:51:19AM -0800, Stephen Boyd wrote:
> Quoting Matthias Kaehlcke (2018-12-04 14:42:30)
> > diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
> > index 71fe60e5f01f1..032bf3e8614bd 100644
> > --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
> > +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
> > @@ -40,7 +40,6 @@
> >  
> >  #define NUM_PROVIDED_CLKS              2
> >  
> > -#define VCO_REF_CLK_RATE               19200000
> >  #define VCO_MIN_RATE                   1300000000UL
> >  #define VCO_MAX_RATE                   2600000000UL
> >  
> > @@ -139,6 +138,7 @@ struct dsi_pll_14nm {
> >         /* protects REG_DSI_14nm_PHY_CMN_CLK_CFG0 register */
> >         spinlock_t postdiv_lock;
> >  
> > +       struct clk *vco_ref_clk;
> 
> Is there any need to keep it in the struct? Or just get the clk, find
> the rate, and then put the clk and call pll_14nm_postdiv_register()?

I suppose you mean passing the clock name to pll_14nm_register()?

Is putting the clock really needed or preferable, or is it just fine
to auto-put it when the device is deleted?

Re: [PATCH v4 4/8] drm/msm/dsi: 14nm PHY: Get ref clock from the DT

[Stephen Boyd]

Quoting Matthias Kaehlcke (2018-12-19 14:22:22)
> On Mon, Dec 10, 2018 at 07:51:19AM -0800, Stephen Boyd wrote:
> > Quoting Matthias Kaehlcke (2018-12-04 14:42:30)
> > > diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
> > > index 71fe60e5f01f1..032bf3e8614bd 100644
> > > --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
> > > +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
> > > @@ -40,7 +40,6 @@
> > >  
> > >  #define NUM_PROVIDED_CLKS              2
> > >  
> > > -#define VCO_REF_CLK_RATE               19200000
> > >  #define VCO_MIN_RATE                   1300000000UL
> > >  #define VCO_MAX_RATE                   2600000000UL
> > >  
> > > @@ -139,6 +138,7 @@ struct dsi_pll_14nm {
> > >         /* protects REG_DSI_14nm_PHY_CMN_CLK_CFG0 register */
> > >         spinlock_t postdiv_lock;
> > >  
> > > +       struct clk *vco_ref_clk;
> > 
> > Is there any need to keep it in the struct? Or just get the clk, find
> > the rate, and then put the clk and call pll_14nm_postdiv_register()?
> 
> I suppose you mean passing the clock name to pll_14nm_register()?

Yes, whatever makes it possible to avoid storing the pointer in the
struct.

> 
> Is putting the clock really needed or preferable, or is it just fine
> to auto-put it when the device is deleted?

Up to you. If you don't have a need for the clk anymore it seems fine to
just put the clk and be done.