linux-kernel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
* [v3] drm/msm/dpu: Clean up dpu hw interrupts
@ 2018-12-18 11:35 Jayant Shekhar
  2019-01-22 20:11 ` [Freedreno] " Sean Paul
  0 siblings, 1 reply; 2+ messages in thread
From: Jayant Shekhar @ 2018-12-18 11:35 UTC (permalink / raw)
  To: dri-devel, linux-arm-msm, freedreno, devicetree
  Cc: Jayant Shekhar, linux-kernel, robdclark, seanpaul, hoegsberg,
	abhinavk, jsanka, chandanu, nganji

Remove unused functions and macros from files handling
dpu hardware interrupts.

changes in v2:
  Removed clear_interrupt_status (Jordan Crouse)
changes in v3:
  Changed commit text

Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 44 -----------------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 44 -----------------------
 2 files changed, 88 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
index c0b7f00..8a28a03 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
@@ -170,10 +170,6 @@
 /**
  * AD4 interrupt status bit definitions
  */
-#define DPU_INTR_BRIGHTPR_UPDATED BIT(4)
-#define DPU_INTR_DARKENH_UPDATED BIT(3)
-#define DPU_INTR_STREN_OUTROI_UPDATED BIT(2)
-#define DPU_INTR_STREN_INROI_UPDATED BIT(1)
 #define DPU_INTR_BACKLIGHT_UPDATED BIT(0)
 /**
  * struct dpu_intr_reg - array of DPU register sets
@@ -782,18 +778,6 @@ static int dpu_hw_intr_irqidx_lookup(enum dpu_intr_type intr_type,
 	return -EINVAL;
 }
 
-static void dpu_hw_intr_set_mask(struct dpu_hw_intr *intr, uint32_t reg_off,
-		uint32_t mask)
-{
-	if (!intr)
-		return;
-
-	DPU_REG_WRITE(&intr->hw, reg_off, mask);
-
-	/* ensure register writes go through */
-	wmb();
-}
-
 static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr,
 		void (*cbfunc)(void *, int),
 		void *arg)
@@ -1004,18 +988,6 @@ static int dpu_hw_intr_disable_irqs(struct dpu_hw_intr *intr)
 	return 0;
 }
 
-static int dpu_hw_intr_get_valid_interrupts(struct dpu_hw_intr *intr,
-		uint32_t *mask)
-{
-	if (!intr || !mask)
-		return -EINVAL;
-
-	*mask = IRQ_SOURCE_MDP | IRQ_SOURCE_DSI0 | IRQ_SOURCE_DSI1
-		| IRQ_SOURCE_HDMI | IRQ_SOURCE_EDP;
-
-	return 0;
-}
-
 static void dpu_hw_intr_get_interrupt_statuses(struct dpu_hw_intr *intr)
 {
 	int i;
@@ -1065,19 +1037,6 @@ static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr,
 	wmb();
 }
 
-static void dpu_hw_intr_clear_interrupt_status(struct dpu_hw_intr *intr,
-		int irq_idx)
-{
-	unsigned long irq_flags;
-
-	if (!intr)
-		return;
-
-	spin_lock_irqsave(&intr->irq_lock, irq_flags);
-	dpu_hw_intr_clear_intr_status_nolock(intr, irq_idx);
-	spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
-}
-
 static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr,
 		int irq_idx, bool clear)
 {
@@ -1113,16 +1072,13 @@ static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr,
 
 static void __setup_intr_ops(struct dpu_hw_intr_ops *ops)
 {
-	ops->set_mask = dpu_hw_intr_set_mask;
 	ops->irq_idx_lookup = dpu_hw_intr_irqidx_lookup;
 	ops->enable_irq = dpu_hw_intr_enable_irq;
 	ops->disable_irq = dpu_hw_intr_disable_irq;
 	ops->dispatch_irqs = dpu_hw_intr_dispatch_irq;
 	ops->clear_all_irqs = dpu_hw_intr_clear_irqs;
 	ops->disable_all_irqs = dpu_hw_intr_disable_irqs;
-	ops->get_valid_interrupts = dpu_hw_intr_get_valid_interrupts;
 	ops->get_interrupt_statuses = dpu_hw_intr_get_interrupt_statuses;
-	ops->clear_interrupt_status = dpu_hw_intr_clear_interrupt_status;
 	ops->clear_intr_status_nolock = dpu_hw_intr_clear_intr_status_nolock;
 	ops->get_interrupt_status = dpu_hw_intr_get_interrupt_status;
 }
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
index 61e4cba..4d7a1c7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
@@ -20,13 +20,6 @@
 #include "dpu_hw_util.h"
 #include "dpu_hw_mdss.h"
 
-#define IRQ_SOURCE_MDP		BIT(0)
-#define IRQ_SOURCE_DSI0		BIT(4)
-#define IRQ_SOURCE_DSI1		BIT(5)
-#define IRQ_SOURCE_HDMI		BIT(8)
-#define IRQ_SOURCE_EDP		BIT(12)
-#define IRQ_SOURCE_MHL		BIT(16)
-
 /**
  * dpu_intr_type - HW Interrupt Type
  * @DPU_IRQ_TYPE_WB_ROT_COMP:		WB rotator done
@@ -96,18 +89,6 @@ enum dpu_intr_type {
  */
 struct dpu_hw_intr_ops {
 	/**
-	 * set_mask - Programs the given interrupt register with the
-	 *            given interrupt mask. Register value will get overwritten.
-	 * @intr:	HW interrupt handle
-	 * @reg_off:	MDSS HW register offset
-	 * @irqmask:	IRQ mask value
-	 */
-	void (*set_mask)(
-			struct dpu_hw_intr *intr,
-			uint32_t reg,
-			uint32_t irqmask);
-
-	/**
 	 * irq_idx_lookup - Lookup IRQ index on the HW interrupt type
 	 *                 Used for all irq related ops
 	 * @intr_type:		Interrupt type defined in dpu_intr_type
@@ -177,16 +158,6 @@ struct dpu_hw_intr_ops {
 			struct dpu_hw_intr *intr);
 
 	/**
-	 * clear_interrupt_status - Clears HW interrupt status based on given
-	 *                          lookup IRQ index.
-	 * @intr:	HW interrupt handle
-	 * @irq_idx:	Lookup irq index return from irq_idx_lookup
-	 */
-	void (*clear_interrupt_status)(
-			struct dpu_hw_intr *intr,
-			int irq_idx);
-
-	/**
 	 * clear_intr_status_nolock() - clears the HW interrupts without lock
 	 * @intr:	HW interrupt handle
 	 * @irq_idx:	Lookup irq index return from irq_idx_lookup
@@ -206,21 +177,6 @@ struct dpu_hw_intr_ops {
 			struct dpu_hw_intr *intr,
 			int irq_idx,
 			bool clear);
-
-	/**
-	 * get_valid_interrupts - Gets a mask of all valid interrupt sources
-	 *                        within DPU. These are actually status bits
-	 *                        within interrupt registers that specify the
-	 *                        source of the interrupt in IRQs. For example,
-	 *                        valid interrupt sources can be MDP, DSI,
-	 *                        HDMI etc.
-	 * @intr:	HW interrupt handle
-	 * @mask:	Returning the interrupt source MASK
-	 * @return:	0 for success, otherwise failure
-	 */
-	int (*get_valid_interrupts)(
-			struct dpu_hw_intr *intr,
-			uint32_t *mask);
 };
 
 /**
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


^ permalink raw reply related	[flat|nested] 2+ messages in thread
* Re: [Freedreno] [v3] drm/msm/dpu: Clean up dpu hw interrupts
  2018-12-18 11:35 [v3] drm/msm/dpu: Clean up dpu hw interrupts Jayant Shekhar
@ 2019-01-22 20:11 ` Sean Paul
  0 siblings, 0 replies; 2+ messages in thread
From: Sean Paul @ 2019-01-22 20:11 UTC (permalink / raw)
  To: Jayant Shekhar
  Cc: dri-devel, linux-arm-msm, freedreno, devicetree, linux-kernel,
	abhinavk, robdclark, nganji, seanpaul, hoegsberg, jsanka,
	chandanu

On Tue, Dec 18, 2018 at 05:05:48PM +0530, Jayant Shekhar wrote:
> Remove unused functions and macros from files handling
> dpu hardware interrupts.
> 
> changes in v2:
>   Removed clear_interrupt_status (Jordan Crouse)
> changes in v3:
>   Changed commit text
> 
> Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>

Applied to dpu-staging, thanks!

Sean
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 44 -----------------------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 44 -----------------------
>  2 files changed, 88 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> index c0b7f00..8a28a03 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> @@ -170,10 +170,6 @@
>  /**
>   * AD4 interrupt status bit definitions
>   */
> -#define DPU_INTR_BRIGHTPR_UPDATED BIT(4)
> -#define DPU_INTR_DARKENH_UPDATED BIT(3)
> -#define DPU_INTR_STREN_OUTROI_UPDATED BIT(2)
> -#define DPU_INTR_STREN_INROI_UPDATED BIT(1)
>  #define DPU_INTR_BACKLIGHT_UPDATED BIT(0)
>  /**
>   * struct dpu_intr_reg - array of DPU register sets
> @@ -782,18 +778,6 @@ static int dpu_hw_intr_irqidx_lookup(enum dpu_intr_type intr_type,
>  	return -EINVAL;
>  }
>  
> -static void dpu_hw_intr_set_mask(struct dpu_hw_intr *intr, uint32_t reg_off,
> -		uint32_t mask)
> -{
> -	if (!intr)
> -		return;
> -
> -	DPU_REG_WRITE(&intr->hw, reg_off, mask);
> -
> -	/* ensure register writes go through */
> -	wmb();
> -}
> -
>  static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr,
>  		void (*cbfunc)(void *, int),
>  		void *arg)
> @@ -1004,18 +988,6 @@ static int dpu_hw_intr_disable_irqs(struct dpu_hw_intr *intr)
>  	return 0;
>  }
>  
> -static int dpu_hw_intr_get_valid_interrupts(struct dpu_hw_intr *intr,
> -		uint32_t *mask)
> -{
> -	if (!intr || !mask)
> -		return -EINVAL;
> -
> -	*mask = IRQ_SOURCE_MDP | IRQ_SOURCE_DSI0 | IRQ_SOURCE_DSI1
> -		| IRQ_SOURCE_HDMI | IRQ_SOURCE_EDP;
> -
> -	return 0;
> -}
> -
>  static void dpu_hw_intr_get_interrupt_statuses(struct dpu_hw_intr *intr)
>  {
>  	int i;
> @@ -1065,19 +1037,6 @@ static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr,
>  	wmb();
>  }
>  
> -static void dpu_hw_intr_clear_interrupt_status(struct dpu_hw_intr *intr,
> -		int irq_idx)
> -{
> -	unsigned long irq_flags;
> -
> -	if (!intr)
> -		return;
> -
> -	spin_lock_irqsave(&intr->irq_lock, irq_flags);
> -	dpu_hw_intr_clear_intr_status_nolock(intr, irq_idx);
> -	spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
> -}
> -
>  static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr,
>  		int irq_idx, bool clear)
>  {
> @@ -1113,16 +1072,13 @@ static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr,
>  
>  static void __setup_intr_ops(struct dpu_hw_intr_ops *ops)
>  {
> -	ops->set_mask = dpu_hw_intr_set_mask;
>  	ops->irq_idx_lookup = dpu_hw_intr_irqidx_lookup;
>  	ops->enable_irq = dpu_hw_intr_enable_irq;
>  	ops->disable_irq = dpu_hw_intr_disable_irq;
>  	ops->dispatch_irqs = dpu_hw_intr_dispatch_irq;
>  	ops->clear_all_irqs = dpu_hw_intr_clear_irqs;
>  	ops->disable_all_irqs = dpu_hw_intr_disable_irqs;
> -	ops->get_valid_interrupts = dpu_hw_intr_get_valid_interrupts;
>  	ops->get_interrupt_statuses = dpu_hw_intr_get_interrupt_statuses;
> -	ops->clear_interrupt_status = dpu_hw_intr_clear_interrupt_status;
>  	ops->clear_intr_status_nolock = dpu_hw_intr_clear_intr_status_nolock;
>  	ops->get_interrupt_status = dpu_hw_intr_get_interrupt_status;
>  }
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> index 61e4cba..4d7a1c7 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> @@ -20,13 +20,6 @@
>  #include "dpu_hw_util.h"
>  #include "dpu_hw_mdss.h"
>  
> -#define IRQ_SOURCE_MDP		BIT(0)
> -#define IRQ_SOURCE_DSI0		BIT(4)
> -#define IRQ_SOURCE_DSI1		BIT(5)
> -#define IRQ_SOURCE_HDMI		BIT(8)
> -#define IRQ_SOURCE_EDP		BIT(12)
> -#define IRQ_SOURCE_MHL		BIT(16)
> -
>  /**
>   * dpu_intr_type - HW Interrupt Type
>   * @DPU_IRQ_TYPE_WB_ROT_COMP:		WB rotator done
> @@ -96,18 +89,6 @@ enum dpu_intr_type {
>   */
>  struct dpu_hw_intr_ops {
>  	/**
> -	 * set_mask - Programs the given interrupt register with the
> -	 *            given interrupt mask. Register value will get overwritten.
> -	 * @intr:	HW interrupt handle
> -	 * @reg_off:	MDSS HW register offset
> -	 * @irqmask:	IRQ mask value
> -	 */
> -	void (*set_mask)(
> -			struct dpu_hw_intr *intr,
> -			uint32_t reg,
> -			uint32_t irqmask);
> -
> -	/**
>  	 * irq_idx_lookup - Lookup IRQ index on the HW interrupt type
>  	 *                 Used for all irq related ops
>  	 * @intr_type:		Interrupt type defined in dpu_intr_type
> @@ -177,16 +158,6 @@ struct dpu_hw_intr_ops {
>  			struct dpu_hw_intr *intr);
>  
>  	/**
> -	 * clear_interrupt_status - Clears HW interrupt status based on given
> -	 *                          lookup IRQ index.
> -	 * @intr:	HW interrupt handle
> -	 * @irq_idx:	Lookup irq index return from irq_idx_lookup
> -	 */
> -	void (*clear_interrupt_status)(
> -			struct dpu_hw_intr *intr,
> -			int irq_idx);
> -
> -	/**
>  	 * clear_intr_status_nolock() - clears the HW interrupts without lock
>  	 * @intr:	HW interrupt handle
>  	 * @irq_idx:	Lookup irq index return from irq_idx_lookup
> @@ -206,21 +177,6 @@ struct dpu_hw_intr_ops {
>  			struct dpu_hw_intr *intr,
>  			int irq_idx,
>  			bool clear);
> -
> -	/**
> -	 * get_valid_interrupts - Gets a mask of all valid interrupt sources
> -	 *                        within DPU. These are actually status bits
> -	 *                        within interrupt registers that specify the
> -	 *                        source of the interrupt in IRQs. For example,
> -	 *                        valid interrupt sources can be MDP, DSI,
> -	 *                        HDMI etc.
> -	 * @intr:	HW interrupt handle
> -	 * @mask:	Returning the interrupt source MASK
> -	 * @return:	0 for success, otherwise failure
> -	 */
> -	int (*get_valid_interrupts)(
> -			struct dpu_hw_intr *intr,
> -			uint32_t *mask);
>  };
>  
>  /**
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 
> _______________________________________________
> Freedreno mailing list
> Freedreno@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/freedreno

-- 
Sean Paul, Software Engineer, Google / Chromium OS

^ permalink raw reply	[flat|nested] 2+ messages in thread
end of thread, other threads:[~2019-01-22 20:12 UTC | newest]

Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-12-18 11:35 [v3] drm/msm/dpu: Clean up dpu hw interrupts Jayant Shekhar
2019-01-22 20:11 ` [Freedreno] " Sean Paul

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).