* [PATCH V9 1/3] dt-bindings: mmc: tegra: Add supports-cqe property
@ 2019-01-15 19:03 Sowjanya Komatineni
2019-01-15 19:03 ` [PATCH V9 2/3] arm64: dts: tegra: Add CQE Support for SDMMC4 Sowjanya Komatineni
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: Sowjanya Komatineni @ 2019-01-15 19:03 UTC (permalink / raw)
To: robh+dt, mark.rutland, mperttunen, chunyan.zhang, thierry.reding,
jonathanh, adrian.hunter, ulf.hansson
Cc: anrao, devicetree, linux-tegra, linux-kernel, linux-mmc,
Sowjanya Komatineni
Add supports-cqe optional property for Tegra SDMMC.
Tegra186 and Tegra194 supports HW Command queue only
on SDMMC4 controller. This property is used to identify
command queue support controller in the tegra sdhci driver.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
index 32b4b4e41923..fb14c2c8d7ee 100644
--- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
@@ -72,6 +72,10 @@ Optional properties for Tegra210 and Tegra186:
- nvidia,default-trim : Specify the default outbound clock trimmer
value.
- nvidia,dqs-trim : Specify DQS trim value for HS400 timing
+- supports-cqe : The presence of this property indicates that the
+ corresponding controller supports HW command queue feature.
+ Tegra186 and Tegra194 has 4 SDMMC Controllers and only SDMMC4
+ controller supports HW Command Queue with eMMC device.
Notes on the pad calibration pull up and pulldown offset values:
- The property values are drive codes which are programmed into the
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH V9 2/3] arm64: dts: tegra: Add CQE Support for SDMMC4
2019-01-15 19:03 [PATCH V9 1/3] dt-bindings: mmc: tegra: Add supports-cqe property Sowjanya Komatineni
@ 2019-01-15 19:03 ` Sowjanya Komatineni
2019-01-15 19:03 ` [PATCH V9 3/3] mmc: tegra: HW Command Queue Support for Tegra SDMMC Sowjanya Komatineni
` (2 subsequent siblings)
3 siblings, 0 replies; 8+ messages in thread
From: Sowjanya Komatineni @ 2019-01-15 19:03 UTC (permalink / raw)
To: robh+dt, mark.rutland, mperttunen, chunyan.zhang, thierry.reding,
jonathanh, adrian.hunter, ulf.hansson
Cc: anrao, devicetree, linux-tegra, linux-kernel, linux-mmc,
Sowjanya Komatineni
Add CQE Support for Tegra186 and Tegra194 SDMMC4 controller
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 +
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 22815db4a3ed..3dfdc4701934 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -319,6 +319,7 @@
nvidia,default-trim = <0x9>;
nvidia,dqs-trim = <63>;
mmc-hs400-1_8v;
+ supports-cqe;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 6dfa1ca0b851..9ce1c91d4596 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -325,6 +325,7 @@
clock-names = "sdhci";
resets = <&bpmp TEGRA194_RESET_SDMMC4>;
reset-names = "sdhci";
+ supports-cqe;
status = "disabled";
};
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH V9 3/3] mmc: tegra: HW Command Queue Support for Tegra SDMMC
2019-01-15 19:03 [PATCH V9 1/3] dt-bindings: mmc: tegra: Add supports-cqe property Sowjanya Komatineni
2019-01-15 19:03 ` [PATCH V9 2/3] arm64: dts: tegra: Add CQE Support for SDMMC4 Sowjanya Komatineni
@ 2019-01-15 19:03 ` Sowjanya Komatineni
2019-01-21 10:44 ` Thierry Reding
2019-01-21 10:41 ` [PATCH V9 1/3] dt-bindings: mmc: tegra: Add supports-cqe property Thierry Reding
2019-01-21 10:43 ` Thierry Reding
3 siblings, 1 reply; 8+ messages in thread
From: Sowjanya Komatineni @ 2019-01-15 19:03 UTC (permalink / raw)
To: robh+dt, mark.rutland, mperttunen, chunyan.zhang, thierry.reding,
jonathanh, adrian.hunter, ulf.hansson
Cc: anrao, devicetree, linux-tegra, linux-kernel, linux-mmc,
Sowjanya Komatineni
This patch adds HW Command Queue for supported Tegra SDMMC
controllers.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
drivers/mmc/host/Kconfig | 1 +
drivers/mmc/host/sdhci-tegra.c | 117 +++++++++++++++++++++++++++++++++++++++--
drivers/mmc/host/sdhci.c | 9 +++-
drivers/mmc/host/sdhci.h | 2 +
4 files changed, 124 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index e26b8145efb3..0739d26c001b 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -250,6 +250,7 @@ config MMC_SDHCI_TEGRA
depends on ARCH_TEGRA
depends on MMC_SDHCI_PLTFM
select MMC_SDHCI_IO_ACCESSORS
+ select MMC_CQHCI
help
This selects the Tegra SD/MMC controller. If you have a Tegra
platform with SD or MMC devices, say Y or M here.
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index e6ace31e2a41..d400f158bee4 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -33,6 +33,7 @@
#include <linux/ktime.h>
#include "sdhci-pltfm.h"
+#include "cqhci.h"
/* Tegra SDHOST controller vendor register definitions */
#define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100
@@ -89,6 +90,9 @@
#define NVQUIRK_NEEDS_PAD_CONTROL BIT(7)
#define NVQUIRK_DIS_CARD_CLK_CONFIG_TAP BIT(8)
+/* SDMMC CQE Base Address for Tegra Host Ver 4.1 and Higher */
+#define SDHCI_TEGRA_CQE_BASE_ADDR 0xF000
+
struct sdhci_tegra_soc_data {
const struct sdhci_pltfm_data *pdata;
u32 nvquirks;
@@ -128,6 +132,7 @@ struct sdhci_tegra {
u32 default_tap;
u32 default_trim;
u32 dqs_trim;
+ bool enable_hwcq;
};
static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
@@ -595,6 +600,20 @@ static void tegra_sdhci_parse_tap_and_trim(struct sdhci_host *host)
tegra_host->dqs_trim = 0x11;
}
+static void tegra_sdhci_parse_dt(struct sdhci_host *host)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
+
+ if (device_property_read_bool(host->mmc->parent, "supports-cqe"))
+ tegra_host->enable_hwcq = true;
+ else
+ tegra_host->enable_hwcq = false;
+
+ tegra_sdhci_parse_pad_autocal_dt(host);
+ tegra_sdhci_parse_tap_and_trim(host);
+}
+
static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
{
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
@@ -836,6 +855,49 @@ static void tegra_sdhci_voltage_switch(struct sdhci_host *host)
tegra_host->pad_calib_required = true;
}
+static void sdhci_tegra_cqe_enable(struct mmc_host *mmc)
+{
+ struct cqhci_host *cq_host = mmc->cqe_private;
+ u32 cqcfg = 0;
+
+ /*
+ * Tegra SDMMC Controller design prevents write access to BLOCK_COUNT
+ * registers when CQE is enabled.
+ */
+ cqcfg = cqhci_readl(cq_host, CQHCI_CFG);
+ if (cqcfg & CQHCI_ENABLE)
+ cqhci_writel(cq_host, (cqcfg & ~CQHCI_ENABLE), CQHCI_CFG);
+
+ sdhci_cqe_enable(mmc);
+
+ if (cqcfg & CQHCI_ENABLE)
+ cqhci_writel(cq_host, cqcfg, CQHCI_CFG);
+}
+
+static void sdhci_tegra_dumpregs(struct mmc_host *mmc)
+{
+ sdhci_dumpregs(mmc_priv(mmc));
+}
+
+static u32 sdhci_tegra_cqhci_irq(struct sdhci_host *host, u32 intmask)
+{
+ int cmd_error = 0;
+ int data_error = 0;
+
+ if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
+ return intmask;
+
+ cqhci_irq(host->mmc, intmask, cmd_error, data_error);
+
+ return 0;
+}
+
+static const struct cqhci_host_ops sdhci_tegra_cqhci_ops = {
+ .enable = sdhci_tegra_cqe_enable,
+ .disable = sdhci_cqe_disable,
+ .dumpregs = sdhci_tegra_dumpregs,
+};
+
static const struct sdhci_ops tegra_sdhci_ops = {
.get_ro = tegra_sdhci_get_ro,
.read_w = tegra_sdhci_readw,
@@ -989,6 +1051,7 @@ static const struct sdhci_ops tegra186_sdhci_ops = {
.set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
.voltage_switch = tegra_sdhci_voltage_switch,
.get_max_clock = tegra_sdhci_get_max_clock,
+ .irq = sdhci_tegra_cqhci_irq,
};
static const struct sdhci_pltfm_data sdhci_tegra186_pdata = {
@@ -1030,6 +1093,54 @@ static const struct of_device_id sdhci_tegra_dt_match[] = {
};
MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match);
+static int sdhci_tegra_add_host(struct sdhci_host *host)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
+ struct cqhci_host *cq_host;
+ bool dma64;
+ int ret;
+
+ if (!tegra_host->enable_hwcq)
+ return sdhci_add_host(host);
+
+ sdhci_enable_v4_mode(host);
+
+ ret = sdhci_setup_host(host);
+ if (ret)
+ return ret;
+
+ host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
+
+ cq_host = devm_kzalloc(host->mmc->parent,
+ sizeof(*cq_host), GFP_KERNEL);
+ if (!cq_host) {
+ ret = -ENOMEM;
+ goto cleanup;
+ }
+
+ cq_host->mmio = host->ioaddr + SDHCI_TEGRA_CQE_BASE_ADDR;
+ cq_host->ops = &sdhci_tegra_cqhci_ops;
+
+ dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
+ if (dma64)
+ cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
+
+ ret = cqhci_init(cq_host, host->mmc, dma64);
+ if (ret)
+ goto cleanup;
+
+ ret = __sdhci_add_host(host);
+ if (ret)
+ goto cleanup;
+
+ return 0;
+
+cleanup:
+ sdhci_cleanup_host(host);
+ return ret;
+}
+
static int sdhci_tegra_probe(struct platform_device *pdev)
{
const struct of_device_id *match;
@@ -1077,9 +1188,7 @@ static int sdhci_tegra_probe(struct platform_device *pdev)
if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
host->mmc->caps |= MMC_CAP_1_8V_DDR;
- tegra_sdhci_parse_pad_autocal_dt(host);
-
- tegra_sdhci_parse_tap_and_trim(host);
+ tegra_sdhci_parse_dt(host);
tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power",
GPIOD_OUT_HIGH);
@@ -1117,7 +1226,7 @@ static int sdhci_tegra_probe(struct platform_device *pdev)
usleep_range(2000, 4000);
- rc = sdhci_add_host(host);
+ rc = sdhci_tegra_add_host(host);
if (rc)
goto err_add_host;
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index a22e11a65658..c6afe793399e 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -3353,7 +3353,14 @@ void sdhci_cqe_enable(struct mmc_host *mmc)
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
ctrl &= ~SDHCI_CTRL_DMA_MASK;
- if (host->flags & SDHCI_USE_64_BIT_DMA)
+ /*
+ * Host from V4.10 supports ADMA3 DMA type.
+ * ADMA3 performs integrated descriptor which is more suitable
+ * for cmd queuing to fetch both command and transfer descriptors.
+ */
+ if (host->v4_mode && (host->caps1 & SDHCI_CAN_DO_ADMA3))
+ ctrl |= SDHCI_CTRL_ADMA3;
+ else if (host->flags & SDHCI_USE_64_BIT_DMA)
ctrl |= SDHCI_CTRL_ADMA64;
else
ctrl |= SDHCI_CTRL_ADMA32;
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 6cc9a3c2ac66..4070be49d947 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -88,6 +88,7 @@
#define SDHCI_CTRL_ADMA1 0x08
#define SDHCI_CTRL_ADMA32 0x10
#define SDHCI_CTRL_ADMA64 0x18
+#define SDHCI_CTRL_ADMA3 0x18
#define SDHCI_CTRL_8BITBUS 0x20
#define SDHCI_CTRL_CDTEST_INS 0x40
#define SDHCI_CTRL_CDTEST_EN 0x80
@@ -230,6 +231,7 @@
#define SDHCI_RETUNING_MODE_SHIFT 14
#define SDHCI_CLOCK_MUL_MASK 0x00FF0000
#define SDHCI_CLOCK_MUL_SHIFT 16
+#define SDHCI_CAN_DO_ADMA3 0x08000000
#define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */
#define SDHCI_CAPABILITIES_1 0x44
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH V9 1/3] dt-bindings: mmc: tegra: Add supports-cqe property
2019-01-15 19:03 [PATCH V9 1/3] dt-bindings: mmc: tegra: Add supports-cqe property Sowjanya Komatineni
2019-01-15 19:03 ` [PATCH V9 2/3] arm64: dts: tegra: Add CQE Support for SDMMC4 Sowjanya Komatineni
2019-01-15 19:03 ` [PATCH V9 3/3] mmc: tegra: HW Command Queue Support for Tegra SDMMC Sowjanya Komatineni
@ 2019-01-21 10:41 ` Thierry Reding
2019-01-21 10:43 ` Thierry Reding
3 siblings, 0 replies; 8+ messages in thread
From: Thierry Reding @ 2019-01-21 10:41 UTC (permalink / raw)
To: Sowjanya Komatineni
Cc: robh+dt, mark.rutland, mperttunen, chunyan.zhang, jonathanh,
adrian.hunter, ulf.hansson, anrao, devicetree, linux-tegra,
linux-kernel, linux-mmc
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On Tue, Jan 15, 2019 at 11:03:50AM -0800, Sowjanya Komatineni wrote:
> Add supports-cqe optional property for Tegra SDMMC.
>
> Tegra186 and Tegra194 supports HW Command queue only
> on SDMMC4 controller. This property is used to identify
> command queue support controller in the tegra sdhci driver.
>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 4 ++++
> 1 file changed, 4 insertions(+)
Acked-by: Thierry Reding <treding@nvidia.com>
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH V9 1/3] dt-bindings: mmc: tegra: Add supports-cqe property
2019-01-15 19:03 [PATCH V9 1/3] dt-bindings: mmc: tegra: Add supports-cqe property Sowjanya Komatineni
` (2 preceding siblings ...)
2019-01-21 10:41 ` [PATCH V9 1/3] dt-bindings: mmc: tegra: Add supports-cqe property Thierry Reding
@ 2019-01-21 10:43 ` Thierry Reding
2019-01-21 14:31 ` Rob Herring
3 siblings, 1 reply; 8+ messages in thread
From: Thierry Reding @ 2019-01-21 10:43 UTC (permalink / raw)
To: Sowjanya Komatineni, Rob Herring
Cc: robh+dt, mark.rutland, mperttunen, chunyan.zhang, jonathanh,
adrian.hunter, ulf.hansson, anrao, devicetree, linux-tegra,
linux-kernel, linux-mmc
[-- Attachment #1: Type: text/plain, Size: 1757 bytes --]
On Tue, Jan 15, 2019 at 11:03:50AM -0800, Sowjanya Komatineni wrote:
> Add supports-cqe optional property for Tegra SDMMC.
>
> Tegra186 and Tegra194 supports HW Command queue only
> on SDMMC4 controller. This property is used to identify
> command queue support controller in the tegra sdhci driver.
>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> index 32b4b4e41923..fb14c2c8d7ee 100644
> --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> @@ -72,6 +72,10 @@ Optional properties for Tegra210 and Tegra186:
> - nvidia,default-trim : Specify the default outbound clock trimmer
> value.
> - nvidia,dqs-trim : Specify DQS trim value for HS400 timing
> +- supports-cqe : The presence of this property indicates that the
> + corresponding controller supports HW command queue feature.
> + Tegra186 and Tegra194 has 4 SDMMC Controllers and only SDMMC4
> + controller supports HW Command Queue with eMMC device.
Hi Rob,
are you okay with the property name for this. I'm wondering if it should
have a vendor prefix or not, but I suspect that something like this may
be needed for other vendors as well, so not having a vendor prefix could
be warranted in this case.
Thierry
>
> Notes on the pad calibration pull up and pulldown offset values:
> - The property values are drive codes which are programmed into the
> --
> 2.7.4
>
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH V9 3/3] mmc: tegra: HW Command Queue Support for Tegra SDMMC
2019-01-15 19:03 ` [PATCH V9 3/3] mmc: tegra: HW Command Queue Support for Tegra SDMMC Sowjanya Komatineni
@ 2019-01-21 10:44 ` Thierry Reding
2019-01-21 12:52 ` Adrian Hunter
0 siblings, 1 reply; 8+ messages in thread
From: Thierry Reding @ 2019-01-21 10:44 UTC (permalink / raw)
To: Sowjanya Komatineni
Cc: robh+dt, mark.rutland, mperttunen, chunyan.zhang, jonathanh,
adrian.hunter, ulf.hansson, anrao, devicetree, linux-tegra,
linux-kernel, linux-mmc
[-- Attachment #1: Type: text/plain, Size: 711 bytes --]
On Tue, Jan 15, 2019 at 11:03:52AM -0800, Sowjanya Komatineni wrote:
> This patch adds HW Command Queue for supported Tegra SDMMC
> controllers.
>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> drivers/mmc/host/Kconfig | 1 +
> drivers/mmc/host/sdhci-tegra.c | 117 +++++++++++++++++++++++++++++++++++++++--
> drivers/mmc/host/sdhci.c | 9 +++-
> drivers/mmc/host/sdhci.h | 2 +
> 4 files changed, 124 insertions(+), 5 deletions(-)
Looks good to me. It might be worth splitting off the SDHCI core changes
into a separate patch, but that's for Adrian and Ulf to decide. From a
Tegra point of view:
Acked-by: Thierry Reding <treding@nvidia.com>
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH V9 3/3] mmc: tegra: HW Command Queue Support for Tegra SDMMC
2019-01-21 10:44 ` Thierry Reding
@ 2019-01-21 12:52 ` Adrian Hunter
0 siblings, 0 replies; 8+ messages in thread
From: Adrian Hunter @ 2019-01-21 12:52 UTC (permalink / raw)
To: Thierry Reding, Sowjanya Komatineni
Cc: robh+dt, mark.rutland, mperttunen, chunyan.zhang, jonathanh,
ulf.hansson, anrao, devicetree, linux-tegra, linux-kernel,
linux-mmc
On 21/01/19 12:44 PM, Thierry Reding wrote:
> On Tue, Jan 15, 2019 at 11:03:52AM -0800, Sowjanya Komatineni wrote:
>> This patch adds HW Command Queue for supported Tegra SDMMC
>> controllers.
>>
>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>> ---
>> drivers/mmc/host/Kconfig | 1 +
>> drivers/mmc/host/sdhci-tegra.c | 117 +++++++++++++++++++++++++++++++++++++++--
>> drivers/mmc/host/sdhci.c | 9 +++-
>> drivers/mmc/host/sdhci.h | 2 +
>> 4 files changed, 124 insertions(+), 5 deletions(-)
>
> Looks good to me. It might be worth splitting off the SDHCI core changes
> into a separate patch, but that's for Adrian and Ulf to decide. From a
Yes that would be better. Otherwise seems fine.
> Tegra point of view:
>
> Acked-by: Thierry Reding <treding@nvidia.com>
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH V9 1/3] dt-bindings: mmc: tegra: Add supports-cqe property
2019-01-21 10:43 ` Thierry Reding
@ 2019-01-21 14:31 ` Rob Herring
0 siblings, 0 replies; 8+ messages in thread
From: Rob Herring @ 2019-01-21 14:31 UTC (permalink / raw)
To: Thierry Reding
Cc: Sowjanya Komatineni, mark.rutland, mperttunen, chunyan.zhang,
jonathanh, adrian.hunter, ulf.hansson, anrao, devicetree,
linux-tegra, linux-kernel, linux-mmc
On Mon, Jan 21, 2019 at 11:43:33AM +0100, Thierry Reding wrote:
> On Tue, Jan 15, 2019 at 11:03:50AM -0800, Sowjanya Komatineni wrote:
> > Add supports-cqe optional property for Tegra SDMMC.
> >
> > Tegra186 and Tegra194 supports HW Command queue only
> > on SDMMC4 controller. This property is used to identify
> > command queue support controller in the tegra sdhci driver.
> >
> > Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> > ---
> > Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> > index 32b4b4e41923..fb14c2c8d7ee 100644
> > --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> > +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> > @@ -72,6 +72,10 @@ Optional properties for Tegra210 and Tegra186:
> > - nvidia,default-trim : Specify the default outbound clock trimmer
> > value.
> > - nvidia,dqs-trim : Specify DQS trim value for HS400 timing
> > +- supports-cqe : The presence of this property indicates that the
> > + corresponding controller supports HW command queue feature.
> > + Tegra186 and Tegra194 has 4 SDMMC Controllers and only SDMMC4
> > + controller supports HW Command Queue with eMMC device.
>
> Hi Rob,
>
> are you okay with the property name for this. I'm wondering if it should
> have a vendor prefix or not, but I suspect that something like this may
> be needed for other vendors as well, so not having a vendor prefix could
> be warranted in this case.
Seems likely. Please document with common MMC properties in that case.
Rob
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2019-01-21 14:31 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-01-15 19:03 [PATCH V9 1/3] dt-bindings: mmc: tegra: Add supports-cqe property Sowjanya Komatineni
2019-01-15 19:03 ` [PATCH V9 2/3] arm64: dts: tegra: Add CQE Support for SDMMC4 Sowjanya Komatineni
2019-01-15 19:03 ` [PATCH V9 3/3] mmc: tegra: HW Command Queue Support for Tegra SDMMC Sowjanya Komatineni
2019-01-21 10:44 ` Thierry Reding
2019-01-21 12:52 ` Adrian Hunter
2019-01-21 10:41 ` [PATCH V9 1/3] dt-bindings: mmc: tegra: Add supports-cqe property Thierry Reding
2019-01-21 10:43 ` Thierry Reding
2019-01-21 14:31 ` Rob Herring
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