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From: Atish Patra <atish.patra@wdc.com>
To: linux-riscv@lists.infradead.org
Cc: Atish Patra <atish.patra@wdc.com>,
	Alan Kao <alankao@andestech.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Andreas Schwab <schwab@suse.de>, Anup Patel <anup@brainfault.org>,
	Dmitriy Cherkasov <dmitriy@oss-tech.org>,
	Johan Hovold <johan@kernel.org>,
	linux-kernel@vger.kernel.org, Palmer Dabbelt <palmer@sifive.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Thomas Gleixner <tglx@linutronix.de>
Subject: [v6 PATCH 6/6] RISC-V: Assign hwcap as per comman capabilities.
Date: Fri, 22 Feb 2019 11:41:40 -0800	[thread overview]
Message-ID: <1550864500-13652-7-git-send-email-atish.patra@wdc.com> (raw)
In-Reply-To: <1550864500-13652-1-git-send-email-atish.patra@wdc.com>

Currently, we set hwcap based on first valid hart from DT. This may not
be correct always as that hart might not be current booting cpu or may
have a different capability.

Set hwcap as the capabilities supported by all possible harts with "okay"
status.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
 arch/riscv/kernel/cpufeature.c | 41 ++++++++++++++++++++++-------------------
 1 file changed, 22 insertions(+), 19 deletions(-)

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index e7a4701f..bc29b010 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -20,6 +20,7 @@
 #include <linux/of.h>
 #include <asm/processor.h>
 #include <asm/hwcap.h>
+#include <asm/smp.h>
 
 unsigned long elf_hwcap __read_mostly;
 #ifdef CONFIG_FPU
@@ -42,28 +43,30 @@ void riscv_fill_hwcap(void)
 
 	elf_hwcap = 0;
 
-	/*
-	 * We don't support running Linux on hertergenous ISA systems.  For
-	 * now, we just check the ISA of the first "okay" processor.
-	 */
 	for_each_of_cpu_node(node) {
-		if (riscv_of_processor_hartid(node) >= 0)
-			break;
-	}
-	if (!node) {
-		pr_warn("Unable to find \"cpu\" devicetree entry\n");
-		return;
-	}
+		unsigned long this_hwcap = 0;
 
-	if (of_property_read_string(node, "riscv,isa", &isa)) {
-		pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
-		of_node_put(node);
-		return;
-	}
-	of_node_put(node);
+		if (riscv_of_processor_hartid(node) < 0)
+			continue;
 
-	for (i = 0; i < strlen(isa); ++i)
-		elf_hwcap |= isa2hwcap[(unsigned char)(isa[i])];
+		if (of_property_read_string(node, "riscv,isa", &isa)) {
+			pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
+			continue;
+		}
+
+		for (i = 0; i < strlen(isa); ++i)
+			this_hwcap |= isa2hwcap[(unsigned char)(isa[i])];
+
+		/*
+		 * All "okay" hart should have same isa. Set HWCAP based on
+		 * common capabilities of every "okay" hart, in case they don't
+		 * have.
+		 */
+		if (elf_hwcap)
+			elf_hwcap &= this_hwcap;
+		else
+			elf_hwcap = this_hwcap;
+	}
 
 	/* We don't support systems with F but without D, so mask those out
 	 * here. */
-- 
2.7.4


  parent reply	other threads:[~2019-02-22 19:41 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-02-22 19:41 [v6 PATCH 0/6] Various SMP related fixes Atish Patra
2019-02-22 19:41 ` [v6 PATCH 1/6] RISC-V: Do not wait indefinitely in __cpu_up Atish Patra
2019-02-22 19:41 ` [v6 PATCH 2/6] RISC-V: Move cpuid to hartid mapping to SMP Atish Patra
2019-02-22 19:41 ` [v6 PATCH 3/6] RISC-V: Remove NR_CPUs check during hartid search from DT Atish Patra
2019-02-22 19:41 ` [v6 PATCH 4/6] RISC-V: Allow hartid-to-cpuid function to fail Atish Patra
2019-02-22 19:41 ` [v6 PATCH 5/6] RISC-V: Compare cpuid with NR_CPUS before mapping Atish Patra
2019-02-22 19:41 ` Atish Patra [this message]
2019-02-25  3:35   ` [v6 PATCH 6/6] RISC-V: Assign hwcap as per comman capabilities Anup Patel
2019-02-25  8:34   ` Johan Hovold
2019-03-04  8:36   ` Andreas Schwab
2019-03-04 19:06 ` [v6 PATCH 0/6] Various SMP related fixes Palmer Dabbelt

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