* [PATCH V7 1/2] arm64: dts: freescale: imx8qxp: add cpu opp table
@ 2019-02-26 5:17 Anson Huang
2019-02-26 5:17 ` [PATCH V7 2/2] clk: imx: scu: add cpu frequency scaling support Anson Huang
2019-02-28 3:18 ` [PATCH V7 1/2] arm64: dts: freescale: imx8qxp: add cpu opp table Shawn Guo
0 siblings, 2 replies; 6+ messages in thread
From: Anson Huang @ 2019-02-26 5:17 UTC (permalink / raw)
To: robh+dt, mark.rutland, shawnguo, s.hauer, kernel, festevam,
mturquette, sboyd, Aisheng Dong, Daniel Baluta, devicetree,
linux-arm-kernel, linux-kernel, linux-clk
Cc: dl-linux-imx
Add i.MX8QXP CPU opp table to support cpufreq.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
---
No changes since V6.
---
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 4c3dd95..41bf0ce 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -34,6 +34,9 @@
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
+ clocks = <&clk IMX_A35_CLK>;
+ operating-points-v2 = <&a35_0_opp_table>;
+ #cooling-cells = <2>;
};
A35_1: cpu@1 {
@@ -42,6 +45,9 @@
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
+ clocks = <&clk IMX_A35_CLK>;
+ operating-points-v2 = <&a35_0_opp_table>;
+ #cooling-cells = <2>;
};
A35_2: cpu@2 {
@@ -50,6 +56,9 @@
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
+ clocks = <&clk IMX_A35_CLK>;
+ operating-points-v2 = <&a35_0_opp_table>;
+ #cooling-cells = <2>;
};
A35_3: cpu@3 {
@@ -58,6 +67,9 @@
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
+ clocks = <&clk IMX_A35_CLK>;
+ operating-points-v2 = <&a35_0_opp_table>;
+ #cooling-cells = <2>;
};
A35_L2: l2-cache0 {
@@ -65,6 +77,24 @@
};
};
+ a35_0_opp_table: opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <150000>;
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <150000>;
+ opp-suspend;
+ };
+ };
+
gic: interrupt-controller@51a00000 {
compatible = "arm,gic-v3";
reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH V7 2/2] clk: imx: scu: add cpu frequency scaling support
2019-02-26 5:17 [PATCH V7 1/2] arm64: dts: freescale: imx8qxp: add cpu opp table Anson Huang
@ 2019-02-26 5:17 ` Anson Huang
2019-02-26 18:08 ` Stephen Boyd
2019-02-28 3:18 ` [PATCH V7 1/2] arm64: dts: freescale: imx8qxp: add cpu opp table Shawn Guo
1 sibling, 1 reply; 6+ messages in thread
From: Anson Huang @ 2019-02-26 5:17 UTC (permalink / raw)
To: robh+dt, mark.rutland, shawnguo, s.hauer, kernel, festevam,
mturquette, sboyd, Aisheng Dong, Daniel Baluta, devicetree,
linux-arm-kernel, linux-kernel, linux-clk
Cc: dl-linux-imx
On NXP's i.MX SoCs with system controller inside, CPU frequency
scaling can ONLY be done by system controller firmware, and it
can ONLY be requested from secure mode, so Linux kernel has to
call ARM SMC to trap to ARM-Trusted-Firmware to request system
controller firmware to do CPU frequency scaling.
This patch adds i.MX system controller CPU frequency scaling support,
it reuses cpufreq-dt driver and implement the CPU frequency scaling
inside SCU clock driver.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
Changes since V6:
- add return fail to clk_scu_atf_set_cpu_rate() when the resource ID
is NOT expected, this is to avoid warning of uninitialized data usage.
---
drivers/clk/imx/clk-scu.c | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c
index f460526..fbef740 100644
--- a/drivers/clk/imx/clk-scu.c
+++ b/drivers/clk/imx/clk-scu.c
@@ -4,12 +4,17 @@
* Dong Aisheng <aisheng.dong@nxp.com>
*/
+#include <dt-bindings/firmware/imx/rsrc.h>
+#include <linux/arm-smccc.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/slab.h>
#include "clk-scu.h"
+#define IMX_SIP_CPUFREQ 0xC2000001
+#define IMX_SIP_SET_CPUFREQ 0x00
+
static struct imx_sc_ipc *ccm_ipc_handle;
/*
@@ -180,6 +185,25 @@ static long clk_scu_round_rate(struct clk_hw *hw, unsigned long rate,
return rate;
}
+static int clk_scu_atf_set_cpu_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_scu *clk = to_clk_scu(hw);
+ struct arm_smccc_res res;
+ unsigned long cluster_id;
+
+ if (clk->rsrc_id == IMX_SC_R_A35)
+ cluster_id = 0;
+ else
+ return -EINVAL;
+
+ /* CPU frequency scaling can ONLY be done by ARM-Trusted-Firmware */
+ arm_smccc_smc(IMX_SIP_CPUFREQ, IMX_SIP_SET_CPUFREQ,
+ cluster_id, rate, 0, 0, 0, 0, &res);
+
+ return 0;
+}
+
/*
* clk_scu_set_rate - Set rate for a SCU clock
* @hw: clock to change rate for
@@ -312,6 +336,14 @@ static const struct clk_ops clk_scu_ops = {
.unprepare = clk_scu_unprepare,
};
+static const struct clk_ops clk_scu_cpu_ops = {
+ .recalc_rate = clk_scu_recalc_rate,
+ .round_rate = clk_scu_round_rate,
+ .set_rate = clk_scu_atf_set_cpu_rate,
+ .prepare = clk_scu_prepare,
+ .unprepare = clk_scu_unprepare,
+};
+
struct clk_hw *__imx_clk_scu(const char *name, const char * const *parents,
int num_parents, u32 rsrc_id, u8 clk_type)
{
@@ -329,6 +361,10 @@ struct clk_hw *__imx_clk_scu(const char *name, const char * const *parents,
init.name = name;
init.ops = &clk_scu_ops;
+ if (rsrc_id == IMX_SC_R_A35)
+ init.ops = &clk_scu_cpu_ops;
+ else
+ init.ops = &clk_scu_ops;
init.parent_names = parents;
init.num_parents = num_parents;
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH V7 2/2] clk: imx: scu: add cpu frequency scaling support
2019-02-26 5:17 ` [PATCH V7 2/2] clk: imx: scu: add cpu frequency scaling support Anson Huang
@ 2019-02-26 18:08 ` Stephen Boyd
0 siblings, 0 replies; 6+ messages in thread
From: Stephen Boyd @ 2019-02-26 18:08 UTC (permalink / raw)
To: devicetree, festevam, kernel, linux-arm-kernel, linux-clk,
linux-kernel, mark.rutland, mturquette, robh+dt, s.hauer,
shawnguo, Aisheng Dong, Anson Huang, Daniel Baluta
Cc: dl-linux-imx
Quoting Anson Huang (2019-02-25 21:17:36)
> On NXP's i.MX SoCs with system controller inside, CPU frequency
> scaling can ONLY be done by system controller firmware, and it
> can ONLY be requested from secure mode, so Linux kernel has to
> call ARM SMC to trap to ARM-Trusted-Firmware to request system
> controller firmware to do CPU frequency scaling.
>
> This patch adds i.MX system controller CPU frequency scaling support,
> it reuses cpufreq-dt driver and implement the CPU frequency scaling
> inside SCU clock driver.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH V7 1/2] arm64: dts: freescale: imx8qxp: add cpu opp table
2019-02-26 5:17 [PATCH V7 1/2] arm64: dts: freescale: imx8qxp: add cpu opp table Anson Huang
2019-02-26 5:17 ` [PATCH V7 2/2] clk: imx: scu: add cpu frequency scaling support Anson Huang
@ 2019-02-28 3:18 ` Shawn Guo
2019-02-28 6:18 ` Anson Huang
1 sibling, 1 reply; 6+ messages in thread
From: Shawn Guo @ 2019-02-28 3:18 UTC (permalink / raw)
To: Anson Huang
Cc: robh+dt, mark.rutland, s.hauer, kernel, festevam, mturquette,
sboyd, Aisheng Dong, Daniel Baluta, devicetree, linux-arm-kernel,
linux-kernel, linux-clk, dl-linux-imx
On Tue, Feb 26, 2019 at 05:17:31AM +0000, Anson Huang wrote:
> Add i.MX8QXP CPU opp table to support cpufreq.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Prefix 'arm64: dts: imx8qxp: ' would already be clear enough. I dropped
'freescale' from there and applied patch.
> ---
> No changes since V6.
> ---
> arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 30 ++++++++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> index 4c3dd95..41bf0ce 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> @@ -34,6 +34,9 @@
> reg = <0x0 0x0>;
> enable-method = "psci";
> next-level-cache = <&A35_L2>;
> + clocks = <&clk IMX_A35_CLK>;
> + operating-points-v2 = <&a35_0_opp_table>;
> + #cooling-cells = <2>;
> };
>
> A35_1: cpu@1 {
> @@ -42,6 +45,9 @@
> reg = <0x0 0x1>;
> enable-method = "psci";
> next-level-cache = <&A35_L2>;
> + clocks = <&clk IMX_A35_CLK>;
> + operating-points-v2 = <&a35_0_opp_table>;
> + #cooling-cells = <2>;
> };
>
> A35_2: cpu@2 {
> @@ -50,6 +56,9 @@
> reg = <0x0 0x2>;
> enable-method = "psci";
> next-level-cache = <&A35_L2>;
> + clocks = <&clk IMX_A35_CLK>;
> + operating-points-v2 = <&a35_0_opp_table>;
> + #cooling-cells = <2>;
> };
>
> A35_3: cpu@3 {
> @@ -58,6 +67,9 @@
> reg = <0x0 0x3>;
> enable-method = "psci";
> next-level-cache = <&A35_L2>;
> + clocks = <&clk IMX_A35_CLK>;
> + operating-points-v2 = <&a35_0_opp_table>;
> + #cooling-cells = <2>;
> };
>
> A35_L2: l2-cache0 {
> @@ -65,6 +77,24 @@
> };
> };
>
> + a35_0_opp_table: opp-table {
What does the '0' in the label mean?
Shawn
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-900000000 {
> + opp-hz = /bits/ 64 <900000000>;
> + opp-microvolt = <1000000>;
> + clock-latency-ns = <150000>;
> + };
> +
> + opp-1200000000 {
> + opp-hz = /bits/ 64 <1200000000>;
> + opp-microvolt = <1100000>;
> + clock-latency-ns = <150000>;
> + opp-suspend;
> + };
> + };
> +
> gic: interrupt-controller@51a00000 {
> compatible = "arm,gic-v3";
> reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
> --
> 2.7.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH V7 1/2] arm64: dts: freescale: imx8qxp: add cpu opp table
2019-02-28 3:18 ` [PATCH V7 1/2] arm64: dts: freescale: imx8qxp: add cpu opp table Shawn Guo
@ 2019-02-28 6:18 ` Anson Huang
2019-02-28 6:42 ` Shawn Guo
0 siblings, 1 reply; 6+ messages in thread
From: Anson Huang @ 2019-02-28 6:18 UTC (permalink / raw)
To: Shawn Guo
Cc: robh+dt, mark.rutland, s.hauer, kernel, festevam, mturquette,
sboyd, Aisheng Dong, Daniel Baluta, devicetree, linux-arm-kernel,
linux-kernel, linux-clk, dl-linux-imx
Hi, Shawn
Best Regards!
Anson Huang
> -----Original Message-----
> From: Shawn Guo [mailto:shawnguo@kernel.org]
> Sent: 2019年2月28日 11:19
> To: Anson Huang <anson.huang@nxp.com>
> Cc: robh+dt@kernel.org; mark.rutland@arm.com; s.hauer@pengutronix.de;
> kernel@pengutronix.de; festevam@gmail.com; mturquette@baylibre.com;
> sboyd@kernel.org; Aisheng Dong <aisheng.dong@nxp.com>; Daniel Baluta
> <daniel.baluta@nxp.com>; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
> clk@vger.kernel.org; dl-linux-imx <linux-imx@nxp.com>
> Subject: Re: [PATCH V7 1/2] arm64: dts: freescale: imx8qxp: add cpu opp
> table
>
> On Tue, Feb 26, 2019 at 05:17:31AM +0000, Anson Huang wrote:
> > Add i.MX8QXP CPU opp table to support cpufreq.
> >
> > Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> > Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
>
> Prefix 'arm64: dts: imx8qxp: ' would already be clear enough. I dropped
> 'freescale' from there and applied patch.
>
> > ---
> > No changes since V6.
> > ---
> > arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 30
> > ++++++++++++++++++++++++++++++
> > 1 file changed, 30 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > index 4c3dd95..41bf0ce 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > @@ -34,6 +34,9 @@
> > reg = <0x0 0x0>;
> > enable-method = "psci";
> > next-level-cache = <&A35_L2>;
> > + clocks = <&clk IMX_A35_CLK>;
> > + operating-points-v2 = <&a35_0_opp_table>;
> > + #cooling-cells = <2>;
> > };
> >
> > A35_1: cpu@1 {
> > @@ -42,6 +45,9 @@
> > reg = <0x0 0x1>;
> > enable-method = "psci";
> > next-level-cache = <&A35_L2>;
> > + clocks = <&clk IMX_A35_CLK>;
> > + operating-points-v2 = <&a35_0_opp_table>;
> > + #cooling-cells = <2>;
> > };
> >
> > A35_2: cpu@2 {
> > @@ -50,6 +56,9 @@
> > reg = <0x0 0x2>;
> > enable-method = "psci";
> > next-level-cache = <&A35_L2>;
> > + clocks = <&clk IMX_A35_CLK>;
> > + operating-points-v2 = <&a35_0_opp_table>;
> > + #cooling-cells = <2>;
> > };
> >
> > A35_3: cpu@3 {
> > @@ -58,6 +67,9 @@
> > reg = <0x0 0x3>;
> > enable-method = "psci";
> > next-level-cache = <&A35_L2>;
> > + clocks = <&clk IMX_A35_CLK>;
> > + operating-points-v2 = <&a35_0_opp_table>;
> > + #cooling-cells = <2>;
> > };
> >
> > A35_L2: l2-cache0 {
> > @@ -65,6 +77,24 @@
> > };
> > };
> >
> > + a35_0_opp_table: opp-table {
>
> What does the '0' in the label mean?
Looks like the '0' in the label is NOT necessary, we can just use 'a35_opp_table',
do you want me resend the patch to remove '0'?
Anson.
>
> Shawn
>
> > + compatible = "operating-points-v2";
> > + opp-shared;
> > +
> > + opp-900000000 {
> > + opp-hz = /bits/ 64 <900000000>;
> > + opp-microvolt = <1000000>;
> > + clock-latency-ns = <150000>;
> > + };
> > +
> > + opp-1200000000 {
> > + opp-hz = /bits/ 64 <1200000000>;
> > + opp-microvolt = <1100000>;
> > + clock-latency-ns = <150000>;
> > + opp-suspend;
> > + };
> > + };
> > +
> > gic: interrupt-controller@51a00000 {
> > compatible = "arm,gic-v3";
> > reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
> > --
> > 2.7.4
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel@lists.infradead.org
> > https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Flist
> > s.infradead.org%2Fmailman%2Flistinfo%2Flinux-arm-
> kernel&data=02%7C
> >
> 01%7Canson.huang%40nxp.com%7Cfe4ff92a639e4739c2a108d69d2b8e12%7
> C686ea1
> >
> d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636869207728398808&sd
> ata=oz%2
> > FPyAki6fkfQZqaSYkjWfo3m8S48sCzpDf2lxDIjKs%3D&reserved=0
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH V7 1/2] arm64: dts: freescale: imx8qxp: add cpu opp table
2019-02-28 6:18 ` Anson Huang
@ 2019-02-28 6:42 ` Shawn Guo
0 siblings, 0 replies; 6+ messages in thread
From: Shawn Guo @ 2019-02-28 6:42 UTC (permalink / raw)
To: Anson Huang
Cc: mark.rutland, Aisheng Dong, devicetree, sboyd, Daniel Baluta,
s.hauer, linux-kernel, linux-clk, robh+dt, dl-linux-imx, kernel,
festevam, mturquette, linux-arm-kernel
On Thu, Feb 28, 2019 at 06:18:30AM +0000, Anson Huang wrote:
> Hi, Shawn
>
> Best Regards!
> Anson Huang
>
> > -----Original Message-----
> > From: Shawn Guo [mailto:shawnguo@kernel.org]
> > Sent: 2019年2月28日 11:19
> > To: Anson Huang <anson.huang@nxp.com>
> > Cc: robh+dt@kernel.org; mark.rutland@arm.com; s.hauer@pengutronix.de;
> > kernel@pengutronix.de; festevam@gmail.com; mturquette@baylibre.com;
> > sboyd@kernel.org; Aisheng Dong <aisheng.dong@nxp.com>; Daniel Baluta
> > <daniel.baluta@nxp.com>; devicetree@vger.kernel.org; linux-arm-
> > kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
> > clk@vger.kernel.org; dl-linux-imx <linux-imx@nxp.com>
> > Subject: Re: [PATCH V7 1/2] arm64: dts: freescale: imx8qxp: add cpu opp
> > table
> >
> > On Tue, Feb 26, 2019 at 05:17:31AM +0000, Anson Huang wrote:
> > > Add i.MX8QXP CPU opp table to support cpufreq.
> > >
> > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> > > Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
> >
> > Prefix 'arm64: dts: imx8qxp: ' would already be clear enough. I dropped
> > 'freescale' from there and applied patch.
> >
> > > ---
> > > No changes since V6.
> > > ---
> > > arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 30
> > > ++++++++++++++++++++++++++++++
> > > 1 file changed, 30 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > > b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > > index 4c3dd95..41bf0ce 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > > @@ -34,6 +34,9 @@
> > > reg = <0x0 0x0>;
> > > enable-method = "psci";
> > > next-level-cache = <&A35_L2>;
> > > + clocks = <&clk IMX_A35_CLK>;
> > > + operating-points-v2 = <&a35_0_opp_table>;
> > > + #cooling-cells = <2>;
> > > };
> > >
> > > A35_1: cpu@1 {
> > > @@ -42,6 +45,9 @@
> > > reg = <0x0 0x1>;
> > > enable-method = "psci";
> > > next-level-cache = <&A35_L2>;
> > > + clocks = <&clk IMX_A35_CLK>;
> > > + operating-points-v2 = <&a35_0_opp_table>;
> > > + #cooling-cells = <2>;
> > > };
> > >
> > > A35_2: cpu@2 {
> > > @@ -50,6 +56,9 @@
> > > reg = <0x0 0x2>;
> > > enable-method = "psci";
> > > next-level-cache = <&A35_L2>;
> > > + clocks = <&clk IMX_A35_CLK>;
> > > + operating-points-v2 = <&a35_0_opp_table>;
> > > + #cooling-cells = <2>;
> > > };
> > >
> > > A35_3: cpu@3 {
> > > @@ -58,6 +67,9 @@
> > > reg = <0x0 0x3>;
> > > enable-method = "psci";
> > > next-level-cache = <&A35_L2>;
> > > + clocks = <&clk IMX_A35_CLK>;
> > > + operating-points-v2 = <&a35_0_opp_table>;
> > > + #cooling-cells = <2>;
> > > };
> > >
> > > A35_L2: l2-cache0 {
> > > @@ -65,6 +77,24 @@
> > > };
> > > };
> > >
> > > + a35_0_opp_table: opp-table {
> >
> > What does the '0' in the label mean?
>
> Looks like the '0' in the label is NOT necessary, we can just use 'a35_opp_table',
> do you want me resend the patch to remove '0'?
No. I just fixed it up and applied the patch.
Shawn
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-02-28 6:43 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2019-02-26 5:17 [PATCH V7 1/2] arm64: dts: freescale: imx8qxp: add cpu opp table Anson Huang
2019-02-26 5:17 ` [PATCH V7 2/2] clk: imx: scu: add cpu frequency scaling support Anson Huang
2019-02-26 18:08 ` Stephen Boyd
2019-02-28 3:18 ` [PATCH V7 1/2] arm64: dts: freescale: imx8qxp: add cpu opp table Shawn Guo
2019-02-28 6:18 ` Anson Huang
2019-02-28 6:42 ` Shawn Guo
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