* [PATCH 1/2] include: dt-binding: clock: Rename zynqmp header file
2019-02-27 20:51 [PATCH 0/2] Rename dt header and move clock binding Jolly Shah
@ 2019-02-27 20:51 ` Jolly Shah
2019-02-27 20:51 ` [PATCH 2/2] dt-bindings: xilinx: Separate clock binding from firmware doc Jolly Shah
2019-03-18 12:42 ` [PATCH 0/2] Rename dt header and move clock binding Michal Simek
2 siblings, 0 replies; 4+ messages in thread
From: Jolly Shah @ 2019-02-27 20:51 UTC (permalink / raw)
To: robh+dt
Cc: michal.simek, rajanv, linux-arm-kernel, linux-kernel, devicetree,
Jolly Shah, Rajan Vaja
Rename file name of ZynqMP clk dt-bindings to align with
file name of reset and power dt-bindings.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
---
.../firmware/xilinx/xlnx,zynqmp-firmware.txt | 2 +-
include/dt-bindings/clock/xlnx,zynqmp-clk.h | 116 -------------------
include/dt-bindings/clock/xlnx-zynqmp-clk.h | 126 +++++++++++++++++++++
3 files changed, 127 insertions(+), 117 deletions(-)
delete mode 100644 include/dt-bindings/clock/xlnx,zynqmp-clk.h
create mode 100644 include/dt-bindings/clock/xlnx-zynqmp-clk.h
diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
index 614bac5..45d259c 100644
--- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
+++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
@@ -62,7 +62,7 @@ order to provide an optional (E)MIO clock source:
Output clocks are registered based on clock information received
from firmware. Output clocks indexes are mentioned in
-include/dt-bindings/clock/xlnx,zynqmp-clk.h.
+include/dt-bindings/clock/xlnx-zynqmp-clk.h.
-------
Example
diff --git a/include/dt-bindings/clock/xlnx,zynqmp-clk.h b/include/dt-bindings/clock/xlnx,zynqmp-clk.h
deleted file mode 100644
index 4aebe6e..0000000
--- a/include/dt-bindings/clock/xlnx,zynqmp-clk.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Xilinx Zynq MPSoC Firmware layer
- *
- * Copyright (C) 2014-2018 Xilinx, Inc.
- *
- */
-
-#ifndef _DT_BINDINGS_CLK_ZYNQMP_H
-#define _DT_BINDINGS_CLK_ZYNQMP_H
-
-#define IOPLL 0
-#define RPLL 1
-#define APLL 2
-#define DPLL 3
-#define VPLL 4
-#define IOPLL_TO_FPD 5
-#define RPLL_TO_FPD 6
-#define APLL_TO_LPD 7
-#define DPLL_TO_LPD 8
-#define VPLL_TO_LPD 9
-#define ACPU 10
-#define ACPU_HALF 11
-#define DBF_FPD 12
-#define DBF_LPD 13
-#define DBG_TRACE 14
-#define DBG_TSTMP 15
-#define DP_VIDEO_REF 16
-#define DP_AUDIO_REF 17
-#define DP_STC_REF 18
-#define GDMA_REF 19
-#define DPDMA_REF 20
-#define DDR_REF 21
-#define SATA_REF 22
-#define PCIE_REF 23
-#define GPU_REF 24
-#define GPU_PP0_REF 25
-#define GPU_PP1_REF 26
-#define TOPSW_MAIN 27
-#define TOPSW_LSBUS 28
-#define GTGREF0_REF 29
-#define LPD_SWITCH 30
-#define LPD_LSBUS 31
-#define USB0_BUS_REF 32
-#define USB1_BUS_REF 33
-#define USB3_DUAL_REF 34
-#define USB0 35
-#define USB1 36
-#define CPU_R5 37
-#define CPU_R5_CORE 38
-#define CSU_SPB 39
-#define CSU_PLL 40
-#define PCAP 41
-#define IOU_SWITCH 42
-#define GEM_TSU_REF 43
-#define GEM_TSU 44
-#define GEM0_REF 45
-#define GEM1_REF 46
-#define GEM2_REF 47
-#define GEM3_REF 48
-#define GEM0_TX 49
-#define GEM1_TX 50
-#define GEM2_TX 51
-#define GEM3_TX 52
-#define QSPI_REF 53
-#define SDIO0_REF 54
-#define SDIO1_REF 55
-#define UART0_REF 56
-#define UART1_REF 57
-#define SPI0_REF 58
-#define SPI1_REF 59
-#define NAND_REF 60
-#define I2C0_REF 61
-#define I2C1_REF 62
-#define CAN0_REF 63
-#define CAN1_REF 64
-#define CAN0 65
-#define CAN1 66
-#define DLL_REF 67
-#define ADMA_REF 68
-#define TIMESTAMP_REF 69
-#define AMS_REF 70
-#define PL0_REF 71
-#define PL1_REF 72
-#define PL2_REF 73
-#define PL3_REF 74
-#define WDT 75
-#define IOPLL_INT 76
-#define IOPLL_PRE_SRC 77
-#define IOPLL_HALF 78
-#define IOPLL_INT_MUX 79
-#define IOPLL_POST_SRC 80
-#define RPLL_INT 81
-#define RPLL_PRE_SRC 82
-#define RPLL_HALF 83
-#define RPLL_INT_MUX 84
-#define RPLL_POST_SRC 85
-#define APLL_INT 86
-#define APLL_PRE_SRC 87
-#define APLL_HALF 88
-#define APLL_INT_MUX 89
-#define APLL_POST_SRC 90
-#define DPLL_INT 91
-#define DPLL_PRE_SRC 92
-#define DPLL_HALF 93
-#define DPLL_INT_MUX 94
-#define DPLL_POST_SRC 95
-#define VPLL_INT 96
-#define VPLL_PRE_SRC 97
-#define VPLL_HALF 98
-#define VPLL_INT_MUX 99
-#define VPLL_POST_SRC 100
-#define CAN0_MIO 101
-#define CAN1_MIO 102
-
-#endif
diff --git a/include/dt-bindings/clock/xlnx-zynqmp-clk.h b/include/dt-bindings/clock/xlnx-zynqmp-clk.h
new file mode 100644
index 0000000..cdc4c0b
--- /dev/null
+++ b/include/dt-bindings/clock/xlnx-zynqmp-clk.h
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Xilinx Zynq MPSoC Firmware layer
+ *
+ * Copyright (C) 2014-2018 Xilinx, Inc.
+ *
+ */
+
+#ifndef _DT_BINDINGS_CLK_ZYNQMP_H
+#define _DT_BINDINGS_CLK_ZYNQMP_H
+
+#define IOPLL 0
+#define RPLL 1
+#define APLL 2
+#define DPLL 3
+#define VPLL 4
+#define IOPLL_TO_FPD 5
+#define RPLL_TO_FPD 6
+#define APLL_TO_LPD 7
+#define DPLL_TO_LPD 8
+#define VPLL_TO_LPD 9
+#define ACPU 10
+#define ACPU_HALF 11
+#define DBF_FPD 12
+#define DBF_LPD 13
+#define DBG_TRACE 14
+#define DBG_TSTMP 15
+#define DP_VIDEO_REF 16
+#define DP_AUDIO_REF 17
+#define DP_STC_REF 18
+#define GDMA_REF 19
+#define DPDMA_REF 20
+#define DDR_REF 21
+#define SATA_REF 22
+#define PCIE_REF 23
+#define GPU_REF 24
+#define GPU_PP0_REF 25
+#define GPU_PP1_REF 26
+#define TOPSW_MAIN 27
+#define TOPSW_LSBUS 28
+#define GTGREF0_REF 29
+#define LPD_SWITCH 30
+#define LPD_LSBUS 31
+#define USB0_BUS_REF 32
+#define USB1_BUS_REF 33
+#define USB3_DUAL_REF 34
+#define USB0 35
+#define USB1 36
+#define CPU_R5 37
+#define CPU_R5_CORE 38
+#define CSU_SPB 39
+#define CSU_PLL 40
+#define PCAP 41
+#define IOU_SWITCH 42
+#define GEM_TSU_REF 43
+#define GEM_TSU 44
+#define GEM0_TX 45
+#define GEM1_TX 46
+#define GEM2_TX 47
+#define GEM3_TX 48
+#define GEM0_RX 49
+#define GEM1_RX 50
+#define GEM2_RX 51
+#define GEM3_RX 52
+#define QSPI_REF 53
+#define SDIO0_REF 54
+#define SDIO1_REF 55
+#define UART0_REF 56
+#define UART1_REF 57
+#define SPI0_REF 58
+#define SPI1_REF 59
+#define NAND_REF 60
+#define I2C0_REF 61
+#define I2C1_REF 62
+#define CAN0_REF 63
+#define CAN1_REF 64
+#define CAN0 65
+#define CAN1 66
+#define DLL_REF 67
+#define ADMA_REF 68
+#define TIMESTAMP_REF 69
+#define AMS_REF 70
+#define PL0_REF 71
+#define PL1_REF 72
+#define PL2_REF 73
+#define PL3_REF 74
+#define WDT 75
+#define IOPLL_INT 76
+#define IOPLL_PRE_SRC 77
+#define IOPLL_HALF 78
+#define IOPLL_INT_MUX 79
+#define IOPLL_POST_SRC 80
+#define RPLL_INT 81
+#define RPLL_PRE_SRC 82
+#define RPLL_HALF 83
+#define RPLL_INT_MUX 84
+#define RPLL_POST_SRC 85
+#define APLL_INT 86
+#define APLL_PRE_SRC 87
+#define APLL_HALF 88
+#define APLL_INT_MUX 89
+#define APLL_POST_SRC 90
+#define DPLL_INT 91
+#define DPLL_PRE_SRC 92
+#define DPLL_HALF 93
+#define DPLL_INT_MUX 94
+#define DPLL_POST_SRC 95
+#define VPLL_INT 96
+#define VPLL_PRE_SRC 97
+#define VPLL_HALF 98
+#define VPLL_INT_MUX 99
+#define VPLL_POST_SRC 100
+#define CAN0_MIO 101
+#define CAN1_MIO 102
+#define ACPU_FULL 103
+#define GEM0_REF 104
+#define GEM1_REF 105
+#define GEM2_REF 106
+#define GEM3_REF 107
+#define GEM0_REF_UNG 108
+#define GEM1_REF_UNG 109
+#define GEM2_REF_UNG 110
+#define GEM3_REF_UNG 111
+#define LPD_WDT 112
+
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] dt-bindings: xilinx: Separate clock binding from firmware doc
2019-02-27 20:51 [PATCH 0/2] Rename dt header and move clock binding Jolly Shah
2019-02-27 20:51 ` [PATCH 1/2] include: dt-binding: clock: Rename zynqmp header file Jolly Shah
@ 2019-02-27 20:51 ` Jolly Shah
2019-03-18 12:42 ` [PATCH 0/2] Rename dt header and move clock binding Michal Simek
2 siblings, 0 replies; 4+ messages in thread
From: Jolly Shah @ 2019-02-27 20:51 UTC (permalink / raw)
To: robh+dt
Cc: michal.simek, rajanv, linux-arm-kernel, linux-kernel, devicetree,
Rajan Vaja, Jolly Shah
From: Rajan Vaja <rajan.vaja@xilinx.com>
Clock description is part of firmware doc. Move clock description
in separate doc.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
---
.../devicetree/bindings/clock/xlnx,zynqmp-clk.txt | 63 ++++++++++++++++++++++
.../firmware/xilinx/xlnx,zynqmp-firmware.txt | 54 +------------------
2 files changed, 64 insertions(+), 53 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt
diff --git a/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt b/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt
new file mode 100644
index 0000000..391ee1a6
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt
@@ -0,0 +1,63 @@
+--------------------------------------------------------------------------
+Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using
+Zynq MPSoC firmware interface
+--------------------------------------------------------------------------
+The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock
+tree. It reads required input clock frequencies from the devicetree and acts
+as clock provider for all clock consumers of PS clocks.
+
+See clock_bindings.txt for more information on the generic clock bindings.
+
+Required properties:
+ - #clock-cells: Must be 1
+ - compatible: Must contain: "xlnx,zynqmp-clk"
+ - clocks: List of clock specifiers which are external input
+ clocks to the given clock controller. Please refer
+ the next section to find the input clocks for a
+ given controller.
+ - clock-names: List of clock names which are exteral input clocks
+ to the given clock controller. Please refer to the
+ clock bindings for more details.
+
+Input clocks for zynqmp Ultrascale+ clock controller:
+
+The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock
+inputs. These required clock inputs are:
+ - pss_ref_clk (PS reference clock)
+ - video_clk (reference clock for video system )
+ - pss_alt_ref_clk (alternative PS reference clock)
+ - aux_ref_clk
+ - gt_crx_ref_clk (transceiver reference clock)
+
+The following strings are optional parameters to the 'clock-names' property in
+order to provide an optional (E)MIO clock source:
+ - swdt0_ext_clk
+ - swdt1_ext_clk
+ - gem0_emio_clk
+ - gem1_emio_clk
+ - gem2_emio_clk
+ - gem3_emio_clk
+ - mio_clk_XX # with XX = 00..77
+ - mio_clk_50_or_51 #for the mux clock to gem tsu from 50 or 51
+
+
+Output clocks are registered based on clock information received
+from firmware. Output clocks indexes are mentioned in
+include/dt-bindings/clock/xlnx-zynqmp-clk.h.
+
+-------
+Example
+-------
+
+firmware {
+ zynqmp_firmware: zynqmp-firmware {
+ compatible = "xlnx,zynqmp-firmware";
+ method = "smc";
+ zynqmp_clk: clock-controller {
+ #clock-cells = <1>;
+ compatible = "xlnx,zynqmp-clk";
+ clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>;
+ clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
+ };
+ };
+};
diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
index 45d259c..a4fe136 100644
--- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
+++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
@@ -17,53 +17,6 @@ Required properties:
- "smc" : SMC #0, following the SMCCC
- "hvc" : HVC #0, following the SMCCC
---------------------------------------------------------------------------
-Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using
-Zynq MPSoC firmware interface
---------------------------------------------------------------------------
-The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock
-tree. It reads required input clock frequencies from the devicetree and acts
-as clock provider for all clock consumers of PS clocks.
-
-See clock_bindings.txt for more information on the generic clock bindings.
-
-Required properties:
- - #clock-cells: Must be 1
- - compatible: Must contain: "xlnx,zynqmp-clk"
- - clocks: List of clock specifiers which are external input
- clocks to the given clock controller. Please refer
- the next section to find the input clocks for a
- given controller.
- - clock-names: List of clock names which are exteral input clocks
- to the given clock controller. Please refer to the
- clock bindings for more details.
-
-Input clocks for zynqmp Ultrascale+ clock controller:
-
-The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock
-inputs. These required clock inputs are:
- - pss_ref_clk (PS reference clock)
- - video_clk (reference clock for video system )
- - pss_alt_ref_clk (alternative PS reference clock)
- - aux_ref_clk
- - gt_crx_ref_clk (transceiver reference clock)
-
-The following strings are optional parameters to the 'clock-names' property in
-order to provide an optional (E)MIO clock source:
- - swdt0_ext_clk
- - swdt1_ext_clk
- - gem0_emio_clk
- - gem1_emio_clk
- - gem2_emio_clk
- - gem3_emio_clk
- - mio_clk_XX # with XX = 00..77
- - mio_clk_50_or_51 #for the mux clock to gem tsu from 50 or 51
-
-
-Output clocks are registered based on clock information received
-from firmware. Output clocks indexes are mentioned in
-include/dt-bindings/clock/xlnx-zynqmp-clk.h.
-
-------
Example
-------
@@ -72,11 +25,6 @@ firmware {
zynqmp_firmware: zynqmp-firmware {
compatible = "xlnx,zynqmp-firmware";
method = "smc";
- zynqmp_clk: clock-controller {
- #clock-cells = <1>;
- compatible = "xlnx,zynqmp-clk";
- clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>;
- clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
- };
+ ...
};
};
--
2.7.4
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH 0/2] Rename dt header and move clock binding
2019-02-27 20:51 [PATCH 0/2] Rename dt header and move clock binding Jolly Shah
2019-02-27 20:51 ` [PATCH 1/2] include: dt-binding: clock: Rename zynqmp header file Jolly Shah
2019-02-27 20:51 ` [PATCH 2/2] dt-bindings: xilinx: Separate clock binding from firmware doc Jolly Shah
@ 2019-03-18 12:42 ` Michal Simek
2 siblings, 0 replies; 4+ messages in thread
From: Michal Simek @ 2019-03-18 12:42 UTC (permalink / raw)
To: Jolly Shah, robh+dt
Cc: michal.simek, rajanv, linux-arm-kernel, linux-kernel, devicetree,
Jolly Shah
On 27. 02. 19 21:51, Jolly Shah wrote:
> This patchset renames clock dt include file to align with other incldues.
> Other patch moves clock binding to a separate file under clock directory to
> align with other firmware child binding documenetation.
>
> Jolly Shah (1):
> include: dt-binding: clock: Rename zynqmp header file
>
> Rajan Vaja (1):
> dt-bindings: xilinx: Separate clock binding from firmware doc
>
> .../devicetree/bindings/clock/xlnx,zynqmp-clk.txt | 63 +++++++++++
> .../firmware/xilinx/xlnx,zynqmp-firmware.txt | 54 +--------
> include/dt-bindings/clock/xlnx,zynqmp-clk.h | 116 -------------------
> include/dt-bindings/clock/xlnx-zynqmp-clk.h | 126 +++++++++++++++++++++
> 4 files changed, 190 insertions(+), 169 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt
> delete mode 100644 include/dt-bindings/clock/xlnx,zynqmp-clk.h
> create mode 100644 include/dt-bindings/clock/xlnx-zynqmp-clk.h
>
I have applied this. Please let me know if you see any issue with it.
Thanks,
Michal
^ permalink raw reply [flat|nested] 4+ messages in thread