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From: Fenghua Yu <fenghua.yu@intel.com>
To: "Thomas Gleixner" <tglx@linutronix.de>,
	"Ingo Molnar" <mingo@redhat.com>, "H Peter Anvin" <hpa@zytor.com>,
	"Dave Hansen" <dave.hansen@intel.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Ashok Raj" <ashok.raj@intel.com>,
	"Peter Zijlstra" <peterz@infradead.org>,
	"Xiaoyao Li " <xiaoyao.li@intel.com>,
	"Michael Chan" <michael.chan@broadcom.com>,
	"Ravi V Shankar" <ravi.v.shankar@intel.com>
Cc: "linux-kernel" <linux-kernel@vger.kernel.org>,
	"x86" <x86@kernel.org>,
	linux-wireless@vger.kernel.org, netdev@vger.kernel.org,
	kvm@vger.kernel.org, Fenghua Yu <fenghua.yu@intel.com>
Subject: [PATCH v5 02/18] drivers/net/b44: Align pwol_mask to unsigned long for better performance
Date: Tue, 12 Mar 2019 16:00:20 -0700	[thread overview]
Message-ID: <1552431636-31511-3-git-send-email-fenghua.yu@intel.com> (raw)
In-Reply-To: <1552431636-31511-1-git-send-email-fenghua.yu@intel.com>

From: Peter Zijlstra <peterz@infradead.org>

A bit in pwol_mask is set in b44_magic_pattern by atomic set_bit.
But since pwol_mask is local and never exposed to concurrency, there is
no need to set bit in pwol_mask atomically.

set_bit sets the bit in a single unsigned long location. Because pwol_mask
may not be aligned to unsigned long, the location may cross two cache
lines and accessing the location degradates performance. On x86, accessing
two cache lines in locked instruction in set_bit is called split lock and
can cause overall performance degradation.

So we use non atomic __set_bit to set pwol_mask bits. __set_bit won't
hit split lock issue on x86.

Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
---
 drivers/net/ethernet/broadcom/b44.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/broadcom/b44.c b/drivers/net/ethernet/broadcom/b44.c
index 97ab0dd25552..5738ab963dfb 100644
--- a/drivers/net/ethernet/broadcom/b44.c
+++ b/drivers/net/ethernet/broadcom/b44.c
@@ -1520,7 +1520,7 @@ static int b44_magic_pattern(u8 *macaddr, u8 *ppattern, u8 *pmask, int offset)
 
 	memset(ppattern + offset, 0xff, magicsync);
 	for (j = 0; j < magicsync; j++)
-		set_bit(len++, (unsigned long *) pmask);
+		__set_bit(len++, (unsigned long *)pmask);
 
 	for (j = 0; j < B44_MAX_PATTERNS; j++) {
 		if ((B44_PATTERN_SIZE - len) >= ETH_ALEN)
@@ -1532,7 +1532,7 @@ static int b44_magic_pattern(u8 *macaddr, u8 *ppattern, u8 *pmask, int offset)
 		for (k = 0; k< ethaddr_bytes; k++) {
 			ppattern[offset + magicsync +
 				(j * ETH_ALEN) + k] = macaddr[k];
-			set_bit(len++, (unsigned long *) pmask);
+			__set_bit(len++, (unsigned long *)pmask);
 		}
 	}
 	return len - 1;
-- 
2.19.1


  parent reply	other threads:[~2019-03-12 23:11 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-12 23:00 [PATCH v5 00/18] x86/split_lock: Enable #AC exception for split locked accesses Fenghua Yu
2019-03-12 23:00 ` [PATCH v5 01/18] x86/common: Align cpu_caps_cleared and cpu_caps_set to unsigned long Fenghua Yu
2019-03-12 23:00 ` Fenghua Yu [this message]
2019-03-12 23:00 ` [PATCH v5 03/18] wlcore: simplify/fix/optimize reg_ch_conf_pending operations Fenghua Yu
2019-03-14 13:16   ` Kalle Valo
2019-03-14 23:16     ` Fenghua Yu
2019-03-15 17:17       ` Paolo Bonzini
2019-03-26  7:55         ` Kalle Valo
2019-03-12 23:00 ` [PATCH v5 04/18] x86/split_lock: Align x86_capability to unsigned long to avoid split locked access Fenghua Yu
2019-03-12 23:00 ` [PATCH v5 05/18] x86/cpufeatures: Enumerate IA32_CORE_CAPABILITIES MSR Fenghua Yu
2019-03-12 23:00 ` [PATCH v5 06/18] x86/msr-index: Define IA32_CORE_CAPABILITY MSR and #AC exception for split lock bit Fenghua Yu
2019-03-12 23:00 ` [PATCH v5 07/18] x86/split_lock: Enumerate #AC for split lock by MSR IA32_CORE_CAPABILITY Fenghua Yu
2019-03-12 23:52   ` Dave Hansen
2019-03-13  0:56     ` Fenghua Yu
2019-03-12 23:00 ` [PATCH v5 08/18] x86/split_lock: Define MSR TEST_CTL register Fenghua Yu
2019-03-12 23:00 ` [PATCH v5 09/18] x86/split_lock: Handle #AC exception for split lock Fenghua Yu
2019-03-12 23:51   ` Dave Hansen
2019-03-13  0:49     ` Fenghua Yu
2019-03-13 16:22       ` Dave Hansen
2019-03-12 23:00 ` [PATCH v5 10/18] kvm/x86: Emulate MSR IA32_CORE_CAPABILITY Fenghua Yu
2019-03-13  8:15   ` Paolo Bonzini
2019-03-12 23:00 ` [PATCH v5 11/18] kvm/vmx: Emulate MSR TEST_CTL Fenghua Yu
2019-03-13  8:15   ` Paolo Bonzini
2019-03-12 23:00 ` [PATCH v5 12/18] x86/split_lock: Enable #AC for split lock by default Fenghua Yu
2019-03-12 23:43   ` Dave Hansen
2019-03-12 23:00 ` [PATCH v5 13/18] x86/split_lock: Add a sysfs interface to allow user to enable or disable split lock detection on all CPUs during run time Fenghua Yu
2019-03-12 23:48   ` Dave Hansen
2019-03-13  0:53     ` Fenghua Yu
2019-03-13  1:08       ` Dave Hansen
2019-03-12 23:00 ` [PATCH v5 14/18] x86/clearcpuid: Support multiple clearcpuid options Fenghua Yu
2019-03-12 23:00 ` [PATCH v5 15/18] x86/clearcpuid: Support feature flag string in kernel option clearcpuid Fenghua Yu
2019-03-12 23:00 ` [PATCH v5 16/18] x86/clearcpuid: Apply cleared feature bits that are forced set before Fenghua Yu
2019-03-12 23:00 ` [PATCH v5 17/18] x86/clearcpuid: Clear CPUID bit in CPUID faulting Fenghua Yu
2019-03-12 23:00 ` [PATCH v5 18/18] Change document for kernel option clearcpuid Fenghua Yu

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