* [PATCH v2 1/3] dt-bindings: arm: coresight: Support non-configurable funnel
2019-03-20 12:38 [PATCH v2 0/3] Support static funnel and CoreSight DT on Hikey960 Wanglai Shi
@ 2019-03-20 12:38 ` Wanglai Shi
2019-03-20 17:28 ` Mathieu Poirier
2019-03-20 12:38 ` [PATCH v2 2/3] coresight: funnel: Support static funnel Wanglai Shi
2019-03-20 12:38 ` [PATCH v2 3/3] arm64: dts: hi3660: Add CoreSight support Wanglai Shi
2 siblings, 1 reply; 8+ messages in thread
From: Wanglai Shi @ 2019-03-20 12:38 UTC (permalink / raw)
To: mathieu.poirier, suzuki.poulose, robh+dt, mark.rutland, xuwei5,
alexander.shishkin
Cc: linux-arm-kernel, devicetree, linux-kernel, leo.yan, suzhuangluan
From: Leo Yan <leo.yan@linaro.org>
Document DT binding for non-configurable funnel and give an example
for it.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
---
.../devicetree/bindings/arm/coresight.txt | 45 +++++++++++++++++--
1 file changed, 42 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
index f8aff65ab921..e63ec3362af8 100644
--- a/Documentation/devicetree/bindings/arm/coresight.txt
+++ b/Documentation/devicetree/bindings/arm/coresight.txt
@@ -8,7 +8,8 @@ through the intermediate links connecting the source to the currently selected
sink. Each CoreSight component device should use these properties to describe
its hardware characteristcs.
-* Required properties for all components *except* non-configurable replicators:
+* Required properties for all components *except* non-configurable replicators
+ and non-configurable funnels:
* compatible: These have to be supplemented with "arm,primecell" as
drivers are using the AMBA bus interface. Possible values include:
@@ -24,7 +25,7 @@ its hardware characteristcs.
discovered at boot time when the device is probed.
"arm,coresight-tmc", "arm,primecell";
- - Trace Funnel:
+ - Trace Programmable Funnel:
"arm,coresight-funnel", "arm,primecell";
- Embedded Trace Macrocell (version 3.x) and
@@ -65,11 +66,12 @@ its hardware characteristcs.
"stm-stimulus-base", each corresponding to the areas defined in "reg".
* Required properties for devices that don't show up on the AMBA bus, such as
- non-configurable replicators:
+ non-configurable replicators and non-configurable funnels:
* compatible: Currently supported value is (note the absence of the
AMBA markee):
- "arm,coresight-replicator"
+ - "arm,coresight-funnel"
* port or ports: see "Graph bindings for Coresight" below.
@@ -200,6 +202,43 @@ Example:
};
};
+ funnel {
+ /*
+ * non-configurable funnel don't show up on the AMBA
+ * bus. As such no need to add "arm,primecell".
+ */
+ compatible = "arm,coresight-funnel";
+ clocks = <&crg_ctrl HI3660_PCLK>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ combo_funnel_out: endpoint {
+ remote-endpoint = <&top_funnel_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ combo_funnel_in0: endpoint {
+ remote-endpoint = <&cluster0_etf_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ combo_funnel_in1: endpoint {
+ remote-endpoint = <&cluster1_etf_out>;
+ };
+ };
+ };
+ };
+
funnel@20040000 {
compatible = "arm,coresight-funnel", "arm,primecell";
reg = <0 0x20040000 0 0x1000>;
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v2 1/3] dt-bindings: arm: coresight: Support non-configurable funnel
2019-03-20 12:38 ` [PATCH v2 1/3] dt-bindings: arm: coresight: Support non-configurable funnel Wanglai Shi
@ 2019-03-20 17:28 ` Mathieu Poirier
0 siblings, 0 replies; 8+ messages in thread
From: Mathieu Poirier @ 2019-03-20 17:28 UTC (permalink / raw)
To: Wanglai Shi
Cc: Suzuki K. Poulose, Rob Herring, Mark Rutland, xuwei,
Alexander Shishkin, linux-arm-kernel, devicetree,
Linux Kernel Mailing List, Leo Yan, Suzhuangluan
Hi Wanglai,
On Wed, 20 Mar 2019 at 06:53, Wanglai Shi <shiwanglai@hisilicon.com> wrote:
>
> From: Leo Yan <leo.yan@linaro.org>
>
> Document DT binding for non-configurable funnel and give an example
> for it.
>
> Signed-off-by: Leo Yan <leo.yan@linaro.org>
This patch needs to be sent on its own.
> ---
> .../devicetree/bindings/arm/coresight.txt | 45 +++++++++++++++++--
> 1 file changed, 42 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
> index f8aff65ab921..e63ec3362af8 100644
> --- a/Documentation/devicetree/bindings/arm/coresight.txt
> +++ b/Documentation/devicetree/bindings/arm/coresight.txt
> @@ -8,7 +8,8 @@ through the intermediate links connecting the source to the currently selected
> sink. Each CoreSight component device should use these properties to describe
> its hardware characteristcs.
>
> -* Required properties for all components *except* non-configurable replicators:
> +* Required properties for all components *except* non-configurable replicators
> + and non-configurable funnels:
>
> * compatible: These have to be supplemented with "arm,primecell" as
> drivers are using the AMBA bus interface. Possible values include:
> @@ -24,7 +25,7 @@ its hardware characteristcs.
> discovered at boot time when the device is probed.
> "arm,coresight-tmc", "arm,primecell";
>
> - - Trace Funnel:
> + - Trace Programmable Funnel:
> "arm,coresight-funnel", "arm,primecell";
>
> - Embedded Trace Macrocell (version 3.x) and
> @@ -65,11 +66,12 @@ its hardware characteristcs.
> "stm-stimulus-base", each corresponding to the areas defined in "reg".
>
> * Required properties for devices that don't show up on the AMBA bus, such as
> - non-configurable replicators:
> + non-configurable replicators and non-configurable funnels:
>
> * compatible: Currently supported value is (note the absence of the
> AMBA markee):
> - "arm,coresight-replicator"
> + - "arm,coresight-funnel"
>
> * port or ports: see "Graph bindings for Coresight" below.
>
> @@ -200,6 +202,43 @@ Example:
> };
> };
>
> + funnel {
> + /*
> + * non-configurable funnel don't show up on the AMBA
> + * bus. As such no need to add "arm,primecell".
> + */
> + compatible = "arm,coresight-funnel";
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + combo_funnel_out: endpoint {
> + remote-endpoint = <&top_funnel_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + combo_funnel_in0: endpoint {
> + remote-endpoint = <&cluster0_etf_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + combo_funnel_in1: endpoint {
> + remote-endpoint = <&cluster1_etf_out>;
> + };
> + };
> + };
> + };
> +
> funnel@20040000 {
> compatible = "arm,coresight-funnel", "arm,primecell";
> reg = <0 0x20040000 0 0x1000>;
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 2/3] coresight: funnel: Support static funnel
2019-03-20 12:38 [PATCH v2 0/3] Support static funnel and CoreSight DT on Hikey960 Wanglai Shi
2019-03-20 12:38 ` [PATCH v2 1/3] dt-bindings: arm: coresight: Support non-configurable funnel Wanglai Shi
@ 2019-03-20 12:38 ` Wanglai Shi
2019-03-20 13:52 ` Suzuki K Poulose
2019-03-20 12:38 ` [PATCH v2 3/3] arm64: dts: hi3660: Add CoreSight support Wanglai Shi
2 siblings, 1 reply; 8+ messages in thread
From: Wanglai Shi @ 2019-03-20 12:38 UTC (permalink / raw)
To: mathieu.poirier, suzuki.poulose, robh+dt, mark.rutland, xuwei5,
alexander.shishkin
Cc: linux-arm-kernel, devicetree, linux-kernel, leo.yan, suzhuangluan
From: Leo Yan <leo.yan@linaro.org>
Since CoreSight hardware topology can use a 'hidden' funnel in the
trace data path, this kind funnel doesn't have register for accessing
and is used by default from hardware design perspective. Below is an
example for related hardware topology:
+------+ +------+
| cpu0 |->| ETM |-\
+------+ +------+ \-> +--------+ +-----+
...... | Funnel |->| ETF |-\ Hidden funnel
+------+ +------+ /-> +--------+ +-----+ \ |
| cpu3 |->| ETM |-/ \ V
+------+ +------+ \-> +--------+
| Funnel |-> ...
+------+ +------+ /-> +--------+
| cpu4 |->| ETM |-\ /
+------+ +------+ \-> +--------+ +-----+ /
...... | Funnel |->| ETF |-/
+------+ +------+ /-> +--------+ +-----+
| cpu7 |->| ETM |-/
+------+ +------+
The CoreSight funnel driver only supports dynamic funnel with
registration register resource, thus it cannot support for the static
funnel case and it's impossible to create trace data path for this case.
This patch is to extend CoreSight funnel driver to support both for
static funnel and dynamic funnel. For the dynamic funnel it reuses the
code existed in the driver, for static funnel the driver will support
device probe if without providing register resource and the driver skips
registers accessing when detect the register base is NULL.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
---
.../hwtracing/coresight/coresight-funnel.c | 112 +++++++++++++-----
1 file changed, 85 insertions(+), 27 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c
index 927925151509..c6ba864ae488 100644
--- a/drivers/hwtracing/coresight/coresight-funnel.c
+++ b/drivers/hwtracing/coresight/coresight-funnel.c
@@ -12,6 +12,7 @@
#include <linux/err.h>
#include <linux/fs.h>
#include <linux/slab.h>
+#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/coresight.h>
#include <linux/amba/bus.h>
@@ -43,7 +44,7 @@ struct funnel_drvdata {
unsigned long priority;
};
-static int funnel_enable_hw(struct funnel_drvdata *drvdata, int port)
+static int dynamic_funnel_enable_hw(struct funnel_drvdata *drvdata, int port)
{
u32 functl;
int rc = 0;
@@ -71,17 +72,19 @@ static int funnel_enable_hw(struct funnel_drvdata *drvdata, int port)
static int funnel_enable(struct coresight_device *csdev, int inport,
int outport)
{
- int rc;
+ int rc = 0;
struct funnel_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
- rc = funnel_enable_hw(drvdata, inport);
+ if (drvdata->base)
+ rc = dynamic_funnel_enable_hw(drvdata, inport);
if (!rc)
dev_dbg(drvdata->dev, "FUNNEL inport %d enabled\n", inport);
return rc;
}
-static void funnel_disable_hw(struct funnel_drvdata *drvdata, int inport)
+static void dynamic_funnel_disable_hw(struct funnel_drvdata *drvdata,
+ int inport)
{
u32 functl;
@@ -103,7 +106,8 @@ static void funnel_disable(struct coresight_device *csdev, int inport,
{
struct funnel_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
- funnel_disable_hw(drvdata, inport);
+ if (drvdata->base)
+ dynamic_funnel_disable_hw(drvdata, inport);
dev_dbg(drvdata->dev, "FUNNEL inport %d disabled\n", inport);
}
@@ -177,54 +181,67 @@ static struct attribute *coresight_funnel_attrs[] = {
};
ATTRIBUTE_GROUPS(coresight_funnel);
-static int funnel_probe(struct amba_device *adev, const struct amba_id *id)
+static int funnel_probe(struct device *dev, struct resource *res)
{
int ret;
void __iomem *base;
- struct device *dev = &adev->dev;
struct coresight_platform_data *pdata = NULL;
struct funnel_drvdata *drvdata;
- struct resource *res = &adev->res;
struct coresight_desc desc = { 0 };
- struct device_node *np = adev->dev.of_node;
+ struct device_node *np = dev->of_node;
if (np) {
pdata = of_get_coresight_platform_data(dev, np);
if (IS_ERR(pdata))
return PTR_ERR(pdata);
- adev->dev.platform_data = pdata;
+ dev->platform_data = pdata;
}
drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
if (!drvdata)
return -ENOMEM;
- drvdata->dev = &adev->dev;
- drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
+ drvdata->dev = dev;
+ drvdata->atclk = devm_clk_get(dev, "atclk"); /* optional */
if (!IS_ERR(drvdata->atclk)) {
ret = clk_prepare_enable(drvdata->atclk);
if (ret)
return ret;
}
- dev_set_drvdata(dev, drvdata);
- /* Validity for the resource is already checked by the AMBA core */
- base = devm_ioremap_resource(dev, res);
- if (IS_ERR(base))
- return PTR_ERR(base);
+ /*
+ * Map the device base for dynamic-funnel, which has been
+ * validated by AMBA core.
+ */
+ if (res) {
+ base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(base)) {
+ ret = PTR_ERR(base);
+ goto out_disable_clk;
+ }
+ drvdata->base = base;
+ desc.groups = coresight_funnel_groups;
+ }
- drvdata->base = base;
- pm_runtime_put(&adev->dev);
+ dev_set_drvdata(dev, drvdata);
desc.type = CORESIGHT_DEV_TYPE_LINK;
desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_MERG;
desc.ops = &funnel_cs_ops;
desc.pdata = pdata;
desc.dev = dev;
- desc.groups = coresight_funnel_groups;
drvdata->csdev = coresight_register(&desc);
+ if (IS_ERR(drvdata->csdev)) {
+ ret = PTR_ERR(drvdata->csdev);
+ goto out_disable_clk;
+ }
+
+ pm_runtime_put(dev);
- return PTR_ERR_OR_ZERO(drvdata->csdev);
+out_disable_clk:
+ if (ret && !IS_ERR_OR_NULL(drvdata->atclk))
+ clk_disable_unprepare(drvdata->atclk);
+ return ret;
}
#ifdef CONFIG_PM
@@ -253,7 +270,48 @@ static const struct dev_pm_ops funnel_dev_pm_ops = {
SET_RUNTIME_PM_OPS(funnel_runtime_suspend, funnel_runtime_resume, NULL)
};
-static const struct amba_id funnel_ids[] = {
+static int static_funnel_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ pm_runtime_get_noresume(&pdev->dev);
+ pm_runtime_set_active(&pdev->dev);
+ pm_runtime_enable(&pdev->dev);
+
+ /* Static funnel do not have programming base */
+ ret = funnel_probe(&pdev->dev, NULL);
+
+ if (ret) {
+ pm_runtime_put_noidle(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
+ }
+
+ return ret;
+}
+
+static const struct of_device_id static_funnel_match[] = {
+ {.compatible = "arm,coresight-funnel"},
+ {}
+};
+
+static struct platform_driver static_funnel_driver = {
+ .probe = static_funnel_probe,
+ .driver = {
+ .name = "coresight-static-funnel",
+ .of_match_table = static_funnel_match,
+ .pm = &funnel_dev_pm_ops,
+ .suppress_bind_attrs = true,
+ },
+};
+builtin_platform_driver(static_funnel_driver);
+
+static int dynamic_funnel_probe(struct amba_device *adev,
+ const struct amba_id *id)
+{
+ return funnel_probe(&adev->dev, &adev->res);
+}
+
+static const struct amba_id dynamic_funnel_ids[] = {
{
.id = 0x000bb908,
.mask = 0x000fffff,
@@ -266,14 +324,14 @@ static const struct amba_id funnel_ids[] = {
{ 0, 0},
};
-static struct amba_driver funnel_driver = {
+static struct amba_driver dynamic_funnel_driver = {
.drv = {
- .name = "coresight-funnel",
+ .name = "coresight-dynamic-funnel",
.owner = THIS_MODULE,
.pm = &funnel_dev_pm_ops,
.suppress_bind_attrs = true,
},
- .probe = funnel_probe,
- .id_table = funnel_ids,
+ .probe = dynamic_funnel_probe,
+ .id_table = dynamic_funnel_ids,
};
-builtin_amba_driver(funnel_driver);
+builtin_amba_driver(dynamic_funnel_driver);
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v2 2/3] coresight: funnel: Support static funnel
2019-03-20 12:38 ` [PATCH v2 2/3] coresight: funnel: Support static funnel Wanglai Shi
@ 2019-03-20 13:52 ` Suzuki K Poulose
2019-03-21 2:09 ` Leo Yan
0 siblings, 1 reply; 8+ messages in thread
From: Suzuki K Poulose @ 2019-03-20 13:52 UTC (permalink / raw)
To: shiwanglai, mathieu.poirier, robh+dt, mark.rutland, xuwei5,
alexander.shishkin
Cc: linux-arm-kernel, devicetree, linux-kernel, leo.yan, suzhuangluan
On 20/03/2019 12:38, Wanglai Shi wrote:
> From: Leo Yan <leo.yan@linaro.org>
>
> Since CoreSight hardware topology can use a 'hidden' funnel in the
> trace data path, this kind funnel doesn't have register for accessing
> and is used by default from hardware design perspective. Below is an
> example for related hardware topology:
>
> +------+ +------+
> | cpu0 |->| ETM |-\
> +------+ +------+ \-> +--------+ +-----+
> ...... | Funnel |->| ETF |-\ Hidden funnel
> +------+ +------+ /-> +--------+ +-----+ \ |
> | cpu3 |->| ETM |-/ \ V
> +------+ +------+ \-> +--------+
> | Funnel |-> ...
> +------+ +------+ /-> +--------+
> | cpu4 |->| ETM |-\ /
> +------+ +------+ \-> +--------+ +-----+ /
> ...... | Funnel |->| ETF |-/
> +------+ +------+ /-> +--------+ +-----+
> | cpu7 |->| ETM |-/
> +------+ +------+
>
> The CoreSight funnel driver only supports dynamic funnel with
> registration register resource, thus it cannot support for the static
> funnel case and it's impossible to create trace data path for this case.
>
> This patch is to extend CoreSight funnel driver to support both for
> static funnel and dynamic funnel. For the dynamic funnel it reuses the
> code existed in the driver, for static funnel the driver will support
> device probe if without providing register resource and the driver skips
> registers accessing when detect the register base is NULL.
>
> Signed-off-by: Leo Yan <leo.yan@linaro.org>
> ---
Suggested-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> -static const struct amba_id funnel_ids[] = {
> +static int static_funnel_probe(struct platform_device *pdev)
> +{
> + int ret;
> +
> + pm_runtime_get_noresume(&pdev->dev);
> + pm_runtime_set_active(&pdev->dev);
> + pm_runtime_enable(&pdev->dev);
> +
> + /* Static funnel do not have programming base */
> + ret = funnel_probe(&pdev->dev, NULL);
> +
> + if (ret) {
> + pm_runtime_put_noidle(&pdev->dev);
> + pm_runtime_disable(&pdev->dev);
> + }
> +
> + return ret;
> +}
> +
> +static const struct of_device_id static_funnel_match[] = {
> + {.compatible = "arm,coresight-funnel"},
There is a potential issue with re-using the "compatible" string
already reserved for the normal programmable funnel. We may handle
a programmable funnel as non-programmable one, which is not good.
Do we need to use "arm,coresight-static-funnel" ?
Otherwise, looks good to me.
Suzuki
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v2 2/3] coresight: funnel: Support static funnel
2019-03-20 13:52 ` Suzuki K Poulose
@ 2019-03-21 2:09 ` Leo Yan
0 siblings, 0 replies; 8+ messages in thread
From: Leo Yan @ 2019-03-21 2:09 UTC (permalink / raw)
To: Suzuki K Poulose
Cc: shiwanglai, mathieu.poirier, robh+dt, mark.rutland, xuwei5,
alexander.shishkin, linux-arm-kernel, devicetree, linux-kernel,
suzhuangluan
Hi Suzuki,
On Wed, Mar 20, 2019 at 01:52:58PM +0000, Suzuki K Poulose wrote:
>
>
> On 20/03/2019 12:38, Wanglai Shi wrote:
> > From: Leo Yan <leo.yan@linaro.org>
> >
> > Since CoreSight hardware topology can use a 'hidden' funnel in the
> > trace data path, this kind funnel doesn't have register for accessing
> > and is used by default from hardware design perspective. Below is an
> > example for related hardware topology:
> >
> > +------+ +------+
> > | cpu0 |->| ETM |-\
> > +------+ +------+ \-> +--------+ +-----+
> > ...... | Funnel |->| ETF |-\ Hidden funnel
> > +------+ +------+ /-> +--------+ +-----+ \ |
> > | cpu3 |->| ETM |-/ \ V
> > +------+ +------+ \-> +--------+
> > | Funnel |-> ...
> > +------+ +------+ /-> +--------+
> > | cpu4 |->| ETM |-\ /
> > +------+ +------+ \-> +--------+ +-----+ /
> > ...... | Funnel |->| ETF |-/
> > +------+ +------+ /-> +--------+ +-----+
> > | cpu7 |->| ETM |-/
> > +------+ +------+
> >
> > The CoreSight funnel driver only supports dynamic funnel with
> > registration register resource, thus it cannot support for the static
> > funnel case and it's impossible to create trace data path for this case.
> >
> > This patch is to extend CoreSight funnel driver to support both for
> > static funnel and dynamic funnel. For the dynamic funnel it reuses the
> > code existed in the driver, for static funnel the driver will support
> > device probe if without providing register resource and the driver skips
> > registers accessing when detect the register base is NULL.
> >
> > Signed-off-by: Leo Yan <leo.yan@linaro.org>
> > ---
>
> Suggested-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Will add the tag in next version, and very appreciate you shared me
offline the replicator code for reference!
> > -static const struct amba_id funnel_ids[] = {
> > +static int static_funnel_probe(struct platform_device *pdev)
> > +{
> > + int ret;
> > +
> > + pm_runtime_get_noresume(&pdev->dev);
> > + pm_runtime_set_active(&pdev->dev);
> > + pm_runtime_enable(&pdev->dev);
> > +
> > + /* Static funnel do not have programming base */
> > + ret = funnel_probe(&pdev->dev, NULL);
> > +
> > + if (ret) {
> > + pm_runtime_put_noidle(&pdev->dev);
> > + pm_runtime_disable(&pdev->dev);
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +static const struct of_device_id static_funnel_match[] = {
> > + {.compatible = "arm,coresight-funnel"},
>
> There is a potential issue with re-using the "compatible" string
> already reserved for the normal programmable funnel. We may handle
> a programmable funnel as non-programmable one, which is not good.
>
> Do we need to use "arm,coresight-static-funnel" ?
This suggestion makes sense, will do this.
> Otherwise, looks good to me.
Thanks for reviewing.
Thanks,
Leo Yan
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 3/3] arm64: dts: hi3660: Add CoreSight support
2019-03-20 12:38 [PATCH v2 0/3] Support static funnel and CoreSight DT on Hikey960 Wanglai Shi
2019-03-20 12:38 ` [PATCH v2 1/3] dt-bindings: arm: coresight: Support non-configurable funnel Wanglai Shi
2019-03-20 12:38 ` [PATCH v2 2/3] coresight: funnel: Support static funnel Wanglai Shi
@ 2019-03-20 12:38 ` Wanglai Shi
2019-03-20 17:35 ` Mathieu Poirier
2 siblings, 1 reply; 8+ messages in thread
From: Wanglai Shi @ 2019-03-20 12:38 UTC (permalink / raw)
To: mathieu.poirier, suzuki.poulose, robh+dt, mark.rutland, xuwei5,
alexander.shishkin
Cc: linux-arm-kernel, devicetree, linux-kernel, leo.yan,
suzhuangluan, Wanglai Shi
This patch adds DT bindings for the CoreSight trace components
on hi3660, which is used by 96boards Hikey960.
Signed-off-by: Wanglai Shi <shiwanglai@hisilicon.com>
---
.../boot/dts/hisilicon/hi3660-coresight.dtsi | 456 ++++++++++++++++++
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 2 +
2 files changed, 458 insertions(+)
create mode 100644 arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi
new file mode 100644
index 000000000000..b6271fb407b7
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi
@@ -0,0 +1,456 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * dtsi for Hisilicon Hi3660 Coresight
+ *
+ * Copyright (C) 2016-2018 Hisilicon Ltd.
+ *
+ * Author: Wanglai Shi <shiwanglai@hisilicon.com>
+ *
+ */
+/ {
+ soc {
+ /* A53 cluster internals */
+ etm@ecc40000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0xecc40000 0 0x1000>;
+ clocks = <&crg_ctrl HI3660_PCLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu0>;
+
+ out-ports {
+ port {
+ etm0_out: endpoint {
+ remote-endpoint =
+ <&cluster0_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ etm@ecd40000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0xecd40000 0 0x1000>;
+ clocks = <&crg_ctrl HI3660_PCLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu1>;
+
+ out-ports {
+ port {
+ etm1_out: endpoint {
+ remote-endpoint =
+ <&cluster0_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ etm@ece40000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0xece40000 0 0x1000>;
+ clocks = <&crg_ctrl HI3660_PCLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu2>;
+
+ out-ports {
+ port {
+ etm2_out: endpoint {
+ remote-endpoint =
+ <&cluster0_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ etm@ecf40000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0xecf40000 0 0x1000>;
+ clocks = <&crg_ctrl HI3660_PCLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu3>;
+
+ out-ports {
+ port {
+ etm3_out: endpoint {
+ remote-endpoint =
+ <&cluster0_funnel_in3>;
+ };
+ };
+ };
+ };
+
+ funnel@ec801000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0 0xec801000 0 0x1000>;
+ clocks = <&crg_ctrl HI3660_PCLK>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ cluster0_funnel_out: endpoint {
+ remote-endpoint =
+ <&cluster0_etf_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ cluster0_funnel_in0: endpoint {
+ remote-endpoint = <&etm0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ cluster0_funnel_in1: endpoint {
+ remote-endpoint = <&etm1_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ cluster0_funnel_in2: endpoint {
+ remote-endpoint = <&etm2_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ cluster0_funnel_in3: endpoint {
+ remote-endpoint = <&etm3_out>;
+ };
+ };
+ };
+ };
+
+ etf@ec802000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0xec802000 0 0x1000>;
+ clocks = <&crg_ctrl HI3660_PCLK>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ cluster0_etf_in: endpoint {
+ remote-endpoint =
+ <&cluster0_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ cluster0_etf_out: endpoint {
+ remote-endpoint =
+ <&combo_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ /* A73 cluster internals */
+ etm@ed440000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0xed440000 0 0x1000>;
+ clocks = <&crg_ctrl HI3660_PCLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu4>;
+
+ out-ports {
+ port {
+ etm4_out: endpoint {
+ remote-endpoint =
+ <&cluster1_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ etm@ed540000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0xed540000 0 0x1000>;
+ clocks = <&crg_ctrl HI3660_PCLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu5>;
+
+ out-ports {
+ port {
+ etm5_out: endpoint {
+ remote-endpoint =
+ <&cluster1_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ etm@ed640000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0xed640000 0 0x1000>;
+ clocks = <&crg_ctrl HI3660_PCLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu6>;
+
+ out-ports {
+ port {
+ etm6_out: endpoint {
+ remote-endpoint =
+ <&cluster1_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ etm@ed740000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0xed740000 0 0x1000>;
+ clocks = <&crg_ctrl HI3660_PCLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu7>;
+
+ out-ports {
+ port {
+ etm7_out: endpoint {
+ remote-endpoint =
+ <&cluster1_funnel_in3>;
+ };
+ };
+ };
+ };
+
+ funnel@ed001000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0 0xed001000 0 0x1000>;
+ clocks = <&crg_ctrl HI3660_PCLK>;
+ clock-names = "apb_pclk";
+ out-ports {
+ port {
+ cluster1_funnel_out: endpoint {
+ remote-endpoint =
+ <&cluster1_etf_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ cluster1_funnel_in0: endpoint {
+ remote-endpoint = <&etm4_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ cluster1_funnel_in1: endpoint {
+ remote-endpoint = <&etm5_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ cluster1_funnel_in2: endpoint {
+ remote-endpoint = <&etm6_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ cluster1_funnel_in3: endpoint {
+ remote-endpoint = <&etm7_out>;
+ };
+ };
+ };
+ };
+
+ etf@ed002000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0xed002000 0 0x1000>;
+ clocks = <&crg_ctrl HI3660_PCLK>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ cluster1_etf_in: endpoint {
+ remote-endpoint =
+ <&cluster1_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ cluster1_etf_out: endpoint {
+ remote-endpoint =
+ <&combo_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ /* An invisible combo funnel between clusters and top funnel */
+ funnel {
+ compatible = "arm,coresight-funnel";
+ clocks = <&crg_ctrl HI3660_PCLK>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ combo_funnel_out: endpoint {
+ remote-endpoint =
+ <&top_funnel_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ combo_funnel_in0: endpoint {
+ remote-endpoint =
+ <&cluster0_etf_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ combo_funnel_in1: endpoint {
+ remote-endpoint =
+ <&cluster1_etf_out>;
+ };
+ };
+ };
+ };
+
+ /* Top internals */
+ funnel@ec031000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0 0xec031000 0 0x1000>;
+ clocks = <&crg_ctrl HI3660_PCLK>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ top_funnel_out: endpoint {
+ remote-endpoint =
+ <&top_etf_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ top_funnel_in: endpoint {
+ remote-endpoint =
+ <&combo_funnel_out>;
+ };
+ };
+ };
+ };
+
+ etf@ec036000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0xec036000 0 0x1000>;
+ clocks = <&crg_ctrl HI3660_PCLK>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ top_etf_in: endpoint {
+ remote-endpoint =
+ <&top_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ top_etf_out: endpoint {
+ remote-endpoint =
+ <&replicator_in>;
+ };
+ };
+ };
+ };
+
+ replicator {
+ compatible = "arm,coresight-replicator";
+ clocks = <&crg_ctrl HI3660_PCLK>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ replicator_in: endpoint {
+ remote-endpoint =
+ <&top_etf_out>;
+ };
+ };
+ };
+
+ out-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ replicator0_out0: endpoint {
+ remote-endpoint = <&etr_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ replicator0_out1: endpoint {
+ remote-endpoint = <&tpiu_in>;
+ };
+ };
+ };
+ };
+
+ etr@ec033000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0xec033000 0 0x1000>;
+ clocks = <&crg_ctrl HI3660_PCLK>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ etr_in: endpoint {
+ remote-endpoint =
+ <&replicator0_out0>;
+ };
+ };
+ };
+ };
+
+ tpiu@ec032000 {
+ compatible = "arm,coresight-tpiu", "arm,primecell";
+ reg = <0 0xec032000 0 0x1000>;
+ clocks = <&crg_ctrl HI3660_PCLK>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ tpiu_in: endpoint {
+ remote-endpoint =
+ <&replicator0_out1>;
+ };
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 57ebefbd156f..36fdc9cd443d 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -1216,3 +1216,5 @@
};
};
};
+
+#include "hi3660-coresight.dtsi"
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v2 3/3] arm64: dts: hi3660: Add CoreSight support
2019-03-20 12:38 ` [PATCH v2 3/3] arm64: dts: hi3660: Add CoreSight support Wanglai Shi
@ 2019-03-20 17:35 ` Mathieu Poirier
0 siblings, 0 replies; 8+ messages in thread
From: Mathieu Poirier @ 2019-03-20 17:35 UTC (permalink / raw)
To: Wanglai Shi
Cc: Suzuki K. Poulose, Rob Herring, Mark Rutland, xuwei,
Alexander Shishkin, linux-arm-kernel, devicetree,
Linux Kernel Mailing List, Leo Yan, Suzhuangluan
On Wed, 20 Mar 2019 at 06:54, Wanglai Shi <shiwanglai@hisilicon.com> wrote:
>
> This patch adds DT bindings for the CoreSight trace components
> on hi3660, which is used by 96boards Hikey960.
>
> Signed-off-by: Wanglai Shi <shiwanglai@hisilicon.com>
This patch too needs to be on its own since it is maintained by Wei.
Thanks,
Mathieu
> ---
> .../boot/dts/hisilicon/hi3660-coresight.dtsi | 456 ++++++++++++++++++
> arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 2 +
> 2 files changed, 458 insertions(+)
> create mode 100644 arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi
>
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi
> new file mode 100644
> index 000000000000..b6271fb407b7
> --- /dev/null
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi
> @@ -0,0 +1,456 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +/*
> + * dtsi for Hisilicon Hi3660 Coresight
> + *
> + * Copyright (C) 2016-2018 Hisilicon Ltd.
> + *
> + * Author: Wanglai Shi <shiwanglai@hisilicon.com>
> + *
> + */
> +/ {
> + soc {
> + /* A53 cluster internals */
> + etm@ecc40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0xecc40000 0 0x1000>;
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> + cpu = <&cpu0>;
> +
> + out-ports {
> + port {
> + etm0_out: endpoint {
> + remote-endpoint =
> + <&cluster0_funnel_in0>;
> + };
> + };
> + };
> + };
> +
> + etm@ecd40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0xecd40000 0 0x1000>;
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> + cpu = <&cpu1>;
> +
> + out-ports {
> + port {
> + etm1_out: endpoint {
> + remote-endpoint =
> + <&cluster0_funnel_in1>;
> + };
> + };
> + };
> + };
> +
> + etm@ece40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0xece40000 0 0x1000>;
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> + cpu = <&cpu2>;
> +
> + out-ports {
> + port {
> + etm2_out: endpoint {
> + remote-endpoint =
> + <&cluster0_funnel_in2>;
> + };
> + };
> + };
> + };
> +
> + etm@ecf40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0xecf40000 0 0x1000>;
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> + cpu = <&cpu3>;
> +
> + out-ports {
> + port {
> + etm3_out: endpoint {
> + remote-endpoint =
> + <&cluster0_funnel_in3>;
> + };
> + };
> + };
> + };
> +
> + funnel@ec801000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0 0xec801000 0 0x1000>;
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + cluster0_funnel_out: endpoint {
> + remote-endpoint =
> + <&cluster0_etf_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + cluster0_funnel_in0: endpoint {
> + remote-endpoint = <&etm0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + cluster0_funnel_in1: endpoint {
> + remote-endpoint = <&etm1_out>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> + cluster0_funnel_in2: endpoint {
> + remote-endpoint = <&etm2_out>;
> + };
> + };
> +
> + port@3 {
> + reg = <3>;
> + cluster0_funnel_in3: endpoint {
> + remote-endpoint = <&etm3_out>;
> + };
> + };
> + };
> + };
> +
> + etf@ec802000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0 0xec802000 0 0x1000>;
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> +
> + in-ports {
> + port {
> + cluster0_etf_in: endpoint {
> + remote-endpoint =
> + <&cluster0_funnel_out>;
> + };
> + };
> + };
> +
> + out-ports {
> + port {
> + cluster0_etf_out: endpoint {
> + remote-endpoint =
> + <&combo_funnel_in0>;
> + };
> + };
> + };
> + };
> +
> + /* A73 cluster internals */
> + etm@ed440000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0xed440000 0 0x1000>;
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> + cpu = <&cpu4>;
> +
> + out-ports {
> + port {
> + etm4_out: endpoint {
> + remote-endpoint =
> + <&cluster1_funnel_in0>;
> + };
> + };
> + };
> + };
> +
> + etm@ed540000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0xed540000 0 0x1000>;
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> + cpu = <&cpu5>;
> +
> + out-ports {
> + port {
> + etm5_out: endpoint {
> + remote-endpoint =
> + <&cluster1_funnel_in1>;
> + };
> + };
> + };
> + };
> +
> + etm@ed640000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0xed640000 0 0x1000>;
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> + cpu = <&cpu6>;
> +
> + out-ports {
> + port {
> + etm6_out: endpoint {
> + remote-endpoint =
> + <&cluster1_funnel_in2>;
> + };
> + };
> + };
> + };
> +
> + etm@ed740000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0xed740000 0 0x1000>;
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> + cpu = <&cpu7>;
> +
> + out-ports {
> + port {
> + etm7_out: endpoint {
> + remote-endpoint =
> + <&cluster1_funnel_in3>;
> + };
> + };
> + };
> + };
> +
> + funnel@ed001000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0 0xed001000 0 0x1000>;
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> + out-ports {
> + port {
> + cluster1_funnel_out: endpoint {
> + remote-endpoint =
> + <&cluster1_etf_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + cluster1_funnel_in0: endpoint {
> + remote-endpoint = <&etm4_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + cluster1_funnel_in1: endpoint {
> + remote-endpoint = <&etm5_out>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> + cluster1_funnel_in2: endpoint {
> + remote-endpoint = <&etm6_out>;
> + };
> + };
> +
> + port@3 {
> + reg = <3>;
> + cluster1_funnel_in3: endpoint {
> + remote-endpoint = <&etm7_out>;
> + };
> + };
> + };
> + };
> +
> + etf@ed002000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0 0xed002000 0 0x1000>;
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> +
> + in-ports {
> + port {
> + cluster1_etf_in: endpoint {
> + remote-endpoint =
> + <&cluster1_funnel_out>;
> + };
> + };
> + };
> +
> + out-ports {
> + port {
> + cluster1_etf_out: endpoint {
> + remote-endpoint =
> + <&combo_funnel_in1>;
> + };
> + };
> + };
> + };
> +
> + /* An invisible combo funnel between clusters and top funnel */
> + funnel {
> + compatible = "arm,coresight-funnel";
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + combo_funnel_out: endpoint {
> + remote-endpoint =
> + <&top_funnel_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + combo_funnel_in0: endpoint {
> + remote-endpoint =
> + <&cluster0_etf_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + combo_funnel_in1: endpoint {
> + remote-endpoint =
> + <&cluster1_etf_out>;
> + };
> + };
> + };
> + };
> +
> + /* Top internals */
> + funnel@ec031000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0 0xec031000 0 0x1000>;
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + top_funnel_out: endpoint {
> + remote-endpoint =
> + <&top_etf_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + top_funnel_in: endpoint {
> + remote-endpoint =
> + <&combo_funnel_out>;
> + };
> + };
> + };
> + };
> +
> + etf@ec036000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0 0xec036000 0 0x1000>;
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> +
> + in-ports {
> + port {
> + top_etf_in: endpoint {
> + remote-endpoint =
> + <&top_funnel_out>;
> + };
> + };
> + };
> +
> + out-ports {
> + port {
> + top_etf_out: endpoint {
> + remote-endpoint =
> + <&replicator_in>;
> + };
> + };
> + };
> + };
> +
> + replicator {
> + compatible = "arm,coresight-replicator";
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> +
> + in-ports {
> + port {
> + replicator_in: endpoint {
> + remote-endpoint =
> + <&top_etf_out>;
> + };
> + };
> + };
> +
> + out-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + replicator0_out0: endpoint {
> + remote-endpoint = <&etr_in>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + replicator0_out1: endpoint {
> + remote-endpoint = <&tpiu_in>;
> + };
> + };
> + };
> + };
> +
> + etr@ec033000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0 0xec033000 0 0x1000>;
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> +
> + in-ports {
> + port {
> + etr_in: endpoint {
> + remote-endpoint =
> + <&replicator0_out0>;
> + };
> + };
> + };
> + };
> +
> + tpiu@ec032000 {
> + compatible = "arm,coresight-tpiu", "arm,primecell";
> + reg = <0 0xec032000 0 0x1000>;
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> +
> + in-ports {
> + port {
> + tpiu_in: endpoint {
> + remote-endpoint =
> + <&replicator0_out1>;
> + };
> + };
> + };
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> index 57ebefbd156f..36fdc9cd443d 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> @@ -1216,3 +1216,5 @@
> };
> };
> };
> +
> +#include "hi3660-coresight.dtsi"
> --
> 2.17.1
>
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