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From: Sowjanya Komatineni <skomatineni@nvidia.com>
To: <thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
	<talho@nvidia.com>, <skomatineni@nvidia.com>,
	<broonie@kernel.org>, <robh+dt@kernel.org>,
	<mark.rutland@arm.com>, <kyarlagadda@nvidia.com>
Cc: <ldewangan@nvidia.com>, <linux-tegra@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <linux-spi@vger.kernel.org>,
	<devicetree@vger.kernel.org>
Subject: [PATCH V2 03/20] spi: tegra114: de-assert CS before SPI mode change
Date: Thu, 4 Apr 2019 17:14:02 -0700	[thread overview]
Message-ID: <1554423259-26056-3-git-send-email-skomatineni@nvidia.com> (raw)
In-Reply-To: <1554423259-26056-1-git-send-email-skomatineni@nvidia.com>

With SW CS, during the transfer completion CS is de-asserted by writing
default command1 register value to SPI_COMMAND1 register. With this both
mode and CS state are set at the same time and if current transfer mode
is different to default SPI mode and if mode change happens prior to CS
de-assert, clock polarity can change while CS is active before transfer
finishes.

This causes Slave to see spurious clock edges resulting in data mismatch.

This patch fixes this by de-asserting CS before writing SPI_COMMAND1 to
its default value so through out the transfer it will be in same SPI mode.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 drivers/spi/spi-tegra114.c | 22 ++++++++++++++++------
 1 file changed, 16 insertions(+), 6 deletions(-)

diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index 3042521c3785..c60e40cab0a0 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -863,6 +863,19 @@ static void tegra_spi_transfer_delay(int delay)
 	udelay(delay % 1000);
 }
 
+static void tegra_spi_transfer_end(struct spi_device *spi)
+{
+	struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
+	int cs_val = (spi->mode & SPI_CS_HIGH) ? 0 : 1;
+
+	if (cs_val)
+		tspi->command1_reg |= SPI_CS_SW_VAL;
+	else
+		tspi->command1_reg &= ~SPI_CS_SW_VAL;
+	tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);
+	tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
+}
+
 static int tegra_spi_transfer_one_message(struct spi_master *master,
 			struct spi_message *msg)
 {
@@ -925,8 +938,7 @@ static int tegra_spi_transfer_one_message(struct spi_master *master,
 
 complete_xfer:
 		if (ret < 0 || skip) {
-			tegra_spi_writel(tspi, tspi->def_command1_reg,
-					SPI_COMMAND1);
+			tegra_spi_transfer_end(spi);
 			tegra_spi_transfer_delay(xfer->delay_usecs);
 			goto exit;
 		} else if (list_is_last(&xfer->transfer_list,
@@ -934,13 +946,11 @@ static int tegra_spi_transfer_one_message(struct spi_master *master,
 			if (xfer->cs_change)
 				tspi->cs_control = spi;
 			else {
-				tegra_spi_writel(tspi, tspi->def_command1_reg,
-						SPI_COMMAND1);
+				tegra_spi_transfer_end(spi);
 				tegra_spi_transfer_delay(xfer->delay_usecs);
 			}
 		} else if (xfer->cs_change) {
-			tegra_spi_writel(tspi, tspi->def_command1_reg,
-					SPI_COMMAND1);
+			tegra_spi_transfer_end(spi);
 			tegra_spi_transfer_delay(xfer->delay_usecs);
 		}
 
-- 
2.7.4


  parent reply	other threads:[~2019-04-05  0:16 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-05  0:14 [PATCH V2 01/20] spi: tegra114: fix PIO transfer Sowjanya Komatineni
2019-04-05  0:14 ` [PATCH V2 02/20] spi: tegra114: use unpacked mode for below 4 bytes Sowjanya Komatineni
2019-04-05  0:14 ` Sowjanya Komatineni [this message]
2019-04-05  3:27   ` Applied "spi: tegra114: de-assert CS before SPI mode change" to the spi tree Mark Brown
2019-04-05  0:14 ` [PATCH V2 04/20] spi: tegra114: avoid reset call in atomic context Sowjanya Komatineni
2019-04-05  3:26   ` Applied "spi: tegra114: avoid reset call in atomic context" to the spi tree Mark Brown
2019-04-05  0:14 ` [PATCH V2 05/20] spi: tegra114: dump SPI registers during timeout Sowjanya Komatineni
2019-04-05  3:26   ` Applied "spi: tegra114: dump SPI registers during timeout" to the spi tree Mark Brown
2019-04-05  0:14 ` [PATCH V2 06/20] spi: tegra114: set supported bits per word Sowjanya Komatineni
2019-04-05  3:26   ` Applied "spi: tegra114: set supported bits per word" to the spi tree Mark Brown
2019-04-05  0:14 ` [PATCH V2 07/20] spi: tegra114: set bus number based on id Sowjanya Komatineni
2019-04-05  0:14 ` [PATCH V2 08/20] spi: tegra114: add dual mode support Sowjanya Komatineni
2019-04-08  7:32   ` Applied "spi: tegra114: add dual mode support" to the spi tree Mark Brown
2019-04-05  0:14 ` [PATCH V2 09/20] spi: tegra114: add 3 wire transfer mode support Sowjanya Komatineni
2019-04-08  7:31   ` Applied "spi: tegra114: add 3 wire transfer mode support" to the spi tree Mark Brown
2019-04-05  0:14 ` [PATCH V2 10/20] Documentation: devicetree: spi: add spi-lsbyte-first propery Sowjanya Komatineni
2019-04-08  6:27   ` Mark Brown
2019-04-05  0:14 ` [PATCH V2 11/20] spi: expand mode support and add LSBYTE_FIRST mode Sowjanya Komatineni
2019-04-08  6:28   ` Mark Brown
2019-04-11 19:58     ` Sowjanya Komatineni
2019-04-12  8:32       ` Mark Brown
2019-04-05  0:14 ` [PATCH V2 12/20] spi: tegra114: add support for LSBYTE_FIRST Sowjanya Komatineni
2019-04-05  0:14 ` [PATCH V2 13/20] spi: tegra114: add support for interrupt mask Sowjanya Komatineni
2019-04-05  0:14 ` [PATCH V2 14/20] spi: tegra114: add support for gpio based cs Sowjanya Komatineni
2019-04-08  6:30   ` Mark Brown
2019-04-05  0:14 ` [PATCH V2 15/20] spi: tegra114: add support for hw " Sowjanya Komatineni
2019-04-05  0:14 ` [PATCH V2 16/20] spi-summary: document set_cs_timing Sowjanya Komatineni
2019-04-08  7:31   ` Applied "spi-summary: document set_cs_timing" to the spi tree Mark Brown
2019-04-05  0:14 ` [PATCH V2 17/20] spi: add a method for configuring CS timing Sowjanya Komatineni
2019-04-08  7:31   ` Applied "spi: add a method for configuring CS timing" to the spi tree Mark Brown
2019-04-05  0:14 ` [PATCH V2 18/20] spi: tegra114: add support for HW CS timing Sowjanya Komatineni
2019-04-05  0:14 ` [PATCH V2 19/20] DT bindings: spi: document tx/rx clock delay properties Sowjanya Komatineni
2019-04-08  7:22   ` Mark Brown
2019-04-08  7:31   ` Applied "spi: document tx/rx clock delay properties" to the spi tree Mark Brown
2019-04-05  0:14 ` [PATCH V2 20/20] spi: tegra114: add support for tuning TX and RX trimmers Sowjanya Komatineni

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