From: Lukasz Luba <l.luba@partner.samsung.com>
To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org
Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org,
cw00.choi@samsung.com, kyungmin.park@samsung.com,
m.szyprowski@samsung.com, s.nawrocki@samsung.com,
myungjoo.ham@samsung.com, keescook@chromium.org,
tony@atomide.com, jroedel@suse.de, treding@nvidia.com,
digetx@gmail.com, willy.mh.wolff.ml@gmail.com,
Lukasz Luba <l.luba@partner.samsung.com>
Subject: [PATCH v6 01/10] clk: samsung: add needed IDs for DMC clocks in Exynos5420
Date: Fri, 19 Apr 2019 16:19:19 +0200 [thread overview]
Message-ID: <1555683568-20882-2-git-send-email-l.luba@partner.samsung.com> (raw)
In-Reply-To: <1555683568-20882-1-git-send-email-l.luba@partner.samsung.com>
Define new IDs for clocks used by Dynamic Memory Controller in
Exynos5422 SoC.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
include/dt-bindings/clock/exynos5420.h | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 355f469..abb1842 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -60,6 +60,7 @@
#define CLK_MAU_EPLL 159
#define CLK_SCLK_HSIC_12M 160
#define CLK_SCLK_MPHY_IXTAL24 161
+#define CLK_SCLK_BPLL 162
/* gate clocks */
#define CLK_UART0 257
@@ -195,6 +196,18 @@
#define CLK_ACLK432_CAM 518
#define CLK_ACLK_FL1550_CAM 519
#define CLK_ACLK550_CAM 520
+#define CLK_CLKM_PHY0 521
+#define CLK_CLKM_PHY1 522
+#define CLK_ACLK_PPMU_DREX0_0 523
+#define CLK_ACLK_PPMU_DREX0_1 524
+#define CLK_ACLK_PPMU_DREX1_0 525
+#define CLK_ACLK_PPMU_DREX1_1 526
+#define CLK_PCLK_PPMU_DREX0_0 527
+#define CLK_PCLK_PPMU_DREX0_1 528
+#define CLK_PCLK_PPMU_DREX1_0 529
+#define CLK_PCLK_PPMU_DREX1_1 530
+#define CLK_CDREX_PAUSE 531
+#define CLK_CDREX_TIMING_SET 532
/* mux clocks */
#define CLK_MOUT_HDMI 640
@@ -217,6 +230,8 @@
#define CLK_MOUT_EPLL 657
#define CLK_MOUT_MAU_EPLL 658
#define CLK_MOUT_USER_MAU_EPLL 659
+#define CLK_MOUT_SCLK_SPLL 660
+#define CLK_MOUT_MX_MSPLL_CCORE_PHY 661
/* divider clocks */
#define CLK_DOUT_PIXEL 768
@@ -248,8 +263,9 @@
#define CLK_DOUT_CCLK_DREX0 794
#define CLK_DOUT_CLK2X_PHY0 795
#define CLK_DOUT_PCLK_CORE_MEM 796
+#define CLK_FF_DOUT_SPLL2 797
/* must be greater than maximal clock id */
-#define CLK_NR_CLKS 797
+#define CLK_NR_CLKS 798
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */
--
2.7.4
next prev parent reply other threads:[~2019-04-19 19:08 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20190419141938eucas1p16ee6cdf897184df33cf67b55c5f3c449@eucas1p1.samsung.com>
2019-04-19 14:19 ` [PATCH v6 0/10] Exynos5 Dynamic Memory Controller driver Lukasz Luba
[not found] ` <CGME20190419141940eucas1p295a1130863cf2e69476ca0ba11a8a102@eucas1p2.samsung.com>
2019-04-19 14:19 ` Lukasz Luba [this message]
2019-04-30 4:47 ` [PATCH v6 01/10] clk: samsung: add needed IDs for DMC clocks in Exynos5420 Chanwoo Choi
2019-04-30 12:36 ` Lukasz Luba
[not found] ` <CGME20190419141942eucas1p2eaa1d17d785a27632b214a2da011a9fb@eucas1p2.samsung.com>
2019-04-19 14:19 ` [PATCH v6 02/10] clk: samsung: add new clocks for DMC for Exynos5422 SoC Lukasz Luba
2019-04-30 1:31 ` Chanwoo Choi
2019-04-30 13:12 ` Lukasz Luba
[not found] ` <CGME20190419141943eucas1p220d77bacfc4fcba8ec6a10f540e1a27d@eucas1p2.samsung.com>
2019-04-19 14:19 ` [PATCH v6 03/10] clk: samsung: add BPLL rate table for Exynos 5422 SoC Lukasz Luba
2019-05-02 5:15 ` Chanwoo Choi
2019-05-02 14:23 ` Lukasz Luba
[not found] ` <CGME20190419141945eucas1p1c95d65f261f82da5c856c0f2fcf1ce87@eucas1p1.samsung.com>
2019-04-19 14:19 ` [PATCH v6 04/10] Documentation: dt: device tree bindings for LPDDR3 memories Lukasz Luba
2019-04-25 19:51 ` Rob Herring
2019-04-29 12:04 ` Lukasz Luba
2019-04-29 16:36 ` Rob Herring
2019-04-30 20:04 ` Lukasz Luba
2019-04-25 19:53 ` Rob Herring
2019-04-29 12:05 ` Lukasz Luba
[not found] ` <CGME20190419141946eucas1p2fffda29e18080fd3573f625f0cf2b7f8@eucas1p2.samsung.com>
2019-04-19 14:19 ` [PATCH v6 05/10] drivers: memory: extend of_memory by LPDDR3 support Lukasz Luba
[not found] ` <CGME20190419141947eucas1p13a27605e04169ab528ef5bfb385eddbc@eucas1p1.samsung.com>
2019-04-19 14:19 ` [PATCH v6 06/10] dt-bindings: memory-controllers: add Exynos5422 DMC device description Lukasz Luba
2019-04-25 19:57 ` Rob Herring
2019-04-29 12:14 ` Lukasz Luba
2019-04-29 16:43 ` Rob Herring
2019-04-30 20:15 ` Lukasz Luba
2019-04-30 4:46 ` Chanwoo Choi
2019-04-30 20:30 ` Lukasz Luba
2019-05-02 1:35 ` Chanwoo Choi
2019-05-02 18:56 ` Lukasz Luba
[not found] ` <CGME20190419141949eucas1p2a3ca13166210b6bc5741808055650e04@eucas1p2.samsung.com>
2019-04-19 14:19 ` [PATCH v6 07/10] drivers: memory: add DMC driver for Exynos5422 Lukasz Luba
2019-04-23 11:27 ` Krzysztof Kozlowski
2019-04-29 14:51 ` Lukasz Luba
[not found] ` <CGME20190419141950eucas1p2e810215d1ceaf75fc9e807bbaa78e003@eucas1p2.samsung.com>
2019-04-19 14:19 ` [PATCH v6 08/10] drivers: devfreq: events: add Exynos PPMU new events Lukasz Luba
[not found] ` <CGME20190419141952eucas1p11dc36f30c873a947122e0f7e8d55a3bb@eucas1p1.samsung.com>
2019-04-19 14:19 ` [PATCH v6 09/10] ARM: dts: exynos: add DMC device for exynos5422 Lukasz Luba
2019-04-23 11:03 ` Krzysztof Kozlowski
2019-04-29 12:38 ` Lukasz Luba
[not found] ` <CGME20190419141953eucas1p1b403be15353fa31de3e226599b675f67@eucas1p1.samsung.com>
2019-04-19 14:19 ` [PATCH v6 10/10] ARM: exynos_defconfig: enable DMC driver Lukasz Luba
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