From: Lukasz Luba <l.luba@partner.samsung.com>
To: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org,
b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org,
cw00.choi@samsung.com, kyungmin.park@samsung.com,
m.szyprowski@samsung.com, s.nawrocki@samsung.com,
myungjoo.ham@samsung.com, keescook@chromium.org,
tony@atomide.com, jroedel@suse.de, treding@nvidia.com,
digetx@gmail.com, willy.mh.wolff.ml@gmail.com
Subject: Re: [PATCH v6 06/10] dt-bindings: memory-controllers: add Exynos5422 DMC device description
Date: Mon, 29 Apr 2019 14:14:33 +0200 [thread overview]
Message-ID: <e4613d6e-0893-8163-32ef-8137c40d2b24@partner.samsung.com> (raw)
In-Reply-To: <20190425195750.GA26031@bogus>
Hi Rob,
On 4/25/19 9:57 PM, Rob Herring wrote:
> On Fri, Apr 19, 2019 at 04:19:24PM +0200, Lukasz Luba wrote:
>> The patch adds description for DT binding for a new Exynos5422 Dynamic
>> Memory Controller device.
>>
>> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
>> ---
>> .../bindings/memory-controllers/exynos5422-dmc.txt | 73 ++++++++++++++++++++++
>> 1 file changed, 73 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
>>
>> diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
>> new file mode 100644
>> index 0000000..133b3cc
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
>> @@ -0,0 +1,73 @@
>> +* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device
>> +
>> +The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM
>> +memory chips are connected. The driver is to monitor the controller in runtime
>> +and switch frequency and voltage. To monitor the usage of the controller in
>> +runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which
>> +is able to measure the current load of the memory.
>> +When 'userspace' governor is used for the driver, an application is able to
>> +switch the DMC and memory frequency.
>> +
>> +Required properties for DMC device for Exynos5422:
>> +- compatible: Should be "samsung,exynos5422-bus".
>> +- clock-names : the name of clock used by the bus, "bus".
>> +- clocks : phandles for clock specified in "clock-names" property.
>> +- devfreq-events : phandles for PPMU devices connected to this DMC.
>> +- vdd-supply : phandle for voltage regulator which is connected.
>> +- reg : registers of two CDREX controllers, chip information, clocks subsystem.
>> +- operating-points-v2 : phandle for OPPs described in v2 definition.
>> +- device-handle : phandle of the connected DRAM memory device. For more
>> + information please refer to Documentation
>
> The memory node(s) should be a child of the memory controller IMO.
I have followed the TI code for LPDDR2. They use 'device-handle'
probably because the memory controller can be moved into the common
.dtsi and taken by reference in .dts in a proper board file.
The board .dts files might specify different DRAM chips and timings.
In Exynos case we will also have such situation: one memory controller
and a few different DRAM chips.
>
>> +- devfreq-events : phandles of the PPMU events used by the controller.
>> +
>> +Example:
>> +
>> + ppmu_dmc0_0: ppmu@10d00000 {
>> + compatible = "samsung,exynos-ppmu";
>> + reg = <0x10d00000 0x2000>;
>> + clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
>> + clock-names = "ppmu";
>> + status = "okay";
>
> Don't show 'status' in examples.
Thank you, I accidentally copied it from dt file.
Regards,
Lukasz
>
>> + events {
>> + ppmu_event_dmc0_0: ppmu-event3-dmc0_0 {
>> + event-name = "ppmu-event3-dmc0_0";
>> + };
>> + };
>> + };
>> +
>> + dmc: memory-controller@10c20000 {
>> + compatible = "samsung,exynos5422-dmc";
>> + reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>,
>> + <0x10000000 0x1000>, <0x10030000 0x1000>;
>> + clocks = <&clock CLK_FOUT_SPLL>,
>> + <&clock CLK_MOUT_SCLK_SPLL>,
>> + <&clock CLK_FF_DOUT_SPLL2>,
>> + <&clock CLK_FOUT_BPLL>,
>> + <&clock CLK_MOUT_BPLL>,
>> + <&clock CLK_SCLK_BPLL>,
>> + <&clock CLK_MOUT_MX_MSPLL_CCORE>,
>> + <&clock CLK_MOUT_MX_MSPLL_CCORE_PHY>,
>> + <&clock CLK_MOUT_MCLK_CDREX>,
>> + <&clock CLK_DOUT_CLK2X_PHY0>,
>> + <&clock CLK_CLKM_PHY0>,
>> + <&clock CLK_CLKM_PHY1>;
>> + clock-names = "fout_spll",
>> + "mout_sclk_spll",
>> + "ff_dout_spll2",
>> + "fout_bpll",
>> + "mout_bpll",
>> + "sclk_bpll",
>> + "mout_mx_mspll_ccore",
>> + "mout_mx_mspll_ccore_phy",
>> + "mout_mclk_cdrex",
>> + "dout_clk2x_phy0",
>> + "clkm_phy0",
>> + "clkm_phy1";
>> + status = "okay";
>> + operating-points-v2 = <&dmc_opp_table>;
>> + devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
>> + <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
>> + operating-points-v2 = <&dmc_opp_table>;
>> + device-handle = <&samsung_K3QF2F20DB>;
>> + vdd-supply = <&buck1_reg>;
>> + };
>> --
>> 2.7.4
>>
>
>
next prev parent reply other threads:[~2019-04-29 12:14 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20190419141938eucas1p16ee6cdf897184df33cf67b55c5f3c449@eucas1p1.samsung.com>
2019-04-19 14:19 ` [PATCH v6 0/10] Exynos5 Dynamic Memory Controller driver Lukasz Luba
[not found] ` <CGME20190419141940eucas1p295a1130863cf2e69476ca0ba11a8a102@eucas1p2.samsung.com>
2019-04-19 14:19 ` [PATCH v6 01/10] clk: samsung: add needed IDs for DMC clocks in Exynos5420 Lukasz Luba
2019-04-30 4:47 ` Chanwoo Choi
2019-04-30 12:36 ` Lukasz Luba
[not found] ` <CGME20190419141942eucas1p2eaa1d17d785a27632b214a2da011a9fb@eucas1p2.samsung.com>
2019-04-19 14:19 ` [PATCH v6 02/10] clk: samsung: add new clocks for DMC for Exynos5422 SoC Lukasz Luba
2019-04-30 1:31 ` Chanwoo Choi
2019-04-30 13:12 ` Lukasz Luba
[not found] ` <CGME20190419141943eucas1p220d77bacfc4fcba8ec6a10f540e1a27d@eucas1p2.samsung.com>
2019-04-19 14:19 ` [PATCH v6 03/10] clk: samsung: add BPLL rate table for Exynos 5422 SoC Lukasz Luba
2019-05-02 5:15 ` Chanwoo Choi
2019-05-02 14:23 ` Lukasz Luba
[not found] ` <CGME20190419141945eucas1p1c95d65f261f82da5c856c0f2fcf1ce87@eucas1p1.samsung.com>
2019-04-19 14:19 ` [PATCH v6 04/10] Documentation: dt: device tree bindings for LPDDR3 memories Lukasz Luba
2019-04-25 19:51 ` Rob Herring
2019-04-29 12:04 ` Lukasz Luba
2019-04-29 16:36 ` Rob Herring
2019-04-30 20:04 ` Lukasz Luba
2019-04-25 19:53 ` Rob Herring
2019-04-29 12:05 ` Lukasz Luba
[not found] ` <CGME20190419141946eucas1p2fffda29e18080fd3573f625f0cf2b7f8@eucas1p2.samsung.com>
2019-04-19 14:19 ` [PATCH v6 05/10] drivers: memory: extend of_memory by LPDDR3 support Lukasz Luba
[not found] ` <CGME20190419141947eucas1p13a27605e04169ab528ef5bfb385eddbc@eucas1p1.samsung.com>
2019-04-19 14:19 ` [PATCH v6 06/10] dt-bindings: memory-controllers: add Exynos5422 DMC device description Lukasz Luba
2019-04-25 19:57 ` Rob Herring
2019-04-29 12:14 ` Lukasz Luba [this message]
2019-04-29 16:43 ` Rob Herring
2019-04-30 20:15 ` Lukasz Luba
2019-04-30 4:46 ` Chanwoo Choi
2019-04-30 20:30 ` Lukasz Luba
2019-05-02 1:35 ` Chanwoo Choi
2019-05-02 18:56 ` Lukasz Luba
[not found] ` <CGME20190419141949eucas1p2a3ca13166210b6bc5741808055650e04@eucas1p2.samsung.com>
2019-04-19 14:19 ` [PATCH v6 07/10] drivers: memory: add DMC driver for Exynos5422 Lukasz Luba
2019-04-23 11:27 ` Krzysztof Kozlowski
2019-04-29 14:51 ` Lukasz Luba
[not found] ` <CGME20190419141950eucas1p2e810215d1ceaf75fc9e807bbaa78e003@eucas1p2.samsung.com>
2019-04-19 14:19 ` [PATCH v6 08/10] drivers: devfreq: events: add Exynos PPMU new events Lukasz Luba
[not found] ` <CGME20190419141952eucas1p11dc36f30c873a947122e0f7e8d55a3bb@eucas1p1.samsung.com>
2019-04-19 14:19 ` [PATCH v6 09/10] ARM: dts: exynos: add DMC device for exynos5422 Lukasz Luba
2019-04-23 11:03 ` Krzysztof Kozlowski
2019-04-29 12:38 ` Lukasz Luba
[not found] ` <CGME20190419141953eucas1p1b403be15353fa31de3e226599b675f67@eucas1p1.samsung.com>
2019-04-19 14:19 ` [PATCH v6 10/10] ARM: exynos_defconfig: enable DMC driver Lukasz Luba
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