* [RFC PATCH v2 0/3] Support CPU hotplug for ARM64
@ 2019-06-29 2:42 Xiongfeng Wang
2019-06-29 2:42 ` [RFC PATCH v2 1/3] ACPI / scan: evaluate _STA for processors declared via ASL Device statement Xiongfeng Wang
` (4 more replies)
0 siblings, 5 replies; 15+ messages in thread
From: Xiongfeng Wang @ 2019-06-29 2:42 UTC (permalink / raw)
To: rjw, catalin.marinas, james.morse
Cc: linux-acpi, linux-kernel, linux-arm-kernel, guohanjun, xiexiuqi,
huawei.libin, john.garry, jonathan.cameron, wangxiongfeng2
This patchset mark all the GICC node in MADT as possible CPUs even though it
is disabled. But only those enabled GICC node are marked as present CPUs.
So that kernel will initialize some CPU related data structure in advance before
the CPU is actually hot added into the system. This patchset also implement
'acpi_(un)map_cpu()' and 'arch_(un)register_cpu()' for ARM64. These functions are
needed to enable CPU hotplug.
To support CPU hotplug, we need to add all the possible GICC node in MADT
including those CPUs that are not present but may be hot added later. Those
CPUs are marked as disabled in GICC nodes.
Changelog:
v1 -> v2:
rebase the thrid patch to the lastest kernel
Xiongfeng Wang (3):
ACPI / scan: evaluate _STA for processors declared via ASL Device
statement
arm64: mark all the GICC nodes in MADT as possible cpu
arm64: Add CPU hotplug support
arch/arm64/kernel/acpi.c | 22 ++++++++++++++++++++++
arch/arm64/kernel/setup.c | 19 ++++++++++++++++++-
arch/arm64/kernel/smp.c | 11 +++++------
drivers/acpi/scan.c | 12 ++++++++++++
4 files changed, 57 insertions(+), 7 deletions(-)
--
1.7.12.4
^ permalink raw reply [flat|nested] 15+ messages in thread* [RFC PATCH v2 1/3] ACPI / scan: evaluate _STA for processors declared via ASL Device statement
2019-06-29 2:42 [RFC PATCH v2 0/3] Support CPU hotplug for ARM64 Xiongfeng Wang
@ 2019-06-29 2:42 ` Xiongfeng Wang
2019-06-29 2:42 ` [RFC PATCH v2 2/3] arm64: mark all the GICC nodes in MADT as possible cpu Xiongfeng Wang
` (3 subsequent siblings)
4 siblings, 0 replies; 15+ messages in thread
From: Xiongfeng Wang @ 2019-06-29 2:42 UTC (permalink / raw)
To: rjw, catalin.marinas, james.morse
Cc: linux-acpi, linux-kernel, linux-arm-kernel, guohanjun, xiexiuqi,
huawei.libin, john.garry, jonathan.cameron, wangxiongfeng2
When we scan all the acpi namespace node in
acpi_scan_init()->acpi_bus_scan(), we evaluate '_STA' method for processor
type node to determine whether the device is present. But processors can
also be declared via ASL Device statement. ACPI 6.3 spec specifically
says that the Processor statement is deprecated and a Device statement
should be used for processors. In that case, acpi_object_type is
ACPI_TYPE_DEVICE rather than ACPI_TYPE_PROCESSOR.
Current code doesn't evaluate '_STA' for nodes with ACPI_TYPE_DEVICE, and
the device status is set to 'present' as default. This patch get the
device status from '_STA' method for processors declared via ASL Device
statement if it does have a '_STA' method.
Signed-off-by: Xiongfeng Wang <wangxiongfeng2@huawei.com>
---
I am not sure if I should set 'type' as ACPI_BUS_TYPE_PROCESSOR rather
than ACPI_BUS_TYPE_DEVICE for processors declared via ASL Device
statement.
---
drivers/acpi/scan.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c
index 0e28270..cec43f6 100644
--- a/drivers/acpi/scan.c
+++ b/drivers/acpi/scan.c
@@ -16,6 +16,7 @@
#include <linux/dma-mapping.h>
#include <linux/platform_data/x86/apple.h>
+#include <acpi/processor.h>
#include <asm/pgtable.h>
#include "internal.h"
@@ -1687,6 +1688,7 @@ static int acpi_bus_type_and_status(acpi_handle handle, int *type,
{
acpi_status status;
acpi_object_type acpi_type;
+ struct acpi_device_info *info;
status = acpi_get_type(handle, &acpi_type);
if (ACPI_FAILURE(status))
@@ -1699,6 +1701,16 @@ static int acpi_bus_type_and_status(acpi_handle handle, int *type,
return -ENODEV;
*type = ACPI_BUS_TYPE_DEVICE;
+
+ status = acpi_get_object_info(handle, &info);
+ if (ACPI_SUCCESS(status) && info->valid & ACPI_VALID_HID &&
+ !strcmp(info->hardware_id.string,
+ ACPI_PROCESSOR_DEVICE_HID)) {
+ status = acpi_bus_get_status_handle(handle, sta);
+ if (ACPI_SUCCESS(status))
+ break;
+ }
+
/*
* acpi_add_single_object updates this once we've an acpi_device
* so that acpi_bus_get_status' quirk handling can be used.
--
1.7.12.4
^ permalink raw reply related [flat|nested] 15+ messages in thread* [RFC PATCH v2 2/3] arm64: mark all the GICC nodes in MADT as possible cpu
2019-06-29 2:42 [RFC PATCH v2 0/3] Support CPU hotplug for ARM64 Xiongfeng Wang
2019-06-29 2:42 ` [RFC PATCH v2 1/3] ACPI / scan: evaluate _STA for processors declared via ASL Device statement Xiongfeng Wang
@ 2019-06-29 2:42 ` Xiongfeng Wang
2019-07-04 6:46 ` Jia He
2019-06-29 2:42 ` [RFC PATCH v2 3/3] arm64: Add CPU hotplug support Xiongfeng Wang
` (2 subsequent siblings)
4 siblings, 1 reply; 15+ messages in thread
From: Xiongfeng Wang @ 2019-06-29 2:42 UTC (permalink / raw)
To: rjw, catalin.marinas, james.morse
Cc: linux-acpi, linux-kernel, linux-arm-kernel, guohanjun, xiexiuqi,
huawei.libin, john.garry, jonathan.cameron, wangxiongfeng2
We set 'cpu_possible_mask' based on the enabled GICC node in MADT. If
the GICC node is disabled, we will skip initializing the kernel data
structure for that CPU.
To support CPU hotplug, we need to initialize some CPU related data
structure in advance. This patch mark all the GICC nodes as possible CPU
and only these enabled GICC nodes as present CPU.
Signed-off-by: Xiongfeng Wang <wangxiongfeng2@huawei.com>
---
arch/arm64/kernel/setup.c | 2 +-
arch/arm64/kernel/smp.c | 11 +++++------
2 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
index 7e541f9..7f4d12a 100644
--- a/arch/arm64/kernel/setup.c
+++ b/arch/arm64/kernel/setup.c
@@ -359,7 +359,7 @@ static int __init topology_init(void)
for_each_online_node(i)
register_one_node(i);
- for_each_possible_cpu(i) {
+ for_each_online_cpu(i) {
struct cpu *cpu = &per_cpu(cpu_data.cpu, i);
cpu->hotpluggable = 1;
register_cpu(cpu, i);
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index 6dcf960..6d9983c 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -525,16 +525,14 @@ struct acpi_madt_generic_interrupt *acpi_cpu_get_madt_gicc(int cpu)
{
u64 hwid = processor->arm_mpidr;
- if (!(processor->flags & ACPI_MADT_ENABLED)) {
- pr_debug("skipping disabled CPU entry with 0x%llx MPIDR\n", hwid);
- return;
- }
-
if (hwid & ~MPIDR_HWID_BITMASK || hwid == INVALID_HWID) {
pr_err("skipping CPU entry with invalid MPIDR 0x%llx\n", hwid);
return;
}
+ if (!(processor->flags & ACPI_MADT_ENABLED))
+ pr_debug("disabled CPU entry with 0x%llx MPIDR\n", hwid);
+
if (is_mpidr_duplicate(cpu_count, hwid)) {
pr_err("duplicate CPU MPIDR 0x%llx in MADT\n", hwid);
return;
@@ -755,7 +753,8 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
if (err)
continue;
- set_cpu_present(cpu, true);
+ if ((cpu_madt_gicc[cpu].flags & ACPI_MADT_ENABLED))
+ set_cpu_present(cpu, true);
numa_store_cpu_info(cpu);
}
}
--
1.7.12.4
^ permalink raw reply related [flat|nested] 15+ messages in thread* [RFC PATCH v2 3/3] arm64: Add CPU hotplug support 2019-06-29 2:42 [RFC PATCH v2 0/3] Support CPU hotplug for ARM64 Xiongfeng Wang 2019-06-29 2:42 ` [RFC PATCH v2 1/3] ACPI / scan: evaluate _STA for processors declared via ASL Device statement Xiongfeng Wang 2019-06-29 2:42 ` [RFC PATCH v2 2/3] arm64: mark all the GICC nodes in MADT as possible cpu Xiongfeng Wang @ 2019-06-29 2:42 ` Xiongfeng Wang 2019-06-29 3:23 ` [RFC PATCH v2 0/3] Support CPU hotplug for ARM64 Xiongfeng Wang 2019-07-05 10:12 ` James Morse 4 siblings, 0 replies; 15+ messages in thread From: Xiongfeng Wang @ 2019-06-29 2:42 UTC (permalink / raw) To: rjw, catalin.marinas, james.morse Cc: linux-acpi, linux-kernel, linux-arm-kernel, guohanjun, xiexiuqi, huawei.libin, john.garry, jonathan.cameron, wangxiongfeng2 To support CPU hotplug, we need to implement 'acpi_(un)map_cpu()' and 'arch_(un)register_cpu()' for ARM64. These functions are called in 'acpi_processor_hotadd_init()/acpi_processor_remove()' when the CPU is hot added into or hot removed from the system. Signed-off-by: Xiongfeng Wang <wangxiongfeng2@huawei.com> --- arch/arm64/kernel/acpi.c | 22 ++++++++++++++++++++++ arch/arm64/kernel/setup.c | 17 +++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c index 2804330..57835fa 100644 --- a/arch/arm64/kernel/acpi.c +++ b/arch/arm64/kernel/acpi.c @@ -25,6 +25,7 @@ #include <linux/serial_core.h> #include <acpi/ghes.h> +#include <acpi/processor.h> #include <asm/cputype.h> #include <asm/cpu_ops.h> #include <asm/daifflags.h> @@ -284,3 +285,24 @@ int apei_claim_sea(struct pt_regs *regs) return err; } + +int acpi_map_cpu(acpi_handle handle, phys_cpuid_t physid, u32 acpi_id, + int *pcpu) +{ + int cpu; + + cpu = acpi_map_cpuid(physid, acpi_id); + *pcpu = cpu; + set_cpu_present(cpu, true); + + return 0; +} +EXPORT_SYMBOL(acpi_map_cpu); + +int acpi_unmap_cpu(int cpu) +{ + set_cpu_present(cpu, false); + + return 0; +} +EXPORT_SYMBOL(acpi_unmap_cpu); diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c index 7f4d12a..f2a881e 100644 --- a/arch/arm64/kernel/setup.c +++ b/arch/arm64/kernel/setup.c @@ -398,3 +398,20 @@ static int __init register_kernel_offset_dumper(void) return 0; } __initcall(register_kernel_offset_dumper); + +int arch_register_cpu(int num) +{ + struct cpu *cpu = &per_cpu(cpu_data.cpu, num); + + cpu->hotpluggable = 1; + return register_cpu(cpu, num); +} +EXPORT_SYMBOL(arch_register_cpu); + +void arch_unregister_cpu(int num) +{ + struct cpu *cpu = &per_cpu(cpu_data.cpu, num); + + unregister_cpu(cpu); +} +EXPORT_SYMBOL(arch_unregister_cpu); -- 1.7.12.4 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [RFC PATCH v2 0/3] Support CPU hotplug for ARM64
2019-06-29 2:42 [RFC PATCH v2 0/3] Support CPU hotplug for ARM64 Xiongfeng Wang
` (2 preceding siblings ...)
2019-06-29 2:42 ` [RFC PATCH v2 3/3] arm64: Add CPU hotplug support Xiongfeng Wang
@ 2019-06-29 3:23 ` Xiongfeng Wang
2019-07-05 10:12 ` James Morse
4 siblings, 0 replies; 15+ messages in thread
From: Xiongfeng Wang @ 2019-06-29 3:23 UTC (permalink / raw)
To: rjw, catalin.marinas, james.morse
Cc: linux-acpi, linux-kernel, linux-arm-kernel, guohanjun, xiexiuqi,
huawei.libin, john.garry, jonathan.cameron
[-- Attachment #1: Type: text/plain, Size: 2758 bytes --]
My test process is as follows:
1. Use the following command to boot a Guest OS with 8 CPUs
qemu-system-aarch64 -machine virt -cpu cortex-a57 -machine type=virt \
-nographic -m 2048 -smp cpus=8,sockets=2,cores=4 \
-numa node,mem=1024,cpus=0-3 -numa node,mem=1024,cpus=4-7 \
-kernel $IMAGE_FILE -bios /home/wxf/QEMU_EFI.fd \
--initrd $INITRDFS_FILE \
--append "root=/dev/ram rdinit=/linuxrc earlycon=pl011,0x9000000 acpi.debug_layer=0xffffffff acpi.debug_level=0x2" \
--fsdev local,id=kmod_dev,path=$VIRFS,security_model=none \
-device virtio-9p-device,fsdev=kmod_dev,mount_tag=kmod_mount
2. Extract the ACPI table DSDT and APIC. Mark CPU6 as disabled in APIC.
Add '_STA' and '_EJ0' method for CPU6 in DSDT.
Modified tables are attached as attachment. I referred to the following two
documents to override the ACPI tables.
Documentation/admin-guide/acpi/initrd_table_override.rst
Documentation/admin-guide/acpi/dsdt-override.rst
3. Add a procfs interface to sent a event to a namespace node in DSDT.
It is used to emulate the SCI interrupt. It is based on https://lwn.net/Articles/84089/
The patch is attached.
4. Use the following commands to test hot-add and hot-remove
a. echo "C006 1" > /proc/acpi/sci/notify
b. echo 1 > /sys/devices/system/cpu/cpu6/online
c. use 'taskset' to run an application on CPU6
d. echo 0 > /sys/devices/system/cpu/cpu6/online
e. echo "C006 3" > /proc/acpi/sci/notify
Thanks,
Xiongfeng Wang
On 2019/6/29 10:42, Xiongfeng Wang wrote:
> This patchset mark all the GICC node in MADT as possible CPUs even though it
> is disabled. But only those enabled GICC node are marked as present CPUs.
> So that kernel will initialize some CPU related data structure in advance before
> the CPU is actually hot added into the system. This patchset also implement
> 'acpi_(un)map_cpu()' and 'arch_(un)register_cpu()' for ARM64. These functions are
> needed to enable CPU hotplug.
>
> To support CPU hotplug, we need to add all the possible GICC node in MADT
> including those CPUs that are not present but may be hot added later. Those
> CPUs are marked as disabled in GICC nodes.
>
> Changelog:
>
> v1 -> v2:
> rebase the thrid patch to the lastest kernel
>
> Xiongfeng Wang (3):
> ACPI / scan: evaluate _STA for processors declared via ASL Device
> statement
> arm64: mark all the GICC nodes in MADT as possible cpu
> arm64: Add CPU hotplug support
>
> arch/arm64/kernel/acpi.c | 22 ++++++++++++++++++++++
> arch/arm64/kernel/setup.c | 19 ++++++++++++++++++-
> arch/arm64/kernel/smp.c | 11 +++++------
> drivers/acpi/scan.c | 12 ++++++++++++
> 4 files changed, 57 insertions(+), 7 deletions(-)
>
[-- Attachment #2: 0001-SCI-interrupt-emulation.patch --]
[-- Type: text/plain, Size: 6090 bytes --]
From b85ec923dc0086ce229e5ec3ed20b054570bfc8a Mon Sep 17 00:00:00 2001
From: Xiongfeng Wang <wangxiongfeng2@huawei.com>
Date: Tue, 18 Jun 2019 20:35:02 +0800
Subject: [PATCH] SCI interrupt emulation
This patch can be used to send event to a namespace node.
It is based on the following patchset.
https://lwn.net/Articles/84089/
---
drivers/acpi/Kconfig | 11 ++++
drivers/acpi/bus.c | 152 +++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 163 insertions(+)
diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig
index fb91fe3..f93fa91 100644
--- a/drivers/acpi/Kconfig
+++ b/drivers/acpi/Kconfig
@@ -550,6 +550,16 @@ config ACPI_CONFIGFS
if ARM64
source "drivers/acpi/arm64/Kconfig"
+config ACPI_SCI_EMULATE
+ bool "ACPI SCI Event Emulation Support"
+ depends on ACPI
+ default n
+ help
+ This driver will enable your system to emulate sci hotplug event
+ notification through proc file system. For example user needs to
+ echo "XXX 0" > /proc/acpi/sci/notify (where, XXX is a target ACPI
+ device object name).
+
config ACPI_PPTT
bool
endif
@@ -587,3 +597,4 @@ config X86_PM_TIMER
You should nearly always say Y here because many modern
systems require this timer.
+
diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c
index d2e29a1..9733031 100644
--- a/drivers/acpi/bus.c
+++ b/drivers/acpi/bus.c
@@ -44,6 +44,19 @@
#include "internal.h"
+#ifdef CONFIG_ACPI_SCI_EMULATE
+#include <acpi/acpi.h>
+#include "acpica/accommon.h"
+#include "acpica/acnamesp.h"
+#include "acpica/acevents.h"
+#include "acpica/acinterp.h"
+
+static int acpi_init_sci_emulate(void);
+static void acpi_sci_notify_client(char *acpi_name, u32 event);
+#else
+#define acpi_init_sci_emulate()
+#endif
+
#define _COMPONENT ACPI_BUS_COMPONENT
ACPI_MODULE_NAME("bus");
@@ -51,6 +64,10 @@ struct acpi_device *acpi_root;
struct proc_dir_entry *acpi_root_dir;
EXPORT_SYMBOL(acpi_root_dir);
+#ifdef CONFIG_ACPI_SCI_EMULATE
+struct proc_dir_entry *acpi_sci_dir;
+#endif
+
#ifdef CONFIG_X86
#ifdef CONFIG_ACPI_CUSTOM_DSDT
static inline int set_copy_dsdt(const struct dmi_system_id *id)
@@ -1221,6 +1238,8 @@ static int __init acpi_bus_init(void)
*/
acpi_root_dir = proc_mkdir(ACPI_BUS_FILE_ROOT, NULL);
+ acpi_init_sci_emulate();
+
result = bus_register(&acpi_bus_type);
if (!result)
return 0;
@@ -1269,3 +1288,136 @@ static int __init acpi_init(void)
}
subsys_initcall(acpi_init);
+
+#ifdef CONFIG_ACPI_SCI_EMULATE
+/****** Code to emulate SCI interrupt for Hotplug node insertion/removal ******/
+
+static ssize_t acpi_sci_notify_write_proc(struct file *file, const char __user *buffer,
+ size_t count, loff_t *data)
+{
+ u32 event;
+ char *name1 = NULL;
+ char *name2 = NULL;
+ char *end_name = NULL;
+ const char *delim = " ";
+ char *temp_buf = NULL;
+ char *temp_buf_addr = NULL;
+
+ printk(KERN_INFO PREFIX "Inside acpi_sci_notify_write_proc\n");
+
+ temp_buf = kmalloc(count+1, GFP_ATOMIC);
+ if (!temp_buf) {
+ printk(KERN_WARNING PREFIX "Inside acpi_sci_notify_wire_proc: Memory allocation failed\n");
+ return count;
+ }
+ temp_buf[count] = '\0';
+ temp_buf_addr = temp_buf;
+ memcpy(temp_buf, buffer, count);
+ name1 = strsep(&temp_buf, delim);
+ name2 = strsep(&temp_buf, delim);
+
+ if(name1 && name2)
+ event = simple_strtoul(name2, &end_name, 10);
+ else {
+ printk(KERN_WARNING PREFIX "unknown device\n");
+ kfree(temp_buf_addr);
+ return count;
+ }
+
+ printk(KERN_INFO PREFIX "ACPI device name is <%s>, event code is <%d>\n",\
+ name1, event);
+
+ acpi_sci_notify_client(name1, event);
+
+ kfree(temp_buf_addr);
+
+ return count;
+}
+
+static void acpi_sci_notify_client(char *acpi_name, u32 event)
+{
+ struct acpi_namespace_node *node;
+ acpi_status status, status1;
+ acpi_handle hlsb, hsb;
+ unsigned long long sta;
+ //union acpi_operand_object *obj_desc;
+
+ status = acpi_get_handle(NULL, "\\_SB", &hsb);
+ status1 = acpi_get_handle(hsb, acpi_name, &hlsb);
+ if(ACPI_FAILURE(status) || ACPI_FAILURE(status1)){
+ printk(KERN_ERR PREFIX "acpi getting handle to <\\_SB.%s> failed inside notify_client\n", \
+ acpi_name);
+ return;
+ }
+
+ status = acpi_ut_acquire_mutex(ACPI_MTX_NAMESPACE);
+ if(ACPI_FAILURE(status)) {
+ printk(KERN_ERR PREFIX "Acquiring acpi namespace mutext failed\n");
+ return;
+ }
+
+ node = acpi_ns_validate_handle(hlsb);
+ if(!node) {
+ (void) acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+ printk(KERN_ERR PREFIX "Mapping handle to node failed\n");
+ return;
+ }
+
+ /* Check for internal object and make sure there is a handler registered for this object */
+
+ //obj_desc = acpi_ns_get_attached_object (node);
+ //if(obj_desc) {
+ // if(obj_desc->common_notify.system_notify){
+ /* Release the lock and queue the item for later exectuion */
+ (void) acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+ if (event == 1)
+ acpi_evaluate_integer(hlsb, "_SCP", NULL, &sta);
+ status = acpi_ev_queue_notify_request(node, event);
+ if(ACPI_FAILURE(status)){
+ printk(KERN_ERR PREFIX "acpi_ev_queue_notify_request failed\n");
+ }else {
+ printk(KERN_INFO PREFIX "Notify event is queued\n");
+ }
+ return;
+// }
+// }else {
+// printk(KERN_INFO PREFIX "Notify handler not registered for this device\n");
+// }
+
+
+ (void) acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+ return;
+}
+
+int proc_sci_show(struct seq_file *m, void *v)
+{
+ seq_printf(m, "%s\n", "test");
+
+ return 0;
+}
+
+static int proc_sci_open(struct inode *inode, struct file *filp)
+{
+ return single_open(filp, proc_sci_show, NULL);
+}
+struct file_operations notify_ops = {
+ .open = proc_sci_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .write = acpi_sci_notify_write_proc,
+ .release = single_release,
+};
+
+static int acpi_init_sci_emulate(void)
+{
+ ACPI_FUNCTION_TRACE("acpi_init_sci_emulate");
+
+ acpi_sci_dir = proc_mkdir("sci", acpi_root_dir);
+ if (!acpi_sci_dir)
+ return_VALUE(-ENODEV);
+
+ proc_create("notify", S_IWUGO|S_IRUGO, acpi_sci_dir, ¬ify_ops);
+
+ return_VALUE(0);
+}
+#endif
--
2.7.4
[-- Attachment #3: APIC.dsl --]
[-- Type: text/plain, Size: 15266 bytes --]
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20160108-64
* Copyright (c) 2000 - 2016 Intel Corporation
*
* Disassembly of APIC, Tue Jun 18 12:18:04 2019
*
* ACPI Data Table [APIC]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
[004h 0004 4] Table Length : 000002DC
[008h 0008 1] Revision : 03
[009h 0009 1] Checksum : 18
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPCAPIC"
[018h 0024 4] Oem Revision : 00000002
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 4] Local Apic Address : 00000000
[028h 0040 4] Flags (decoded below) : 00000000
PC-AT Compatibility : 0
[02Ch 0044 1] Subtable Type : 0C [Generic Interrupt Distributor]
[02Dh 0045 1] Length : 18
[02Eh 0046 2] Reserved : 0000
[030h 0048 4] Local GIC Hardware ID : 00000000
[034h 0052 8] Base Address : 0000000008000000
[03Ch 0060 4] Interrupt Base : 00000000
[040h 0064 1] Version : 02
[041h 0065 3] Reserved : 000000
[044h 0068 1] Subtable Type : 0B [Generic Interrupt Controller]
[045h 0069 1] Length : 50
[046h 0070 2] Reserved : 0000
[048h 0072 4] CPU Interface Number : 00000000
[04Ch 0076 4] Processor UID : 00000000
[050h 0080 4] Flags (decoded below) : 00000001
Processor Enabled : 1
Performance Interrupt Trigger Mode : 0
Virtual GIC Interrupt Trigger Mode : 0
[054h 0084 4] Parking Protocol Version : 00000000
[058h 0088 4] Performance Interrupt : 00000017
[05Ch 0092 8] Parked Address : 0000000000000000
[064h 0100 8] Base Address : 0000000008010000
[06Ch 0108 8] Virtual GIC Base Address : 0000000000000000
[074h 0116 8] Hypervisor GIC Base Address : 0000000000000000
[07Ch 0124 4] Virtual GIC Interrupt : 00000000
[080h 0128 8] Redistributor Base Address : 0000000000000000
[088h 0136 8] ARM MPIDR : 0000000000000000
[088h 0136 1] Processor Power Efficiency Class : 00
[041h 0065 3] Reserved : 000000
/**** ACPI subtable terminates early - may be older version (dump table) */
[090h 0144 1] Subtable Type : 0B [Generic Interrupt Controller]
[091h 0145 1] Length : 50
[092h 0146 2] Reserved : 0000
[094h 0148 4] CPU Interface Number : 00000001
[098h 0152 4] Processor UID : 00000001
[09Ch 0156 4] Flags (decoded below) : 00000001
Processor Enabled : 1
Performance Interrupt Trigger Mode : 0
Virtual GIC Interrupt Trigger Mode : 0
[0A0h 0160 4] Parking Protocol Version : 00000000
[0A4h 0164 4] Performance Interrupt : 00000017
[0A8h 0168 8] Parked Address : 0000000000000000
[0B0h 0176 8] Base Address : 0000000008010000
[0B8h 0184 8] Virtual GIC Base Address : 0000000000000000
[0C0h 0192 8] Hypervisor GIC Base Address : 0000000000000000
[0C8h 0200 4] Virtual GIC Interrupt : 00000000
[0CCh 0204 8] Redistributor Base Address : 0000000000000000
[0D4h 0212 8] ARM MPIDR : 0000000000000001
[088h 0136 1] Processor Power Efficiency Class : 00
[041h 0065 3] Reserved : 000000
/**** ACPI subtable terminates early - may be older version (dump table) */
[0DCh 0220 1] Subtable Type : 0B [Generic Interrupt Controller]
[0DDh 0221 1] Length : 50
[0DEh 0222 2] Reserved : 0000
[0E0h 0224 4] CPU Interface Number : 00000002
[0E4h 0228 4] Processor UID : 00000002
[0E8h 0232 4] Flags (decoded below) : 00000001
Processor Enabled : 1
Performance Interrupt Trigger Mode : 0
Virtual GIC Interrupt Trigger Mode : 0
[0ECh 0236 4] Parking Protocol Version : 00000000
[0F0h 0240 4] Performance Interrupt : 00000017
[0F4h 0244 8] Parked Address : 0000000000000000
[0FCh 0252 8] Base Address : 0000000008010000
[104h 0260 8] Virtual GIC Base Address : 0000000000000000
[10Ch 0268 8] Hypervisor GIC Base Address : 0000000000000000
[114h 0276 4] Virtual GIC Interrupt : 00000000
[118h 0280 8] Redistributor Base Address : 0000000000000000
[120h 0288 8] ARM MPIDR : 0000000000000002
[088h 0136 1] Processor Power Efficiency Class : 00
[041h 0065 3] Reserved : 000000
/**** ACPI subtable terminates early - may be older version (dump table) */
[128h 0296 1] Subtable Type : 0B [Generic Interrupt Controller]
[129h 0297 1] Length : 50
[12Ah 0298 2] Reserved : 0000
[12Ch 0300 4] CPU Interface Number : 00000003
[130h 0304 4] Processor UID : 00000003
[134h 0308 4] Flags (decoded below) : 00000001
Processor Enabled : 1
Performance Interrupt Trigger Mode : 0
Virtual GIC Interrupt Trigger Mode : 0
[138h 0312 4] Parking Protocol Version : 00000000
[13Ch 0316 4] Performance Interrupt : 00000017
[140h 0320 8] Parked Address : 0000000000000000
[148h 0328 8] Base Address : 0000000008010000
[150h 0336 8] Virtual GIC Base Address : 0000000000000000
[158h 0344 8] Hypervisor GIC Base Address : 0000000000000000
[160h 0352 4] Virtual GIC Interrupt : 00000000
[164h 0356 8] Redistributor Base Address : 0000000000000000
[16Ch 0364 8] ARM MPIDR : 0000000000000003
[088h 0136 1] Processor Power Efficiency Class : 00
[041h 0065 3] Reserved : 000000
/**** ACPI subtable terminates early - may be older version (dump table) */
[174h 0372 1] Subtable Type : 0B [Generic Interrupt Controller]
[175h 0373 1] Length : 50
[176h 0374 2] Reserved : 0000
[178h 0376 4] CPU Interface Number : 00000004
[17Ch 0380 4] Processor UID : 00000004
[180h 0384 4] Flags (decoded below) : 00000001
Processor Enabled : 1
Performance Interrupt Trigger Mode : 0
Virtual GIC Interrupt Trigger Mode : 0
[184h 0388 4] Parking Protocol Version : 00000000
[188h 0392 4] Performance Interrupt : 00000017
[18Ch 0396 8] Parked Address : 0000000000000000
[194h 0404 8] Base Address : 0000000008010000
[19Ch 0412 8] Virtual GIC Base Address : 0000000000000000
[1A4h 0420 8] Hypervisor GIC Base Address : 0000000000000000
[1ACh 0428 4] Virtual GIC Interrupt : 00000000
[1B0h 0432 8] Redistributor Base Address : 0000000000000000
[1B8h 0440 8] ARM MPIDR : 0000000000000004
[088h 0136 1] Processor Power Efficiency Class : 00
[041h 0065 3] Reserved : 000000
/**** ACPI subtable terminates early - may be older version (dump table) */
[1C0h 0448 1] Subtable Type : 0B [Generic Interrupt Controller]
[1C1h 0449 1] Length : 50
[1C2h 0450 2] Reserved : 0000
[1C4h 0452 4] CPU Interface Number : 00000005
[1C8h 0456 4] Processor UID : 00000005
[1CCh 0460 4] Flags (decoded below) : 00000001
Processor Enabled : 1
Performance Interrupt Trigger Mode : 0
Virtual GIC Interrupt Trigger Mode : 0
[1D0h 0464 4] Parking Protocol Version : 00000000
[1D4h 0468 4] Performance Interrupt : 00000017
[1D8h 0472 8] Parked Address : 0000000000000000
[1E0h 0480 8] Base Address : 0000000008010000
[1E8h 0488 8] Virtual GIC Base Address : 0000000000000000
[1F0h 0496 8] Hypervisor GIC Base Address : 0000000000000000
[1F8h 0504 4] Virtual GIC Interrupt : 00000000
[1FCh 0508 8] Redistributor Base Address : 0000000000000000
[204h 0516 8] ARM MPIDR : 0000000000000005
[088h 0136 1] Processor Power Efficiency Class : 00
[041h 0065 3] Reserved : 000000
/**** ACPI subtable terminates early - may be older version (dump table) */
[20Ch 0524 1] Subtable Type : 0B [Generic Interrupt Controller]
[20Dh 0525 1] Length : 50
[20Eh 0526 2] Reserved : 0000
[210h 0528 4] CPU Interface Number : 00000006
[214h 0532 4] Processor UID : 00000006
[218h 0536 4] Flags (decoded below) : 00000000
Processor Enabled : 0
Performance Interrupt Trigger Mode : 0
Virtual GIC Interrupt Trigger Mode : 0
[21Ch 0540 4] Parking Protocol Version : 00000000
[220h 0544 4] Performance Interrupt : 00000017
[224h 0548 8] Parked Address : 0000000000000000
[22Ch 0556 8] Base Address : 0000000008010000
[234h 0564 8] Virtual GIC Base Address : 0000000000000000
[23Ch 0572 8] Hypervisor GIC Base Address : 0000000000000000
[244h 0580 4] Virtual GIC Interrupt : 00000000
[248h 0584 8] Redistributor Base Address : 0000000000000000
[250h 0592 8] ARM MPIDR : 0000000000000006
[088h 0136 1] Processor Power Efficiency Class : 00
[041h 0065 3] Reserved : 000000
/**** ACPI subtable terminates early - may be older version (dump table) */
[258h 0600 1] Subtable Type : 0B [Generic Interrupt Controller]
[259h 0601 1] Length : 50
[25Ah 0602 2] Reserved : 0000
[25Ch 0604 4] CPU Interface Number : 00000007
[260h 0608 4] Processor UID : 00000007
[264h 0612 4] Flags (decoded below) : 00000000
Processor Enabled : 0
Performance Interrupt Trigger Mode : 0
Virtual GIC Interrupt Trigger Mode : 0
[268h 0616 4] Parking Protocol Version : 00000000
[26Ch 0620 4] Performance Interrupt : 00000017
[270h 0624 8] Parked Address : 0000000000000000
[278h 0632 8] Base Address : 0000000008010000
[280h 0640 8] Virtual GIC Base Address : 0000000000000000
[288h 0648 8] Hypervisor GIC Base Address : 0000000000000000
[290h 0656 4] Virtual GIC Interrupt : 00000000
[294h 0660 8] Redistributor Base Address : 0000000000000000
[29Ch 0668 8] ARM MPIDR : 0000000000000007
[088h 0136 1] Processor Power Efficiency Class : 00
[041h 0065 3] Reserved : 000000
/**** ACPI subtable terminates early - may be older version (dump table) */
[2A4h 0676 1] Subtable Type : 0D [Generic MSI Frame]
[2A5h 0677 1] Length : 18
[2A6h 0678 2] Reserved : 0000
[2A8h 0680 4] MSI Frame ID : 00000000
[2ACh 0684 8] Base Address : 0000000008020000
[2B4h 0692 4] Flags (decoded below) : 00000001
Select SPI : 1
[2B8h 0696 2] SPI Count : 0040
[2BAh 0698 2] SPI Base : 0050
Raw Table Data: Length 700 (0x2BC)
0000: 41 50 49 43 BC 02 00 00 03 18 42 4F 43 48 53 20 // APIC......BOCHS
0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC
0020: 01 00 00 00 00 00 00 00 00 00 00 00 0C 18 00 00 // ................
0030: 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 // ................
0040: 02 00 00 00 0B 4C 00 00 00 00 00 00 00 00 00 00 // .....L..........
0050: 01 00 00 00 00 00 00 00 17 00 00 00 00 00 00 00 // ................
0060: 00 00 00 00 00 00 01 08 00 00 00 00 00 00 00 00 // ................
0070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0090: 0B 4C 00 00 01 00 00 00 01 00 00 00 01 00 00 00 // .L..............
00A0: 00 00 00 00 17 00 00 00 00 00 00 00 00 00 00 00 // ................
00B0: 00 00 01 08 00 00 00 00 00 00 00 00 00 00 00 00 // ................
00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
00D0: 00 00 00 00 01 00 00 00 00 00 00 00 0B 4C 00 00 // .............L..
00E0: 02 00 00 00 02 00 00 00 01 00 00 00 00 00 00 00 // ................
00F0: 17 00 00 00 00 00 00 00 00 00 00 00 00 00 01 08 // ................
0100: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0110: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0120: 02 00 00 00 00 00 00 00 0B 4C 00 00 03 00 00 00 // .........L......
0130: 03 00 00 00 01 00 00 00 00 00 00 00 17 00 00 00 // ................
0140: 00 00 00 00 00 00 00 00 00 00 01 08 00 00 00 00 // ................
0150: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0160: 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 // ................
0170: 00 00 00 00 0B 4C 00 00 04 00 00 00 04 00 00 00 // .....L..........
0180: 01 00 00 00 00 00 00 00 17 00 00 00 00 00 00 00 // ................
0190: 00 00 00 00 00 00 01 08 00 00 00 00 00 00 00 00 // ................
01A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
01B0: 00 00 00 00 00 00 00 00 04 00 00 00 00 00 00 00 // ................
01C0: 0B 4C 00 00 05 00 00 00 05 00 00 00 01 00 00 00 // .L..............
01D0: 00 00 00 00 17 00 00 00 00 00 00 00 00 00 00 00 // ................
01E0: 00 00 01 08 00 00 00 00 00 00 00 00 00 00 00 00 // ................
01F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0200: 00 00 00 00 05 00 00 00 00 00 00 00 0B 4C 00 00 // .............L..
0210: 06 00 00 00 06 00 00 00 01 00 00 00 00 00 00 00 // ................
0220: 17 00 00 00 00 00 00 00 00 00 00 00 00 00 01 08 // ................
0230: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0240: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0250: 06 00 00 00 00 00 00 00 0B 4C 00 00 07 00 00 00 // .........L......
0260: 07 00 00 00 01 00 00 00 00 00 00 00 17 00 00 00 // ................
0270: 00 00 00 00 00 00 00 00 00 00 01 08 00 00 00 00 // ................
0280: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0290: 00 00 00 00 00 00 00 00 00 00 00 00 07 00 00 00 // ................
02A0: 00 00 00 00 0D 18 00 00 00 00 00 00 00 00 02 08 // ................
02B0: 00 00 00 00 01 00 00 00 40 00 50 00 // ........@.P.
[-- Attachment #4: DSDT.dsl --]
[-- Type: text/plain, Size: 224951 bytes --]
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20160108-64
* Copyright (c) 2000 - 2016 Intel Corporation
*
* Disassembling to symbolic ASL+ operators
*
* Disassembly of DSDT, Tue Jun 18 11:19:52 2019
*
* Original Table Header:
* Signature "DSDT"
* Length 0x000048F6 (18678)
* Revision 0x02
* Checksum 0x6D
* OEM ID "BOCHS "
* OEM Table ID "BXPCDSDT"
* OEM Revision 0x00000001 (1)
* Compiler ID "BXPC"
* Compiler Version 0x00000001 (1)
*/
DefinitionBlock ("DSDT.aml", "DSDT", 2, "BOCHS ", "BXPCDSDT", 0x00000001)
{
Scope (\_SB)
{
Method (CPMA, 1, NotSerialized)
{
Local0 = Buffer (0x50)
{
0x0B, 0x4C, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00 ,
0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x17, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
}
Local0 [0x04] = Arg0
Local0 [0x08] = Arg0
Local0 [0x44] = Arg0
return (Local0)
}
Device (C000)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
}
Device (C001)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, One) // _UID: Unique ID
Method (_STA, 0, NotSerialized) {
Store("hello world1!", Debug)
return (0x0f)
}
}
Device (C002)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x02) // _UID: Unique ID
Method (_STA, 0, NotSerialized) {
Store("hello world2!", Debug)
return (0x0f)
}
}
Device (C003)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x03) // _UID: Unique ID
Method (_STA, 0, NotSerialized) {
Store("hello world3!", Debug)
return (0x0f)
}
}
Device (C004)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x04) // _UID: Unique ID
Method (_MAT, 0, NotSerialized)
{
Return (CPMA(0x04))
}
Method (_STA, 0, NotSerialized) {
Store("hello world4!", Debug)
return (0x00)
}
}
Device (C005)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x05) // _UID: Unique ID
Method (_MAT, 0, NotSerialized)
{
Return (CPMA(0x05))
}
}
Device (C006)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x06) // _UID: Unique ID
Method (_MAT, 0, NotSerialized)
{
Return (CPMA(0x06))
}
Method (_STA, 0, NotSerialized) {
Store("hello world!6", Debug)
Local0 = DerefOf (CPON [0x0])
return (Local0)
}
Method (_SCP, 0, NotSerialized) {
Store("hello world!6 SCP", Debug)
CPON [0x0] = 0x0f
return (0x0)
}
Method (_EJ0, 1, NotSerialized) {
Store("hello world!6 EJ0", Debug)
CPON [0x0] = 0x00
}
}
Device (C007)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x07) // _UID: Unique ID
Method (_MAT, 0, NotSerialized)
{
Return (CPMA(0x07))
}
Method (_STA, 0, NotSerialized) {
Store("hello world7!", Debug)
return (0x0f)
}
}
Name (CPON, Package (0x04)
{
Zero,
Zero,
Zero,
Zero,
})
Device (COM0)
{
Name (_HID, "ARMH0011") // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x09000000, // Address Base
0x00001000, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000021,
}
})
Name (_ADR, 0x09000000) // _ADR: Address
}
Device (FLS0)
{
Name (_HID, "LNRO0015") // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x00000000, // Address Base
0x04000000, // Address Length
)
})
}
Device (FLS1)
{
Name (_HID, "LNRO0015") // _HID: Hardware ID
Name (_UID, One) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x04000000, // Address Base
0x04000000, // Address Length
)
})
}
Device (FWCF)
{
Name (_HID, "QEMU0002") // _HID: Hardware ID
Name (_STA, 0x0B) // _STA: Status
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x09020000, // Address Base
0x00000018, // Address Length
)
})
}
Device (VR00)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A000000, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000030,
}
})
}
Device (VR01)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, One) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A000200, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000031,
}
})
}
Device (VR02)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x02) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A000400, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000032,
}
})
}
Device (VR03)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x03) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A000600, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000033,
}
})
}
Device (VR04)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x04) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A000800, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000034,
}
})
}
Device (VR05)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x05) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A000A00, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000035,
}
})
}
Device (VR06)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x06) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A000C00, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000036,
}
})
}
Device (VR07)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x07) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A000E00, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000037,
}
})
}
Device (VR08)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x08) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A001000, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000038,
}
})
}
Device (VR09)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x09) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A001200, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000039,
}
})
}
Device (VR10)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x0A) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A001400, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x0000003A,
}
})
}
Device (VR11)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x0B) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A001600, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x0000003B,
}
})
}
Device (VR12)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x0C) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A001800, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x0000003C,
}
})
}
Device (VR13)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x0D) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A001A00, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x0000003D,
}
})
}
Device (VR14)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x0E) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A001C00, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x0000003E,
}
})
}
Device (VR15)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x0F) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A001E00, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x0000003F,
}
})
}
Device (VR16)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x10) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A002000, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000040,
}
})
}
Device (VR17)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x11) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A002200, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000041,
}
})
}
Device (VR18)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x12) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A002400, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000042,
}
})
}
Device (VR19)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x13) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A002600, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000043,
}
})
}
Device (VR20)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x14) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A002800, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000044,
}
})
}
Device (VR21)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x15) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A002A00, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000045,
}
})
}
Device (VR22)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x16) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A002C00, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000046,
}
})
}
Device (VR23)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x17) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A002E00, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000047,
}
})
}
Device (VR24)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x18) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A003000, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000048,
}
})
}
Device (VR25)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x19) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A003200, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000049,
}
})
}
Device (VR26)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x1A) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A003400, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x0000004A,
}
})
}
Device (VR27)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x1B) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A003600, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x0000004B,
}
})
}
Device (VR28)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x1C) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A003800, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x0000004C,
}
})
}
Device (VR29)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x1D) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A003A00, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x0000004D,
}
})
}
Device (VR30)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x1E) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A003C00, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x0000004E,
}
})
}
Device (VR31)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x1F) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A003E00, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x0000004F,
}
})
}
Device (PCI0)
{
Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
Name (_SEG, Zero) // _SEG: PCI Segment
Name (_BBN, Zero) // _BBN: BIOS Bus Number
Name (_ADR, Zero) // _ADR: Address
Name (_UID, "PCI0") // _UID: Unique ID
Name (_STR, Unicode ("PCIe 0 Device")) // _STR: Description String
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_PRT, Package (0x0400) // _PRT: PCI Routing Table
{
Package (0x04)
{
0xFFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0xFFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0xFFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0xFFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0001FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0001FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0001FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0001FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x0002FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x0002FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x0002FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x0002FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x0003FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x0003FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x0003FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x0003FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x0004FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x0004FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x0004FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x0004FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0005FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0005FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0005FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0005FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x0006FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x0006FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x0006FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x0006FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x0007FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x0007FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x0007FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x0007FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x0008FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x0008FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x0008FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x0008FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0009FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0009FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0009FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0009FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x000AFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x000AFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x000AFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x000AFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x000BFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x000BFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x000BFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x000BFFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x000CFFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x000CFFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x000CFFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x000CFFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x000DFFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x000DFFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x000DFFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x000DFFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x000EFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x000EFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x000EFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x000EFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x000FFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x000FFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x000FFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x000FFFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x0010FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x0010FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x0010FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x0010FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0011FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0011FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0011FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0011FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x0012FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x0012FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x0012FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x0012FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x0013FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x0013FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x0013FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x0013FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x0014FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x0014FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x0014FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x0014FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0015FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0015FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0015FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0015FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x0016FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x0016FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x0016FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x0016FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x0017FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x0017FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x0017FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x0017FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x0018FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x0018FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x0018FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x0018FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0019FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0019FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0019FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0019FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x001AFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x001AFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x001AFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x001AFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x001BFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x001BFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x001BFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x001BFFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x001CFFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x001CFFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x001CFFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x001CFFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x001DFFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x001DFFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x001DFFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x001DFFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x001EFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x001EFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x001EFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x001EFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x001FFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x001FFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x001FFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x001FFFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x0020FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x0020FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x0020FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x0020FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0021FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0021FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0021FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0021FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x0022FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x0022FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x0022FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x0022FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x0023FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x0023FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x0023FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x0023FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x0024FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x0024FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x0024FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x0024FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0025FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0025FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0025FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0025FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x0026FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x0026FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x0026FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x0026FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x0027FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x0027FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x0027FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x0027FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x0028FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x0028FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x0028FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x0028FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0029FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0029FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0029FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0029FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x002AFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x002AFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x002AFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x002AFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x002BFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x002BFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x002BFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x002BFFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x002CFFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x002CFFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x002CFFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x002CFFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x002DFFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x002DFFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x002DFFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x002DFFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x002EFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x002EFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x002EFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x002EFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x002FFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x002FFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x002FFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x002FFFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x0030FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x0030FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x0030FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x0030FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0031FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0031FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0031FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0031FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x0032FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x0032FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x0032FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x0032FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x0033FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x0033FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x0033FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x0033FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x0034FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x0034FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x0034FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x0034FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0035FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0035FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0035FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0035FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x0036FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x0036FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x0036FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x0036FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x0037FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x0037FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x0037FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x0037FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x0038FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x0038FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x0038FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x0038FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0039FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0039FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0039FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0039FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x003AFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x003AFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x003AFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x003AFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x003BFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x003BFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x003BFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x003BFFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x003CFFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x003CFFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x003CFFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x003CFFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x003DFFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x003DFFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x003DFFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x003DFFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x003EFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x003EFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x003EFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x003EFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x003FFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x003FFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x003FFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x003FFFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x0040FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x0040FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x0040FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x0040FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0041FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0041FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0041FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0041FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x0042FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x0042FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x0042FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x0042FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x0043FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x0043FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x0043FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x0043FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x0044FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x0044FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x0044FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x0044FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0045FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0045FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0045FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0045FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x0046FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x0046FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x0046FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x0046FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x0047FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x0047FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x0047FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x0047FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x0048FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x0048FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x0048FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x0048FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0049FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0049FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0049FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0049FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x004AFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x004AFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x004AFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x004AFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x004BFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x004BFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x004BFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x004BFFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x004CFFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x004CFFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x004CFFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x004CFFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x004DFFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x004DFFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x004DFFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x004DFFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x004EFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x004EFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x004EFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x004EFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x004FFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x004FFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x004FFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x004FFFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x0050FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x0050FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x0050FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x0050FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0051FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0051FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0051FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0051FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x0052FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x0052FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x0052FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x0052FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x0053FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x0053FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x0053FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x0053FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x0054FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x0054FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x0054FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x0054FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0055FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0055FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0055FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0055FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x0056FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x0056FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x0056FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x0056FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x0057FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x0057FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x0057FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x0057FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x0058FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x0058FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x0058FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x0058FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0059FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0059FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0059FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0059FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x005AFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x005AFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x005AFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x005AFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x005BFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x005BFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x005BFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x005BFFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x005CFFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x005CFFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x005CFFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x005CFFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x005DFFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x005DFFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x005DFFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x005DFFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x005EFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x005EFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x005EFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x005EFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x005FFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x005FFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x005FFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x005FFFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x0060FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x0060FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x0060FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x0060FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0061FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0061FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0061FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0061FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x0062FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x0062FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x0062FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x0062FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x0063FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x0063FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x0063FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x0063FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x0064FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x0064FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x0064FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x0064FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0065FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0065FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0065FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0065FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x0066FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x0066FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x0066FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x0066FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x0067FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x0067FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x0067FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x0067FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x0068FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x0068FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x0068FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x0068FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0069FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0069FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0069FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0069FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x006AFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x006AFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x006AFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x006AFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x006BFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x006BFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x006BFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x006BFFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x006CFFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x006CFFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x006CFFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x006CFFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x006DFFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x006DFFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x006DFFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x006DFFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x006EFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x006EFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x006EFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x006EFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x006FFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x006FFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x006FFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x006FFFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x0070FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x0070FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x0070FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x0070FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0071FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0071FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0071FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0071FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x0072FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x0072FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x0072FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x0072FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x0073FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x0073FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x0073FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x0073FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x0074FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x0074FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x0074FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x0074FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0075FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0075FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0075FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0075FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x0076FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x0076FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x0076FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x0076FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x0077FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x0077FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x0077FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x0077FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x0078FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x0078FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x0078FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x0078FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0079FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0079FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0079FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0079FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x007AFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x007AFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x007AFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x007AFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x007BFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x007BFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x007BFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x007BFFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x007CFFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x007CFFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x007CFFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x007CFFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x007DFFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x007DFFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x007DFFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x007DFFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x007EFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x007EFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x007EFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x007EFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x007FFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x007FFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x007FFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x007FFFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x0080FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x0080FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x0080FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x0080FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0081FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0081FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0081FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0081FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x0082FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x0082FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x0082FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x0082FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x0083FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x0083FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x0083FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x0083FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x0084FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x0084FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x0084FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x0084FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0085FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0085FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0085FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0085FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x0086FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x0086FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x0086FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x0086FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x0087FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x0087FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x0087FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x0087FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x0088FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x0088FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x0088FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x0088FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0089FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0089FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0089FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0089FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x008AFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x008AFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x008AFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x008AFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x008BFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x008BFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x008BFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x008BFFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x008CFFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x008CFFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x008CFFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x008CFFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x008DFFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x008DFFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x008DFFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x008DFFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x008EFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x008EFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x008EFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x008EFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x008FFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x008FFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x008FFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x008FFFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x0090FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x0090FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x0090FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x0090FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0091FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0091FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0091FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0091FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x0092FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x0092FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x0092FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x0092FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x0093FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x0093FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x0093FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x0093FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x0094FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x0094FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x0094FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x0094FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0095FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0095FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0095FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0095FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x0096FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x0096FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x0096FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x0096FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x0097FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x0097FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x0097FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x0097FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x0098FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x0098FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x0098FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x0098FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x0099FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x0099FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x0099FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x0099FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x009AFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x009AFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x009AFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x009AFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x009BFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x009BFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x009BFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x009BFFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x009CFFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x009CFFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x009CFFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x009CFFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x009DFFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x009DFFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x009DFFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x009DFFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x009EFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x009EFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x009EFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x009EFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x009FFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x009FFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x009FFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x009FFFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x00A0FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x00A0FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x00A0FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x00A0FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x00A1FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x00A1FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x00A1FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x00A1FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x00A2FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x00A2FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x00A2FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x00A2FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x00A3FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x00A3FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x00A3FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x00A3FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x00A4FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x00A4FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x00A4FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x00A4FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x00A5FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x00A5FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x00A5FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x00A5FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x00A6FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x00A6FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x00A6FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x00A6FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x00A7FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x00A7FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x00A7FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x00A7FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x00A8FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x00A8FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x00A8FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x00A8FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x00A9FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x00A9FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x00A9FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x00A9FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x00AAFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x00AAFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x00AAFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x00AAFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x00ABFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x00ABFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x00ABFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x00ABFFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x00ACFFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x00ACFFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x00ACFFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x00ACFFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x00ADFFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x00ADFFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x00ADFFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x00ADFFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x00AEFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x00AEFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x00AEFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x00AEFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x00AFFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x00AFFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x00AFFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x00AFFFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x00B0FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x00B0FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x00B0FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x00B0FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x00B1FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x00B1FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x00B1FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x00B1FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x00B2FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x00B2FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x00B2FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x00B2FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x00B3FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x00B3FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x00B3FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x00B3FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x00B4FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x00B4FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x00B4FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x00B4FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x00B5FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x00B5FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x00B5FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x00B5FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x00B6FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x00B6FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x00B6FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x00B6FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x00B7FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x00B7FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x00B7FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x00B7FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x00B8FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x00B8FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x00B8FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x00B8FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x00B9FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x00B9FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x00B9FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x00B9FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x00BAFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x00BAFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x00BAFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x00BAFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x00BBFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x00BBFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x00BBFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x00BBFFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x00BCFFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x00BCFFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x00BCFFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x00BCFFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x00BDFFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x00BDFFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x00BDFFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x00BDFFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x00BEFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x00BEFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x00BEFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x00BEFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x00BFFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x00BFFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x00BFFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x00BFFFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x00C0FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x00C0FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x00C0FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x00C0FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x00C1FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x00C1FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x00C1FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x00C1FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x00C2FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x00C2FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x00C2FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x00C2FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x00C3FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x00C3FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x00C3FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x00C3FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x00C4FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x00C4FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x00C4FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x00C4FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x00C5FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x00C5FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x00C5FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x00C5FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x00C6FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x00C6FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x00C6FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x00C6FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x00C7FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x00C7FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x00C7FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x00C7FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x00C8FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x00C8FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x00C8FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x00C8FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x00C9FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x00C9FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x00C9FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x00C9FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x00CAFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x00CAFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x00CAFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x00CAFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x00CBFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x00CBFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x00CBFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x00CBFFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x00CCFFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x00CCFFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x00CCFFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x00CCFFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x00CDFFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x00CDFFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x00CDFFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x00CDFFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x00CEFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x00CEFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x00CEFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x00CEFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x00CFFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x00CFFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x00CFFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x00CFFFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x00D0FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x00D0FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x00D0FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x00D0FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x00D1FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x00D1FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x00D1FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x00D1FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x00D2FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x00D2FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x00D2FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x00D2FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x00D3FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x00D3FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x00D3FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x00D3FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x00D4FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x00D4FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x00D4FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x00D4FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x00D5FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x00D5FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x00D5FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x00D5FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x00D6FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x00D6FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x00D6FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x00D6FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x00D7FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x00D7FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x00D7FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x00D7FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x00D8FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x00D8FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x00D8FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x00D8FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x00D9FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x00D9FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x00D9FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x00D9FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x00DAFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x00DAFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x00DAFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x00DAFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x00DBFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x00DBFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x00DBFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x00DBFFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x00DCFFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x00DCFFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x00DCFFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x00DCFFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x00DDFFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x00DDFFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x00DDFFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x00DDFFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x00DEFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x00DEFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x00DEFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x00DEFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x00DFFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x00DFFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x00DFFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x00DFFFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x00E0FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x00E0FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x00E0FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x00E0FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x00E1FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x00E1FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x00E1FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x00E1FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x00E2FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x00E2FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x00E2FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x00E2FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x00E3FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x00E3FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x00E3FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x00E3FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x00E4FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x00E4FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x00E4FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x00E4FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x00E5FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x00E5FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x00E5FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x00E5FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x00E6FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x00E6FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x00E6FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x00E6FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x00E7FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x00E7FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x00E7FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x00E7FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x00E8FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x00E8FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x00E8FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x00E8FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x00E9FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x00E9FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x00E9FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x00E9FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x00EAFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x00EAFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x00EAFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x00EAFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x00EBFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x00EBFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x00EBFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x00EBFFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x00ECFFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x00ECFFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x00ECFFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x00ECFFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x00EDFFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x00EDFFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x00EDFFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x00EDFFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x00EEFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x00EEFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x00EEFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x00EEFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x00EFFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x00EFFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x00EFFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x00EFFFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x00F0FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x00F0FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x00F0FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x00F0FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x00F1FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x00F1FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x00F1FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x00F1FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x00F2FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x00F2FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x00F2FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x00F2FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x00F3FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x00F3FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x00F3FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x00F3FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x00F4FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x00F4FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x00F4FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x00F4FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x00F5FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x00F5FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x00F5FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x00F5FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x00F6FFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x00F6FFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x00F6FFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x00F6FFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x00F7FFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x00F7FFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x00F7FFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x00F7FFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x00F8FFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x00F8FFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x00F8FFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x00F8FFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x00F9FFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x00F9FFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x00F9FFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x00F9FFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x00FAFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x00FAFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x00FAFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x00FAFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x00FBFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x00FBFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x00FBFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x00FBFFFF,
0x03,
GSI2,
Zero
},
Package (0x04)
{
0x00FCFFFF,
Zero,
GSI0,
Zero
},
Package (0x04)
{
0x00FCFFFF,
One,
GSI1,
Zero
},
Package (0x04)
{
0x00FCFFFF,
0x02,
GSI2,
Zero
},
Package (0x04)
{
0x00FCFFFF,
0x03,
GSI3,
Zero
},
Package (0x04)
{
0x00FDFFFF,
Zero,
GSI1,
Zero
},
Package (0x04)
{
0x00FDFFFF,
One,
GSI2,
Zero
},
Package (0x04)
{
0x00FDFFFF,
0x02,
GSI3,
Zero
},
Package (0x04)
{
0x00FDFFFF,
0x03,
GSI0,
Zero
},
Package (0x04)
{
0x00FEFFFF,
Zero,
GSI2,
Zero
},
Package (0x04)
{
0x00FEFFFF,
One,
GSI3,
Zero
},
Package (0x04)
{
0x00FEFFFF,
0x02,
GSI0,
Zero
},
Package (0x04)
{
0x00FEFFFF,
0x03,
GSI1,
Zero
},
Package (0x04)
{
0x00FFFFFF,
Zero,
GSI3,
Zero
},
Package (0x04)
{
0x00FFFFFF,
One,
GSI0,
Zero
},
Package (0x04)
{
0x00FFFFFF,
0x02,
GSI1,
Zero
},
Package (0x04)
{
0x00FFFFFF,
0x03,
GSI2,
Zero
}
})
Device (GSI0)
{
Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
{
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000023,
}
})
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000023,
}
})
Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
{
}
}
Device (GSI1)
{
Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
{
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000024,
}
})
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000024,
}
})
Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
{
}
}
Device (GSI2)
{
Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
{
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000025,
}
})
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000025,
}
})
Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
{
}
}
Device (GSI3)
{
Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
{
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000026,
}
})
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000026,
}
})
Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
{
}
}
Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address
{
Return (0x0000004010000000)
}
Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
{
Name (RBUF, ResourceTemplate ()
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x00FF, // Range Maximum
0x0000, // Translation Offset
0x0100, // Length
,, )
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x00000000, // Granularity
0x10000000, // Range Minimum
0x3EFEFFFF, // Range Maximum
0x00000000, // Translation Offset
0x2EFF0000, // Length
,, , AddressRangeMemory, TypeStatic)
DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x00000000, // Granularity
0x00000000, // Range Minimum
0x0000FFFF, // Range Maximum
0x3EFF0000, // Translation Offset
0x00010000, // Length
,, , TypeStatic)
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000008000000000, // Range Minimum
0x000000FFFFFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000008000000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
Return (ResourceTemplate ()
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x00FF, // Range Maximum
0x0000, // Translation Offset
0x0100, // Length
,, )
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x00000000, // Granularity
0x10000000, // Range Minimum
0x3EFEFFFF, // Range Maximum
0x00000000, // Translation Offset
0x2EFF0000, // Length
,, , AddressRangeMemory, TypeStatic)
DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x00000000, // Granularity
0x00000000, // Range Minimum
0x0000FFFF, // Range Maximum
0x3EFF0000, // Translation Offset
0x00010000, // Length
,, , TypeStatic)
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000008000000000, // Range Minimum
0x000000FFFFFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000008000000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
}
Name (SUPP, Zero)
Name (CTRL, Zero)
Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
{
CreateDWordField (Arg3, Zero, CDW1)
If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
{
CreateDWordField (Arg3, 0x04, CDW2)
CreateDWordField (Arg3, 0x08, CDW3)
SUPP = CDW2 /* \_SB_.PCI0._OSC.CDW2 */
CTRL = CDW3 /* \_SB_.PCI0._OSC.CDW3 */
CTRL = (CTRL & 0x1D)
If ((Arg1 != One))
{
CDW1 = (CDW1 | 0x08)
}
If ((CDW3 != CTRL))
{
CDW1 = (CDW1 | 0x10)
}
CDW3 = CTRL /* \_SB_.PCI0.CTRL */
Return (Arg3)
}
Else
{
CDW1 = (CDW1 | 0x04)
Return (Arg3)
}
}
Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
{
If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */))
{
If ((Arg2 == Zero))
{
Return (Buffer (One)
{
0x01 /* . */
})
}
}
Return (Buffer (One)
{
0x00 /* . */
})
}
Device (RP0)
{
Name (_ADR, Zero) // _ADR: Address
}
Device (RES0)
{
Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000004010000000, // Range Minimum
0x000000401FFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000010000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
}
}
Device (GPO0)
{
Name (_HID, "ARMH0061") // _HID: Hardware ID
Name (_ADR, Zero) // _ADR: Address
Name (_UID, Zero) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x09030000, // Address Base
0x00001000, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000027,
}
})
Name (_AEI, ResourceTemplate () // _AEI: ACPI Event Interrupts
{
GpioInt (Edge, ActiveHigh, Exclusive, PullUp, 0x0000,
"GPO0", 0x00, ResourceConsumer, ,
)
{ // Pin list
0x0003
}
})
Method (_E03, 0, NotSerialized) // _Exx: Edge-Triggered GPE
{
Notify (PWRB, 0x80) // Status Change
}
}
Device (PWRB)
{
Name (_HID, "PNP0C0C" /* Power Button Device */) // _HID: Hardware ID
Name (_ADR, Zero) // _ADR: Address
Name (_UID, Zero) // _UID: Unique ID
}
}
}
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [RFC PATCH v2 2/3] arm64: mark all the GICC nodes in MADT as possible cpu 2019-06-29 2:42 ` [RFC PATCH v2 2/3] arm64: mark all the GICC nodes in MADT as possible cpu Xiongfeng Wang @ 2019-07-04 6:46 ` Jia He 2019-07-04 8:18 ` Xiongfeng Wang 0 siblings, 1 reply; 15+ messages in thread From: Jia He @ 2019-07-04 6:46 UTC (permalink / raw) To: Xiongfeng Wang, rjw, catalin.marinas, james.morse Cc: linux-acpi, linux-kernel, linux-arm-kernel, guohanjun, xiexiuqi, huawei.libin, john.garry, jonathan.cameron On 2019/6/29 10:42, Xiongfeng Wang wrote: > We set 'cpu_possible_mask' based on the enabled GICC node in MADT. If > the GICC node is disabled, we will skip initializing the kernel data > structure for that CPU. > > To support CPU hotplug, we need to initialize some CPU related data > structure in advance. This patch mark all the GICC nodes as possible CPU > and only these enabled GICC nodes as present CPU. > > Signed-off-by: Xiongfeng Wang <wangxiongfeng2@huawei.com> > --- > arch/arm64/kernel/setup.c | 2 +- > arch/arm64/kernel/smp.c | 11 +++++------ > 2 files changed, 6 insertions(+), 7 deletions(-) > > diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c > index 7e541f9..7f4d12a 100644 > --- a/arch/arm64/kernel/setup.c > +++ b/arch/arm64/kernel/setup.c > @@ -359,7 +359,7 @@ static int __init topology_init(void) > for_each_online_node(i) > register_one_node(i); > > - for_each_possible_cpu(i) { > + for_each_online_cpu(i) { Have you considered the case in non-acpi mode? and setting "maxcpus=n" in host kernel boot parameters? --- Cheers, Justin (Jia He) > struct cpu *cpu = &per_cpu(cpu_data.cpu, i); > cpu->hotpluggable = 1; > register_cpu(cpu, i); > diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c > index 6dcf960..6d9983c 100644 > --- a/arch/arm64/kernel/smp.c > +++ b/arch/arm64/kernel/smp.c > @@ -525,16 +525,14 @@ struct acpi_madt_generic_interrupt *acpi_cpu_get_madt_gicc(int cpu) > { > u64 hwid = processor->arm_mpidr; > > - if (!(processor->flags & ACPI_MADT_ENABLED)) { > - pr_debug("skipping disabled CPU entry with 0x%llx MPIDR\n", hwid); > - return; > - } > - > if (hwid & ~MPIDR_HWID_BITMASK || hwid == INVALID_HWID) { > pr_err("skipping CPU entry with invalid MPIDR 0x%llx\n", hwid); > return; > } > > + if (!(processor->flags & ACPI_MADT_ENABLED)) > + pr_debug("disabled CPU entry with 0x%llx MPIDR\n", hwid); > + > if (is_mpidr_duplicate(cpu_count, hwid)) { > pr_err("duplicate CPU MPIDR 0x%llx in MADT\n", hwid); > return; > @@ -755,7 +753,8 @@ void __init smp_prepare_cpus(unsigned int max_cpus) > if (err) > continue; > > - set_cpu_present(cpu, true); > + if ((cpu_madt_gicc[cpu].flags & ACPI_MADT_ENABLED)) > + set_cpu_present(cpu, true); > numa_store_cpu_info(cpu); > } > } -- ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [RFC PATCH v2 2/3] arm64: mark all the GICC nodes in MADT as possible cpu 2019-07-04 6:46 ` Jia He @ 2019-07-04 8:18 ` Xiongfeng Wang 0 siblings, 0 replies; 15+ messages in thread From: Xiongfeng Wang @ 2019-07-04 8:18 UTC (permalink / raw) To: Jia He, rjw, catalin.marinas, james.morse Cc: linux-acpi, linux-kernel, linux-arm-kernel, guohanjun, xiexiuqi, huawei.libin, john.garry, jonathan.cameron On 2019/7/4 14:46, Jia He wrote: > > On 2019/6/29 10:42, Xiongfeng Wang wrote: >> We set 'cpu_possible_mask' based on the enabled GICC node in MADT. If >> the GICC node is disabled, we will skip initializing the kernel data >> structure for that CPU. >> >> To support CPU hotplug, we need to initialize some CPU related data >> structure in advance. This patch mark all the GICC nodes as possible CPU >> and only these enabled GICC nodes as present CPU. >> >> Signed-off-by: Xiongfeng Wang <wangxiongfeng2@huawei.com> >> --- >> arch/arm64/kernel/setup.c | 2 +- >> arch/arm64/kernel/smp.c | 11 +++++------ >> 2 files changed, 6 insertions(+), 7 deletions(-) >> >> diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c >> index 7e541f9..7f4d12a 100644 >> --- a/arch/arm64/kernel/setup.c >> +++ b/arch/arm64/kernel/setup.c >> @@ -359,7 +359,7 @@ static int __init topology_init(void) >> for_each_online_node(i) >> register_one_node(i); >> - for_each_possible_cpu(i) { >> + for_each_online_cpu(i) { > > Have you considered the case in non-acpi mode? and setting "maxcpus=n" in host kernel boot > > parameters? Thanks for your mention. I haven't considered non-acpi mode. I should add ACPI check in 'smp_prepare_cpus()'. 'maxcpus' is check when we actually online the CPU, so I think it is not influenced. Thanks, Xiongfeng > > --- > Cheers, > Justin (Jia He) > > >> struct cpu *cpu = &per_cpu(cpu_data.cpu, i); >> cpu->hotpluggable = 1; >> register_cpu(cpu, i); >> diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c >> index 6dcf960..6d9983c 100644 >> --- a/arch/arm64/kernel/smp.c >> +++ b/arch/arm64/kernel/smp.c >> @@ -525,16 +525,14 @@ struct acpi_madt_generic_interrupt *acpi_cpu_get_madt_gicc(int cpu) >> { >> u64 hwid = processor->arm_mpidr; >> - if (!(processor->flags & ACPI_MADT_ENABLED)) { >> - pr_debug("skipping disabled CPU entry with 0x%llx MPIDR\n", hwid); >> - return; >> - } >> - >> if (hwid & ~MPIDR_HWID_BITMASK || hwid == INVALID_HWID) { >> pr_err("skipping CPU entry with invalid MPIDR 0x%llx\n", hwid); >> return; >> } >> + if (!(processor->flags & ACPI_MADT_ENABLED)) >> + pr_debug("disabled CPU entry with 0x%llx MPIDR\n", hwid); >> + >> if (is_mpidr_duplicate(cpu_count, hwid)) { >> pr_err("duplicate CPU MPIDR 0x%llx in MADT\n", hwid); >> return; >> @@ -755,7 +753,8 @@ void __init smp_prepare_cpus(unsigned int max_cpus) >> if (err) >> continue; >> - set_cpu_present(cpu, true); >> + if ((cpu_madt_gicc[cpu].flags & ACPI_MADT_ENABLED)) >> + set_cpu_present(cpu, true); >> numa_store_cpu_info(cpu); >> } >> } > ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [RFC PATCH v2 0/3] Support CPU hotplug for ARM64
2019-06-29 2:42 [RFC PATCH v2 0/3] Support CPU hotplug for ARM64 Xiongfeng Wang
` (3 preceding siblings ...)
2019-06-29 3:23 ` [RFC PATCH v2 0/3] Support CPU hotplug for ARM64 Xiongfeng Wang
@ 2019-07-05 10:12 ` James Morse
2019-07-09 19:06 ` Maran Wilson
2019-07-16 7:52 ` Xiongfeng Wang
4 siblings, 2 replies; 15+ messages in thread
From: James Morse @ 2019-07-05 10:12 UTC (permalink / raw)
To: Xiongfeng Wang
Cc: rjw, linux-acpi, linux-kernel, linux-arm-kernel, guohanjun,
xiexiuqi, huawei.libin, john.garry, jonathan.cameron, kvmarm
Hi guys,
(CC: +kvmarm list)
On 29/06/2019 03:42, Xiongfeng Wang wrote:
> This patchset mark all the GICC node in MADT as possible CPUs even though it
> is disabled. But only those enabled GICC node are marked as present CPUs.
> So that kernel will initialize some CPU related data structure in advance before
> the CPU is actually hot added into the system. This patchset also implement
> 'acpi_(un)map_cpu()' and 'arch_(un)register_cpu()' for ARM64. These functions are
> needed to enable CPU hotplug.
>
> To support CPU hotplug, we need to add all the possible GICC node in MADT
> including those CPUs that are not present but may be hot added later. Those
> CPUs are marked as disabled in GICC nodes.
... what do you need this for?
(The term cpu-hotplug in the arm world almost never means hot-adding a new package/die to
the platform, we usually mean taking CPUs online/offline for power management. e.g.
cpuhp_offline_cpu_device())
It looks like you're adding support for hot-adding a new package/die to the platform ...
but only for virtualisation.
I don't see why this is needed for virtualisation. The in-kernel irqchip needs to know
these vcpu exist before you can enter the guest for the first time. You can't create them
late. At best you're saving the host scheduling a vcpu that is offline. Is this really a
problem?
If we moved PSCI support to user-space, you could avoid creating host vcpu threads until
the guest brings the vcpu online, which would solve that problem, and save the host
resources for the thread too. (and its acpi/dt agnostic)
I don't see the difference here between booting the guest with 'maxcpus=1', and bringing
the vcpu online later. The only real difference seems to be moving the can-be-online
policy into the hypervisor/VMM...
I think physical package/die hotadd is a much bigger, uglier problem than doing the same
under virtualisation. Its best to do this on real hardware first so we don't miss
something. (cpu-topology, numa, memory, errata, timers?)
I'm worried that doing virtualisation first means the firmware-requirements for physical
hotadd stuff is "whatever Qemu does".
Thanks,
James
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [RFC PATCH v2 0/3] Support CPU hotplug for ARM64 2019-07-05 10:12 ` James Morse @ 2019-07-09 19:06 ` Maran Wilson 2019-07-10 9:15 ` Marc Zyngier 2019-07-16 7:52 ` Xiongfeng Wang 1 sibling, 1 reply; 15+ messages in thread From: Maran Wilson @ 2019-07-09 19:06 UTC (permalink / raw) To: James Morse, Xiongfeng Wang Cc: jonathan.cameron, john.garry, rjw, linux-kernel, linux-acpi, huawei.libin, guohanjun, kvmarm, linux-arm-kernel On 7/5/2019 3:12 AM, James Morse wrote: > Hi guys, > > (CC: +kvmarm list) > > On 29/06/2019 03:42, Xiongfeng Wang wrote: >> This patchset mark all the GICC node in MADT as possible CPUs even though it >> is disabled. But only those enabled GICC node are marked as present CPUs. >> So that kernel will initialize some CPU related data structure in advance before >> the CPU is actually hot added into the system. This patchset also implement >> 'acpi_(un)map_cpu()' and 'arch_(un)register_cpu()' for ARM64. These functions are >> needed to enable CPU hotplug. >> >> To support CPU hotplug, we need to add all the possible GICC node in MADT >> including those CPUs that are not present but may be hot added later. Those >> CPUs are marked as disabled in GICC nodes. > ... what do you need this for? > > (The term cpu-hotplug in the arm world almost never means hot-adding a new package/die to > the platform, we usually mean taking CPUs online/offline for power management. e.g. > cpuhp_offline_cpu_device()) > > It looks like you're adding support for hot-adding a new package/die to the platform ... > but only for virtualisation. > > I don't see why this is needed for virtualisation. The in-kernel irqchip needs to know > these vcpu exist before you can enter the guest for the first time. You can't create them > late. At best you're saving the host scheduling a vcpu that is offline. Is this really a > problem? > > If we moved PSCI support to user-space, you could avoid creating host vcpu threads until > the guest brings the vcpu online, which would solve that problem, and save the host > resources for the thread too. (and its acpi/dt agnostic) > > I don't see the difference here between booting the guest with 'maxcpus=1', and bringing > the vcpu online later. The only real difference seems to be moving the can-be-online > policy into the hypervisor/VMM... Isn't that an important distinction from a cloud service provider's perspective? As far as I understand it, you also need CPU hotplug capabilities to support things like Kata runtime under Kubernetes. i.e. when implementing your containers in the form of light weight VMs for the additional security ... and the orchestration layer cannot determine ahead of time how much CPU/memory resources are going to be needed to run the pod(s). Thanks, -Maran > > I think physical package/die hotadd is a much bigger, uglier problem than doing the same > under virtualisation. Its best to do this on real hardware first so we don't miss > something. (cpu-topology, numa, memory, errata, timers?) > I'm worried that doing virtualisation first means the firmware-requirements for physical > hotadd stuff is "whatever Qemu does". > > > Thanks, > > James > _______________________________________________ > kvmarm mailing list > kvmarm@lists.cs.columbia.edu > https://lists.cs.columbia.edu/mailman/listinfo/kvmarm ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [RFC PATCH v2 0/3] Support CPU hotplug for ARM64 2019-07-09 19:06 ` Maran Wilson @ 2019-07-10 9:15 ` Marc Zyngier 2019-07-10 16:05 ` Maran Wilson 2019-07-16 7:59 ` Jia He 0 siblings, 2 replies; 15+ messages in thread From: Marc Zyngier @ 2019-07-10 9:15 UTC (permalink / raw) To: Maran Wilson, James Morse, Xiongfeng Wang Cc: guohanjun, john.garry, rjw, linux-kernel, linux-acpi, huawei.libin, jonathan.cameron, kvmarm, linux-arm-kernel On 09/07/2019 20:06, Maran Wilson wrote: > On 7/5/2019 3:12 AM, James Morse wrote: >> Hi guys, >> >> (CC: +kvmarm list) >> >> On 29/06/2019 03:42, Xiongfeng Wang wrote: >>> This patchset mark all the GICC node in MADT as possible CPUs even though it >>> is disabled. But only those enabled GICC node are marked as present CPUs. >>> So that kernel will initialize some CPU related data structure in advance before >>> the CPU is actually hot added into the system. This patchset also implement >>> 'acpi_(un)map_cpu()' and 'arch_(un)register_cpu()' for ARM64. These functions are >>> needed to enable CPU hotplug. >>> >>> To support CPU hotplug, we need to add all the possible GICC node in MADT >>> including those CPUs that are not present but may be hot added later. Those >>> CPUs are marked as disabled in GICC nodes. >> ... what do you need this for? >> >> (The term cpu-hotplug in the arm world almost never means hot-adding a new package/die to >> the platform, we usually mean taking CPUs online/offline for power management. e.g. >> cpuhp_offline_cpu_device()) >> >> It looks like you're adding support for hot-adding a new package/die to the platform ... >> but only for virtualisation. >> >> I don't see why this is needed for virtualisation. The in-kernel irqchip needs to know >> these vcpu exist before you can enter the guest for the first time. You can't create them >> late. At best you're saving the host scheduling a vcpu that is offline. Is this really a >> problem? >> >> If we moved PSCI support to user-space, you could avoid creating host vcpu threads until >> the guest brings the vcpu online, which would solve that problem, and save the host >> resources for the thread too. (and its acpi/dt agnostic) >> >> I don't see the difference here between booting the guest with 'maxcpus=1', and bringing >> the vcpu online later. The only real difference seems to be moving the can-be-online >> policy into the hypervisor/VMM... > > Isn't that an important distinction from a cloud service provider's > perspective? > > As far as I understand it, you also need CPU hotplug capabilities to > support things like Kata runtime under Kubernetes. i.e. when > implementing your containers in the form of light weight VMs for the > additional security ... and the orchestration layer cannot determine > ahead of time how much CPU/memory resources are going to be needed to > run the pod(s). Why would it be any different? You can pre-allocate your vcpus, leave them parked until some external agent decides to signal the container that it it can use another bunch of CPUs. At that point, the container must actively boot these vcpus (they aren't going to come up by magic). Given that you must have sized your virtual platform to deal with the maximum set of resources you anticipate (think of the GIC redistributors, for example), I really wonder what you gain here. > > Thanks, > -Maran > >> >> I think physical package/die hotadd is a much bigger, uglier problem than doing the same >> under virtualisation. Its best to do this on real hardware first so we don't miss >> something. (cpu-topology, numa, memory, errata, timers?) >> I'm worried that doing virtualisation first means the firmware-requirements for physical >> hotadd stuff is "whatever Qemu does". For sure, I want to model the virtualization side after the actual HW, and not the other way around. Live reconfiguration of the interrupt topology (and thus the whole memory map) will certainly be challenging. Thanks, M. -- Jazz is not dead. It just smells funny... ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [RFC PATCH v2 0/3] Support CPU hotplug for ARM64 2019-07-10 9:15 ` Marc Zyngier @ 2019-07-10 16:05 ` Maran Wilson 2019-07-15 13:43 ` James Morse 2019-07-16 7:59 ` Jia He 1 sibling, 1 reply; 15+ messages in thread From: Maran Wilson @ 2019-07-10 16:05 UTC (permalink / raw) To: Marc Zyngier, James Morse, Xiongfeng Wang Cc: guohanjun, john.garry, rjw, linux-kernel, linux-acpi, huawei.libin, jonathan.cameron, kvmarm, linux-arm-kernel On 7/10/2019 2:15 AM, Marc Zyngier wrote: > On 09/07/2019 20:06, Maran Wilson wrote: >> On 7/5/2019 3:12 AM, James Morse wrote: >>> Hi guys, >>> >>> (CC: +kvmarm list) >>> >>> On 29/06/2019 03:42, Xiongfeng Wang wrote: >>>> This patchset mark all the GICC node in MADT as possible CPUs even though it >>>> is disabled. But only those enabled GICC node are marked as present CPUs. >>>> So that kernel will initialize some CPU related data structure in advance before >>>> the CPU is actually hot added into the system. This patchset also implement >>>> 'acpi_(un)map_cpu()' and 'arch_(un)register_cpu()' for ARM64. These functions are >>>> needed to enable CPU hotplug. >>>> >>>> To support CPU hotplug, we need to add all the possible GICC node in MADT >>>> including those CPUs that are not present but may be hot added later. Those >>>> CPUs are marked as disabled in GICC nodes. >>> ... what do you need this for? >>> >>> (The term cpu-hotplug in the arm world almost never means hot-adding a new package/die to >>> the platform, we usually mean taking CPUs online/offline for power management. e.g. >>> cpuhp_offline_cpu_device()) >>> >>> It looks like you're adding support for hot-adding a new package/die to the platform ... >>> but only for virtualisation. >>> >>> I don't see why this is needed for virtualisation. The in-kernel irqchip needs to know >>> these vcpu exist before you can enter the guest for the first time. You can't create them >>> late. At best you're saving the host scheduling a vcpu that is offline. Is this really a >>> problem? >>> >>> If we moved PSCI support to user-space, you could avoid creating host vcpu threads until >>> the guest brings the vcpu online, which would solve that problem, and save the host >>> resources for the thread too. (and its acpi/dt agnostic) >>> >>> I don't see the difference here between booting the guest with 'maxcpus=1', and bringing >>> the vcpu online later. The only real difference seems to be moving the can-be-online >>> policy into the hypervisor/VMM... >> Isn't that an important distinction from a cloud service provider's >> perspective? >> >> As far as I understand it, you also need CPU hotplug capabilities to >> support things like Kata runtime under Kubernetes. i.e. when >> implementing your containers in the form of light weight VMs for the >> additional security ... and the orchestration layer cannot determine >> ahead of time how much CPU/memory resources are going to be needed to >> run the pod(s). > Why would it be any different? You can pre-allocate your vcpus, leave > them parked until some external agent decides to signal the container > that it it can use another bunch of CPUs. At that point, the container > must actively boot these vcpus (they aren't going to come up by magic). > > Given that you must have sized your virtual platform to deal with the > maximum set of resources you anticipate (think of the GIC > redistributors, for example), I really wonder what you gain here. Maybe I'm not following the alternative proposal completely, but wouldn't a guest VM (who happens to be in control of its OS) be able to add/online vCPU resources without approval from the VMM this way? Thanks, -Maran >> Thanks, >> -Maran >> >>> I think physical package/die hotadd is a much bigger, uglier problem than doing the same >>> under virtualisation. Its best to do this on real hardware first so we don't miss >>> something. (cpu-topology, numa, memory, errata, timers?) >>> I'm worried that doing virtualisation first means the firmware-requirements for physical >>> hotadd stuff is "whatever Qemu does". > For sure, I want to model the virtualization side after the actual HW, > and not the other way around. Live reconfiguration of the interrupt > topology (and thus the whole memory map) will certainly be challenging. > > Thanks, > > M. ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [RFC PATCH v2 0/3] Support CPU hotplug for ARM64 2019-07-10 16:05 ` Maran Wilson @ 2019-07-15 13:43 ` James Morse 0 siblings, 0 replies; 15+ messages in thread From: James Morse @ 2019-07-15 13:43 UTC (permalink / raw) To: Maran Wilson Cc: Marc Zyngier, Xiongfeng Wang, guohanjun, john.garry, rjw, linux-kernel, linux-acpi, huawei.libin, jonathan.cameron, kvmarm, linux-arm-kernel Hi Maran, On 10/07/2019 17:05, Maran Wilson wrote: > On 7/10/2019 2:15 AM, Marc Zyngier wrote: >> On 09/07/2019 20:06, Maran Wilson wrote: >>> On 7/5/2019 3:12 AM, James Morse wrote: >>>> On 29/06/2019 03:42, Xiongfeng Wang wrote: >>>>> This patchset mark all the GICC node in MADT as possible CPUs even though it >>>>> is disabled. But only those enabled GICC node are marked as present CPUs. >>>>> So that kernel will initialize some CPU related data structure in advance before >>>>> the CPU is actually hot added into the system. This patchset also implement >>>>> 'acpi_(un)map_cpu()' and 'arch_(un)register_cpu()' for ARM64. These functions are >>>>> needed to enable CPU hotplug. >>>>> >>>>> To support CPU hotplug, we need to add all the possible GICC node in MADT >>>>> including those CPUs that are not present but may be hot added later. Those >>>>> CPUs are marked as disabled in GICC nodes. >>>> ... what do you need this for? >>>> >>>> (The term cpu-hotplug in the arm world almost never means hot-adding a new package/die to >>>> the platform, we usually mean taking CPUs online/offline for power management. e.g. >>>> cpuhp_offline_cpu_device()) >>>> >>>> It looks like you're adding support for hot-adding a new package/die to the platform ... >>>> but only for virtualisation. >>>> >>>> I don't see why this is needed for virtualisation. The in-kernel irqchip needs to know >>>> these vcpu exist before you can enter the guest for the first time. You can't create them >>>> late. At best you're saving the host scheduling a vcpu that is offline. Is this really a >>>> problem? >>>> >>>> If we moved PSCI support to user-space, you could avoid creating host vcpu threads until >>>> the guest brings the vcpu online, which would solve that problem, and save the host >>>> resources for the thread too. (and its acpi/dt agnostic) >>>> >>>> I don't see the difference here between booting the guest with 'maxcpus=1', and bringing >>>> the vcpu online later. The only real difference seems to be moving the can-be-online >>>> policy into the hypervisor/VMM... >>> Isn't that an important distinction from a cloud service provider's >>> perspective? Host cpu-time is. Describing this as guest vcpu's is a bit weird. I'd expect the statement be something like "you're paying for 50% of one Xeon v-whatever". It shouldn't make a difference if I run 8 vcpus or 2, the amount of cpu-time would still be constrained by the cloud provider. >>> As far as I understand it, you also need CPU hotplug capabilities to >>> support things like Kata runtime under Kubernetes. i.e. when >>> implementing your containers in the form of light weight VMs for the >>> additional security ... and the orchestration layer cannot determine >>> ahead of time how much CPU/memory resources are going to be needed to >>> run the pod(s). >> Why would it be any different? You can pre-allocate your vcpus, leave >> them parked until some external agent decides to signal the container >> that it it can use another bunch of CPUs. At that point, the container >> must actively boot these vcpus (they aren't going to come up by magic). >> >> Given that you must have sized your virtual platform to deal with the >> maximum set of resources you anticipate (think of the GIC >> redistributors, for example), I really wonder what you gain here. > Maybe I'm not following the alternative proposal completely, but wouldn't a guest VM (who > happens to be in control of its OS) be able to add/online vCPU resources without approval > from the VMM this way? The in-kernel PSCI implementation will allow all CPUs to be online/offline. If we moved that support to the VMM, it could apply some policy as to whether a cpu-online call succeeds or fails. Thanks, James ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [RFC PATCH v2 0/3] Support CPU hotplug for ARM64 2019-07-05 10:12 ` James Morse 2019-07-09 19:06 ` Maran Wilson @ 2019-07-16 7:52 ` Xiongfeng Wang 1 sibling, 0 replies; 15+ messages in thread From: Xiongfeng Wang @ 2019-07-16 7:52 UTC (permalink / raw) To: James Morse Cc: rjw, linux-acpi, linux-kernel, linux-arm-kernel, guohanjun, xiexiuqi, huawei.libin, john.garry, jonathan.cameron, kvmarm On 2019/7/5 18:12, James Morse wrote: > Hi guys, > > (CC: +kvmarm list) > > On 29/06/2019 03:42, Xiongfeng Wang wrote: >> This patchset mark all the GICC node in MADT as possible CPUs even though it >> is disabled. But only those enabled GICC node are marked as present CPUs. >> So that kernel will initialize some CPU related data structure in advance before >> the CPU is actually hot added into the system. This patchset also implement >> 'acpi_(un)map_cpu()' and 'arch_(un)register_cpu()' for ARM64. These functions are >> needed to enable CPU hotplug. >> >> To support CPU hotplug, we need to add all the possible GICC node in MADT >> including those CPUs that are not present but may be hot added later. Those >> CPUs are marked as disabled in GICC nodes. > > ... what do you need this for? > > (The term cpu-hotplug in the arm world almost never means hot-adding a new package/die to > the platform, we usually mean taking CPUs online/offline for power management. e.g. > cpuhp_offline_cpu_device()) > > It looks like you're adding support for hot-adding a new package/die to the platform ... > but only for virtualisation. I read the GIC driver these days. It is a lot of work to configure the GIC at runtime, and this patchset doesn't support this. Actually, my original idea is hot-adding cores to the platform, and it is only for virtualisation. These cores need to be on the same physical package. The GIC is initialized when the kernel boots and GICR is initialized when the core is hot-added and brought up. > > I don't see why this is needed for virtualisation. The in-kernel irqchip needs to know > these vcpu exist before you can enter the guest for the first time. You can't create them > late. At best you're saving the host scheduling a vcpu that is offline. Is this really a > problem? > > If we moved PSCI support to user-space, you could avoid creating host vcpu threads until > the guest brings the vcpu online, which would solve that problem, and save the host > resources for the thread too. (and its acpi/dt agnostic) > > I don't see the difference here between booting the guest with 'maxcpus=1', and bringing > the vcpu online later. The only real difference seems to be moving the can-be-online > policy into the hypervisor/VMM... > > > I think physical package/die hotadd is a much bigger, uglier problem than doing the same > under virtualisation. Its best to do this on real hardware first so we don't miss > something. (cpu-topology, numa, memory, errata, timers?) > I'm worried that doing virtualisation first means the firmware-requirements for physical > hotadd stuff is "whatever Qemu does". > > > Thanks, > > James > > . > ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [RFC PATCH v2 0/3] Support CPU hotplug for ARM64
2019-07-10 9:15 ` Marc Zyngier
2019-07-10 16:05 ` Maran Wilson
@ 2019-07-16 7:59 ` Jia He
2019-07-16 8:32 ` Marc Zyngier
1 sibling, 1 reply; 15+ messages in thread
From: Jia He @ 2019-07-16 7:59 UTC (permalink / raw)
To: Marc Zyngier, Maran Wilson, James Morse, Xiongfeng Wang
Cc: jonathan.cameron, john.garry, rjw, linux-kernel, linux-acpi,
huawei.libin, guohanjun, kvmarm, linux-arm-kernel
Hi Marc
On 2019/7/10 17:15, Marc Zyngier wrote:
> On 09/07/2019 20:06, Maran Wilson wrote:
>> On 7/5/2019 3:12 AM, James Morse wrote:
>>> Hi guys,
>>>
>>> (CC: +kvmarm list)
>>>
>>> On 29/06/2019 03:42, Xiongfeng Wang wrote:
>>>> This patchset mark all the GICC node in MADT as possible CPUs even though it
>>>> is disabled. But only those enabled GICC node are marked as present CPUs.
>>>> So that kernel will initialize some CPU related data structure in advance before
>>>> the CPU is actually hot added into the system. This patchset also implement
>>>> 'acpi_(un)map_cpu()' and 'arch_(un)register_cpu()' for ARM64. These functions are
>>>> needed to enable CPU hotplug.
>>>>
>>>> To support CPU hotplug, we need to add all the possible GICC node in MADT
>>>> including those CPUs that are not present but may be hot added later. Those
>>>> CPUs are marked as disabled in GICC nodes.
>>> ... what do you need this for?
>>>
>>> (The term cpu-hotplug in the arm world almost never means hot-adding a new package/die to
>>> the platform, we usually mean taking CPUs online/offline for power management. e.g.
>>> cpuhp_offline_cpu_device())
>>>
>>> It looks like you're adding support for hot-adding a new package/die to the platform ...
>>> but only for virtualisation.
>>>
>>> I don't see why this is needed for virtualisation. The in-kernel irqchip needs to know
>>> these vcpu exist before you can enter the guest for the first time. You can't create them
>>> late. At best you're saving the host scheduling a vcpu that is offline. Is this really a
>>> problem?
>>>
>>> If we moved PSCI support to user-space, you could avoid creating host vcpu threads until
>>> the guest brings the vcpu online, which would solve that problem, and save the host
>>> resources for the thread too. (and its acpi/dt agnostic)
>>>
>>> I don't see the difference here between booting the guest with 'maxcpus=1', and bringing
>>> the vcpu online later. The only real difference seems to be moving the can-be-online
>>> policy into the hypervisor/VMM...
>> Isn't that an important distinction from a cloud service provider's
>> perspective?
>>
>> As far as I understand it, you also need CPU hotplug capabilities to
>> support things like Kata runtime under Kubernetes. i.e. when
>> implementing your containers in the form of light weight VMs for the
>> additional security ... and the orchestration layer cannot determine
>> ahead of time how much CPU/memory resources are going to be needed to
>> run the pod(s).
> Why would it be any different? You can pre-allocate your vcpus, leave
> them parked until some external agent decides to signal the container
> that it it can use another bunch of CPUs. At that point, the container
> must actively boot these vcpus (they aren't going to come up by magic).
>
> Given that you must have sized your virtual platform to deal with the
> maximum set of resources you anticipate (think of the GIC
> redistributors, for example), I really wonder what you gain here.
I agree with your point in GIC aspect. It will mess up things if it makes
GIC resource hotpluggable in qemu. But it also would be better that vmm
only startup limited vcpu thread resource.
How about:
1. qemu only starts only N vcpu thread (-smp N, maxcpus=M)
2. qemu reserves the GIC resource with maxium M vcpu number
3. when qmp cmd cpu hotplug-add is triggerred, send a GED event to guest kernel
4. guest kernel recv it and trigger the acpi plug process.
Currently ACPI_CPU_HOTPLUG is enabled for Kconfig but completely not workable.
---
Cheers,
Jia
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [RFC PATCH v2 0/3] Support CPU hotplug for ARM64 2019-07-16 7:59 ` Jia He @ 2019-07-16 8:32 ` Marc Zyngier 0 siblings, 0 replies; 15+ messages in thread From: Marc Zyngier @ 2019-07-16 8:32 UTC (permalink / raw) To: Jia He, Maran Wilson, James Morse, Xiongfeng Wang Cc: jonathan.cameron, john.garry, rjw, linux-kernel, linux-acpi, huawei.libin, guohanjun, kvmarm, linux-arm-kernel Hi Jia, On 16/07/2019 08:59, Jia He wrote: > Hi Marc > > On 2019/7/10 17:15, Marc Zyngier wrote: >> On 09/07/2019 20:06, Maran Wilson wrote: >>> On 7/5/2019 3:12 AM, James Morse wrote: >>>> Hi guys, >>>> >>>> (CC: +kvmarm list) >>>> >>>> On 29/06/2019 03:42, Xiongfeng Wang wrote: >>>>> This patchset mark all the GICC node in MADT as possible CPUs even though it >>>>> is disabled. But only those enabled GICC node are marked as present CPUs. >>>>> So that kernel will initialize some CPU related data structure in advance before >>>>> the CPU is actually hot added into the system. This patchset also implement >>>>> 'acpi_(un)map_cpu()' and 'arch_(un)register_cpu()' for ARM64. These functions are >>>>> needed to enable CPU hotplug. >>>>> >>>>> To support CPU hotplug, we need to add all the possible GICC node in MADT >>>>> including those CPUs that are not present but may be hot added later. Those >>>>> CPUs are marked as disabled in GICC nodes. >>>> ... what do you need this for? >>>> >>>> (The term cpu-hotplug in the arm world almost never means hot-adding a new package/die to >>>> the platform, we usually mean taking CPUs online/offline for power management. e.g. >>>> cpuhp_offline_cpu_device()) >>>> >>>> It looks like you're adding support for hot-adding a new package/die to the platform ... >>>> but only for virtualisation. >>>> >>>> I don't see why this is needed for virtualisation. The in-kernel irqchip needs to know >>>> these vcpu exist before you can enter the guest for the first time. You can't create them >>>> late. At best you're saving the host scheduling a vcpu that is offline. Is this really a >>>> problem? >>>> >>>> If we moved PSCI support to user-space, you could avoid creating host vcpu threads until >>>> the guest brings the vcpu online, which would solve that problem, and save the host >>>> resources for the thread too. (and its acpi/dt agnostic) >>>> >>>> I don't see the difference here between booting the guest with 'maxcpus=1', and bringing >>>> the vcpu online later. The only real difference seems to be moving the can-be-online >>>> policy into the hypervisor/VMM... >>> Isn't that an important distinction from a cloud service provider's >>> perspective? >>> >>> As far as I understand it, you also need CPU hotplug capabilities to >>> support things like Kata runtime under Kubernetes. i.e. when >>> implementing your containers in the form of light weight VMs for the >>> additional security ... and the orchestration layer cannot determine >>> ahead of time how much CPU/memory resources are going to be needed to >>> run the pod(s). >> Why would it be any different? You can pre-allocate your vcpus, leave >> them parked until some external agent decides to signal the container >> that it it can use another bunch of CPUs. At that point, the container >> must actively boot these vcpus (they aren't going to come up by magic). >> >> Given that you must have sized your virtual platform to deal with the >> maximum set of resources you anticipate (think of the GIC >> redistributors, for example), I really wonder what you gain here. > I agree with your point in GIC aspect. It will mess up things if it makes > > GIC resource hotpluggable in qemu. It is far worse than just a mess. You'd need to come up with a way to place your redistributors in memory, and tell the running guest where these redistributors are. Currently, there is no method to describe such changes to the address space, and I certainly don't want QEMU to invent one. This needs to be modeled after what would happen on real HW. > But it also would be better that vmm > > only startup limited vcpu thread resource. > > How about: > > 1. qemu only starts only N vcpu thread (-smp N, maxcpus=M) > > 2. qemu reserves the GIC resource with maxium M vcpu number Note that this implies actually initializing M vcpus in the VM. You may not have created the corresponding (M - N) threads, but the vcpus will exist. Can you please quantify how much you'd save by doing that? > 3. when qmp cmd cpu hotplug-add is triggerred, send a GED event to guest kernel > > 4. guest kernel recv it and trigger the acpi plug process. > > Currently ACPI_CPU_HOTPLUG is enabled for Kconfig but completely not workable. Well, there so far *zero* CPU_HOTPLUG in the arm64 kernel other than getting CPUs in and out of PSCI. Thanks, M. -- Jazz is not dead. It just smells funny... ^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2019-07-16 8:32 UTC | newest] Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-06-29 2:42 [RFC PATCH v2 0/3] Support CPU hotplug for ARM64 Xiongfeng Wang 2019-06-29 2:42 ` [RFC PATCH v2 1/3] ACPI / scan: evaluate _STA for processors declared via ASL Device statement Xiongfeng Wang 2019-06-29 2:42 ` [RFC PATCH v2 2/3] arm64: mark all the GICC nodes in MADT as possible cpu Xiongfeng Wang 2019-07-04 6:46 ` Jia He 2019-07-04 8:18 ` Xiongfeng Wang 2019-06-29 2:42 ` [RFC PATCH v2 3/3] arm64: Add CPU hotplug support Xiongfeng Wang 2019-06-29 3:23 ` [RFC PATCH v2 0/3] Support CPU hotplug for ARM64 Xiongfeng Wang 2019-07-05 10:12 ` James Morse 2019-07-09 19:06 ` Maran Wilson 2019-07-10 9:15 ` Marc Zyngier 2019-07-10 16:05 ` Maran Wilson 2019-07-15 13:43 ` James Morse 2019-07-16 7:59 ` Jia He 2019-07-16 8:32 ` Marc Zyngier 2019-07-16 7:52 ` Xiongfeng Wang
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