* [PATCH] clk: imx: pll14xx: avoid glitch when set rate
@ 2019-08-20 2:17 Peng Fan
2019-08-22 8:20 ` Leonard Crestez
0 siblings, 1 reply; 4+ messages in thread
From: Peng Fan @ 2019-08-20 2:17 UTC (permalink / raw)
To: mturquette, sboyd, shawnguo, s.hauer, festevam
Cc: kernel, dl-linux-imx, Anson Huang, Jacky Bai, Abel Vesa,
linux-clk, linux-arm-kernel, linux-kernel, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
According to PLL1443XA and PLL1416X spec,
"When BYPASS is 0 and RESETB is changed from 0 to 1, FOUT starts to
output unstable clock until lock time passes. PLL1416X/PLL1443XA may
generate a glitch at FOUT."
So set BYPASS when RESETB is changed from 0 to 1 to avoid glitch.
In the end of set rate, BYPASS will be cleared.
Fixes: 8646d4dcc7fb ("clk: imx: Add PLLs driver for imx8mm soc")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/clk/imx/clk-pll14xx.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c
index b7213023b238..bd072556bc44 100644
--- a/drivers/clk/imx/clk-pll14xx.c
+++ b/drivers/clk/imx/clk-pll14xx.c
@@ -191,6 +191,10 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate,
tmp &= ~RST_MASK;
writel_relaxed(tmp, pll->base);
+ /* Enable BYPASS */
+ tmp |= BYPASS_MASK;
+ writel(tmp, pll->base);
+
div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
(rate->sdiv << SDIV_SHIFT);
writel_relaxed(div_val, pll->base + 0x4);
@@ -250,6 +254,10 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate,
tmp &= ~RST_MASK;
writel_relaxed(tmp, pll->base);
+ /* Enable BYPASS */
+ tmp |= BYPASS_MASK;
+ writel_relaxed(tmp, pll->base);
+
div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
(rate->sdiv << SDIV_SHIFT);
writel_relaxed(div_val, pll->base + 0x4);
--
2.16.4
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] clk: imx: pll14xx: avoid glitch when set rate
2019-08-20 2:17 [PATCH] clk: imx: pll14xx: avoid glitch when set rate Peng Fan
@ 2019-08-22 8:20 ` Leonard Crestez
2019-08-22 9:18 ` Peng Fan
0 siblings, 1 reply; 4+ messages in thread
From: Leonard Crestez @ 2019-08-22 8:20 UTC (permalink / raw)
To: Peng Fan, sboyd, Jacky Bai
Cc: mturquette, shawnguo, s.hauer, festevam, kernel, dl-linux-imx,
Anson Huang, Abel Vesa, linux-clk, linux-arm-kernel,
linux-kernel
On 20.08.2019 05:17, Peng Fan wrote:
> According to PLL1443XA and PLL1416X spec,
> "When BYPASS is 0 and RESETB is changed from 0 to 1, FOUT starts to
> output unstable clock until lock time passes. PLL1416X/PLL1443XA may
> generate a glitch at FOUT."
>
> So set BYPASS when RESETB is changed from 0 to 1 to avoid glitch.
> In the end of set rate, BYPASS will be cleared.
>
> @@ -191,6 +191,10 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate,
> tmp &= ~RST_MASK;
> writel_relaxed(tmp, pll->base);
>
> + /* Enable BYPASS */
> + tmp |= BYPASS_MASK;
> + writel(tmp, pll->base);
> +
Shouldn't BYPASS be set before reset?
Also, isn't a similar bypass/unbypass dance also needed in
clk_pll14xx_prepare? As far as I understand that could also output
glitches until the PLL is locked. It could be a separate patch.
It's strange that this BYPASS bit is also handled by muxes like
audio_pll1_bypass in clk-imx8mm.c but that's a separate issue not
strictly related to the glitches you're trying to fix here.
--
Regards,
Leonard
^ permalink raw reply [flat|nested] 4+ messages in thread
* RE: [PATCH] clk: imx: pll14xx: avoid glitch when set rate
2019-08-22 8:20 ` Leonard Crestez
@ 2019-08-22 9:18 ` Peng Fan
2019-08-22 12:34 ` Leonard Crestez
0 siblings, 1 reply; 4+ messages in thread
From: Peng Fan @ 2019-08-22 9:18 UTC (permalink / raw)
To: Leonard Crestez, sboyd, Jacky Bai
Cc: mturquette, shawnguo, s.hauer, festevam, kernel, dl-linux-imx,
Anson Huang, Abel Vesa, linux-clk, linux-arm-kernel,
linux-kernel
> Subject: Re: [PATCH] clk: imx: pll14xx: avoid glitch when set rate
>
> On 20.08.2019 05:17, Peng Fan wrote:
> > According to PLL1443XA and PLL1416X spec, "When BYPASS is 0 and RESETB
> > is changed from 0 to 1, FOUT starts to output unstable clock until
> > lock time passes. PLL1416X/PLL1443XA may generate a glitch at FOUT."
> >
> > So set BYPASS when RESETB is changed from 0 to 1 to avoid glitch.
> > In the end of set rate, BYPASS will be cleared.
> >
> > @@ -191,6 +191,10 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw,
> unsigned long drate,
> > tmp &= ~RST_MASK;
> > writel_relaxed(tmp, pll->base);
> >
> > + /* Enable BYPASS */
> > + tmp |= BYPASS_MASK;
> > + writel(tmp, pll->base);
> > +
>
> Shouldn't BYPASS be set before reset?
No. the glitch happens when RESET changes from 0 to 1, not from 1 to 0.
>
> Also, isn't a similar bypass/unbypass dance also needed in
> clk_pll14xx_prepare? As far as I understand that could also output glitches
> until the PLL is locked. It could be a separate patch.
Yes, that might also output glitch. Fix in v2.
>
> It's strange that this BYPASS bit is also handled by muxes like
> audio_pll1_bypass in clk-imx8mm.c but that's a separate issue not strictly
> related to the glitches you're trying to fix here.
Yes, need use EXT_BYPASS for the mux usage.
Regards,
Peng.
>
> --
> Regards,
> Leonard
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] clk: imx: pll14xx: avoid glitch when set rate
2019-08-22 9:18 ` Peng Fan
@ 2019-08-22 12:34 ` Leonard Crestez
0 siblings, 0 replies; 4+ messages in thread
From: Leonard Crestez @ 2019-08-22 12:34 UTC (permalink / raw)
To: Peng Fan, sboyd
Cc: Jacky Bai, mturquette, shawnguo, s.hauer, festevam, kernel,
dl-linux-imx, Anson Huang, Abel Vesa, linux-clk,
linux-arm-kernel, linux-kernel
On 22.08.2019 12:18, Peng Fan wrote:
>> Subject: Re: [PATCH] clk: imx: pll14xx: avoid glitch when set rate
>>
>> On 20.08.2019 05:17, Peng Fan wrote:
>>> According to PLL1443XA and PLL1416X spec, "When BYPASS is 0 and RESETB
>>> is changed from 0 to 1, FOUT starts to output unstable clock until
>>> lock time passes. PLL1416X/PLL1443XA may generate a glitch at FOUT."
>>>
>>> So set BYPASS when RESETB is changed from 0 to 1 to avoid glitch.
>>> In the end of set rate, BYPASS will be cleared.
>>>
>>> @@ -191,6 +191,10 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw,
>> unsigned long drate,
>>> tmp &= ~RST_MASK;
>>> writel_relaxed(tmp, pll->base);
>>>
>>> + /* Enable BYPASS */
>>> + tmp |= BYPASS_MASK;
>>> + writel(tmp, pll->base);
>>> +
>>
>> Shouldn't BYPASS be set before reset?
>
> No. the glitch happens when RESET changes from 0 to 1, not from 1 to 0.
You're right, sorry.
>> Also, isn't a similar bypass/unbypass dance also needed in
>> clk_pll14xx_prepare? As far as I understand that could also output glitches
>> until the PLL is locked. It could be a separate patch.
>
> Yes, that might also output glitch. Fix in v2.
>
>>
>> It's strange that this BYPASS bit is also handled by muxes like
>> audio_pll1_bypass in clk-imx8mm.c but that's a separate issue not strictly
>> related to the glitches you're trying to fix here.
>
> Yes, need use EXT_BYPASS for the mux usage.
Might make sense to post as a series.
^ permalink raw reply [flat|nested] 4+ messages in thread
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2019-08-20 2:17 [PATCH] clk: imx: pll14xx: avoid glitch when set rate Peng Fan
2019-08-22 8:20 ` Leonard Crestez
2019-08-22 9:18 ` Peng Fan
2019-08-22 12:34 ` Leonard Crestez
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