* [PATCHv5 0/2] Variscite DART-6UL SoM support @ 2019-08-28 16:19 Oliver Graute 2019-08-28 16:19 ` [PATCHv5 1/2] ARM: dts: imx6ul: Add " Oliver Graute 2019-08-28 16:19 ` [PATCHv5 2/2] ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard Oliver Graute 0 siblings, 2 replies; 5+ messages in thread From: Oliver Graute @ 2019-08-28 16:19 UTC (permalink / raw) To: shawnguo Cc: oliver.graute, narmstrong, Rob Herring, Mark Rutland, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, devicetree, linux-kernel, linux-arm-kernel Need feedback to the following patches which adds support for a DART-6UL Board Need feedback howto document propertys and compatible the right way Need feedback why ethernet RX is deaf Product Page: https://www.variscite.com/product/evaluation-kits/dart-6ul-kits Oliver Graute (2): ARM: dts: imx6ul: Add Variscite DART-6UL SoM support ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard arch/arm/boot/dts/Makefile | 1 + .../boot/dts/imx6ul-imx6ull-var-dart-common.dtsi | 445 +++++++++++++++++++++ arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts | 196 +++++++++ 3 files changed, 642 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi create mode 100644 arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts -- 2.7.4 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCHv5 1/2] ARM: dts: imx6ul: Add Variscite DART-6UL SoM support 2019-08-28 16:19 [PATCHv5 0/2] Variscite DART-6UL SoM support Oliver Graute @ 2019-08-28 16:19 ` Oliver Graute 2019-08-29 7:28 ` Marco Felsch 2019-08-28 16:19 ` [PATCHv5 2/2] ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard Oliver Graute 1 sibling, 1 reply; 5+ messages in thread From: Oliver Graute @ 2019-08-28 16:19 UTC (permalink / raw) To: shawnguo Cc: oliver.graute, narmstrong, Rob Herring, Mark Rutland, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, devicetree, linux-kernel, linux-arm-kernel This patch adds support for the i.MX6UL variant of the Variscite DART-6UL SoM Carrier-Board Signed-off-by: Oliver Graute <oliver.graute@gmail.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Neil Armstrong <narmstrong@baylibre.com> --- .../boot/dts/imx6ul-imx6ull-var-dart-common.dtsi | 445 +++++++++++++++++++++ 1 file changed, 445 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi diff --git a/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi b/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi new file mode 100644 index 00000000..f345d69 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi @@ -0,0 +1,445 @@ +// SPDX-License-Identifier: (GPL-2.0) +/dts-v1/; + +#include "imx6ul.dtsi" +/ { + chosen { + stdout-path = &uart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + touch_3v3_regulator: regulator-touch-3v3 { + compatible = "regulator-fixed"; + regulator-name = "touch_3v3_supply"; + regulator-always-on; + }; + + reg_sd1_vmmc: regulator-sd1-vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_gpio_dvfs: regulator-gpio { + compatible = "regulator-gpio"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1400000>; + regulator-name = "gpio_dvfs"; + regulator-type = "voltage"; + gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + states = <1300000 0x1 1400000 0x0>; + }; + + rmii_ref_clk: clock-rmii-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "rmii-ref"; + }; + +}; + +&adc1 { + vref-supply = <&touch_3v3_regulator>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "disabled"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "disabled"; +}; + +&cpu0 { + arm-supply = <®_arm>; + soc-supply = <®_soc>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + status = "disabled"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + status = "disabled"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + micrel,rmii-reference-clock-select-25-mhz; + clocks = <&rmii_ref_clk>; + clock-names = "rmii-ref"; + reg = <1>; + }; + + ethphy1: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + micrel,rmii-reference-clock-select-25-mhz; + clocks = <&rmii_ref_clk>; + clock-names = "rmii-ref"; + reg = <3>; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; + + partition@0 { + label = "spl"; + reg = <0x00000000 0x00200000>; + }; + + partition@200000 { + label = "uboot"; + reg = <0x00200000 0x00200000>; + }; + + partition@400000 { + label = "uboot-env"; + reg = <0x00400000 0x00200000>; + }; + + partition@600000 { + label = "kernel"; + reg = <0x00600000 0x00800000>; + }; + + partition@e00000 { + label = "rootfs"; + reg = <0x00e00000 0x3f200000>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "disabled"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "disabled"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "disabled"; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, + <&clks IMX6UL_CLK_SAI2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&snvs_rtc { + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "disabled"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "disabled"; +}; + +&usbotg1 { + disable-over-current; + status = "disabled"; +}; + +&usbotg2 { + disable-over-current; + status = "disabled"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + no-1-8-v; + keep-power-in-suspend; + vmmc-supply = <®_sd1_vmmc>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + status = "disabled"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x1b0b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp{ + fsl,pins = < + MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x1b0b0 + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x17059 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x03029 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_lcdif: lcdif { + fsl,pins = < + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x11088 + MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x17088 + MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x11088 + MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x11088 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x1b0b1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x1b0b1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x1b0b1 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x78b0 + >; + }; +}; -- 2.7.4 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCHv5 1/2] ARM: dts: imx6ul: Add Variscite DART-6UL SoM support 2019-08-28 16:19 ` [PATCHv5 1/2] ARM: dts: imx6ul: Add " Oliver Graute @ 2019-08-29 7:28 ` Marco Felsch 0 siblings, 0 replies; 5+ messages in thread From: Marco Felsch @ 2019-08-29 7:28 UTC (permalink / raw) To: Oliver Graute Cc: shawnguo, Mark Rutland, devicetree, narmstrong, Sascha Hauer, linux-kernel, Rob Herring, NXP Linux Team, Pengutronix Kernel Team, Fabio Estevam, linux-arm-kernel Hi Oliver, thanks for the patch. On 19-08-28 18:19, Oliver Graute wrote: > This patch adds support for the i.MX6UL variant of the Variscite DART-6UL > SoM Carrier-Board > > Signed-off-by: Oliver Graute <oliver.graute@gmail.com> > Cc: Shawn Guo <shawnguo@kernel.org> > Cc: Neil Armstrong <narmstrong@baylibre.com> > --- > .../boot/dts/imx6ul-imx6ull-var-dart-common.dtsi | 445 +++++++++++++++++++++ Is it a imx6ul or a imx6ull? Also can you add a changelog the next time? > 1 file changed, 445 insertions(+) > create mode 100644 arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi > > diff --git a/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi b/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi > new file mode 100644 > index 00000000..f345d69 > --- /dev/null > +++ b/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi > @@ -0,0 +1,445 @@ > +// SPDX-License-Identifier: (GPL-2.0) > +/dts-v1/; > + > +#include "imx6ul.dtsi" > +/ { > + chosen { > + stdout-path = &uart1; You specify uart1 here and disable the node below... That seems wrong to me. > + }; > + > + memory@80000000 { > + device_type = "memory"; > + reg = <0x80000000 0x20000000>; > + }; > + > + touch_3v3_regulator: regulator-touch-3v3 { > + compatible = "regulator-fixed"; > + regulator-name = "touch_3v3_supply"; > + regulator-always-on; Why is it always-on? > + }; Please name the phandle reg_touch_3v3 and specify the regulator-min-microvolt/regulator-max-microvolt properties. > + > + reg_sd1_vmmc: regulator-sd1-vmmc { > + compatible = "regulator-fixed"; > + regulator-name = "VSD_3V3"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + }; > + > + reg_gpio_dvfs: regulator-gpio { > + compatible = "regulator-gpio"; > + regulator-min-microvolt = <1300000>; > + regulator-max-microvolt = <1400000>; > + regulator-name = "gpio_dvfs"; > + regulator-type = "voltage"; > + gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + states = <1300000 0x1 1400000 0x0>; > + }; > + > + rmii_ref_clk: clock-rmii-ref { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <25000000>; > + clock-output-names = "rmii-ref"; > + }; Alphabetical ordering please and please rename the phandle to clk_rmii_ref or something. > + > +}; > + > +&adc1 { > + vref-supply = <&touch_3v3_regulator>; > + status = "okay"; > +}; > + > +&can1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_flexcan1>; > + status = "disabled"; No need to disable it here, it is disabled in the SoC DT. > +}; > + > +&can2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_flexcan2>; > + status = "disabled"; Here too. > +}; > + > +&cpu0 { > + arm-supply = <®_arm>; > + soc-supply = <®_soc>; > +}; > + > +&fec1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_enet1>; > + phy-mode = "rmii"; > + status = "disabled"; And here. > +}; > + > +&fec2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_enet2>; > + phy-mode = "rmii"; > + status = "disabled"; And here. > + mdio { > + #address-cells = <1>; > + #size-cells = <0>; > + > + ethphy0: ethernet-phy@1 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + micrel,rmii-reference-clock-select-25-mhz; > + clocks = <&rmii_ref_clk>; > + clock-names = "rmii-ref"; Do we need to specify the clock-names? > + reg = <1>; > + }; > + > + ethphy1: ethernet-phy@3 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + micrel,rmii-reference-clock-select-25-mhz; > + clocks = <&rmii_ref_clk>; > + clock-names = "rmii-ref"; > + reg = <3>; > + }; > + }; > +}; > + > +&gpmi { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_gpmi_nand>; > + status = "okay"; > + > + partition@0 { > + label = "spl"; > + reg = <0x00000000 0x00200000>; > + }; > + > + partition@200000 { > + label = "uboot"; > + reg = <0x00200000 0x00200000>; > + }; > + > + partition@400000 { > + label = "uboot-env"; > + reg = <0x00400000 0x00200000>; > + }; > + > + partition@600000 { > + label = "kernel"; > + reg = <0x00600000 0x00800000>; > + }; > + > + partition@e00000 { > + label = "rootfs"; > + reg = <0x00e00000 0x3f200000>; > + }; Nope, partitions must be within a subnode. Please check Documentation/devicetree/bindings/mtd/partition.txt. > +}; > + > +&i2c1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c1>; > + status = "disabled"; Drop the status line. > +}; > + > +&i2c2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c2>; > + status = "disabled"; Drop the status line. > +}; > + > +&pwm1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pwm1>; > + status = "disabled"; Drop the status line. > +}; > + > +&sai2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_sai2>; > + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, > + <&clks IMX6UL_CLK_SAI2>; > + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; > + assigned-clock-rates = <0>, <12288000>; > + fsl,sai-mclk-direction-output; > + status = "okay"; > +}; > + > +&snvs_poweroff { > + status = "okay"; > +}; > + > +&snvs_rtc { > + status = "disabled"; > +}; > + > +&uart1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart1>; > + status = "disabled"; No need. > +}; > + > +&uart2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart2>; > + uart-has-rtscts; > + status = "disabled"; No need. > +}; > + > +&uart3 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart3>; > + uart-has-rtscts; > + status = "disabled"; No need. > +}; > + > +&usbotg1 { > + disable-over-current; > + status = "disabled"; No need. > +}; > + > +&usbotg2 { > + disable-over-current; > + status = "disabled"; No need. > +}; > + > +&usdhc1 { > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > + pinctrl-0 = <&pinctrl_usdhc1>; > + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; > + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; > + no-1-8-v; > + keep-power-in-suspend; > + vmmc-supply = <®_sd1_vmmc>; I tought the highspeed modes using 1.8V signal levels. > + non-removable; Please specify the bus-with too. BTW. is it a SD-Card or an eMMC? > + status = "okay"; > +}; > + > +&usdhc2 { > + status = "disabled"; > +}; Remove the whole node. > +&wdog1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_wdog>; > + fsl,ext-reset-output; > +}; > + > +&iomuxc { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_hog>; > + > + pinctrl_enet1: enet1grp { > + fsl,pins = < > + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 > + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 > + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 > + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 > + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 > + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 > + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 > + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 > + >; > + }; > + > + pinctrl_enet2: enet2grp { > + fsl,pins = < > + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 > + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 > + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 > + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 > + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 > + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 > + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 > + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 > + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 > + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 > + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x1b0b0 > + >; > + }; > + > + pinctrl_flexcan1: flexcan1grp{ > + fsl,pins = < > + MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x1b020 > + MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x1b020 > + >; > + }; > + > + pinctrl_flexcan2: flexcan2grp{ > + fsl,pins = < > + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 > + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 > + >; > + }; > + > + pinctrl_gpio_leds: gpioledsgrp { > + fsl,pins = < > + MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x1b0b0 > + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x17059 > + >; > + }; You didn't reference that node. > + > + pinctrl_gpmi_nand: gpminandgrp { > + fsl,pins = < > + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 > + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 > + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 > + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 > + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 > + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 > + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 > + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 > + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 > + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 > + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 > + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 > + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 > + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 > + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 > + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 > + >; > + }; > + > + pinctrl_hog: hoggrp { > + fsl,pins = < > + MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x03029 > + >; > + }; > + > + pinctrl_i2c1: i2c1grp { > + fsl,pins = < > + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 > + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 > + >; > + }; > + > + pinctrl_i2c2: i2c2grp { > + fsl,pins = < > + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 > + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 > + >; > + }; > + > + pinctrl_lcdif: lcdif { > + fsl,pins = < > + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 > + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 > + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 > + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 > + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 > + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 > + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 > + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 > + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 > + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 > + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 > + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 > + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 > + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 > + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 > + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 > + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 > + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 > + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 > + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 > + >; > + }; You didn't reference that. > + > + pinctrl_pwm1: pwm1grp { > + fsl,pins = < > + MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x110b0 > + >; > + }; > + > + pinctrl_sai1: sai1grp { > + fsl,pins = < > + MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x11088 > + MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x17088 > + MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x11088 > + MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x11088 > + >; > + }; You didn't reference that. > + pinctrl_sai2: sai2grp { > + fsl,pins = < > + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 > + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 > + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 > + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 > + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 > + >; > + }; > + > + pinctrl_tsc: tscgrp { > + fsl,pins = < > + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 > + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 > + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 > + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 > + >; > + }; You didn't reference that. > + pinctrl_uart1: uart1grp { > + fsl,pins = < > + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 > + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 > + >; > + }; > + > + pinctrl_uart2: uart2grp { > + fsl,pins = < > + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 > + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 > + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 > + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 > + >; > + }; > + > + pinctrl_uart3: uart3grp { > + fsl,pins = < > + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 > + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 > + MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1 > + MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 > + >; > + }; > + > + pinctrl_usdhc1: usdhc1grp { > + fsl,pins = < > + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 > + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 > + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 > + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 > + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 > + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 > + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x1b0b1 > + >; > + }; > + > + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { > + fsl,pins = < > + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 > + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 > + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 > + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 > + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 > + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 > + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x1b0b1 > + >; > + }; > + > + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { > + fsl,pins = < > + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 > + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 > + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 > + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 > + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 > + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 > + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x1b0b1 > + >; > + }; > + > + pinctrl_wdog: wdoggrp { > + fsl,pins = < > + MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x78b0 > + >; > + }; > +}; > -- > 2.7.4 > > > -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCHv5 2/2] ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard 2019-08-28 16:19 [PATCHv5 0/2] Variscite DART-6UL SoM support Oliver Graute 2019-08-28 16:19 ` [PATCHv5 1/2] ARM: dts: imx6ul: Add " Oliver Graute @ 2019-08-28 16:19 ` Oliver Graute 2019-08-29 7:54 ` Marco Felsch 1 sibling, 1 reply; 5+ messages in thread From: Oliver Graute @ 2019-08-28 16:19 UTC (permalink / raw) To: shawnguo Cc: oliver.graute, narmstrong, Rob Herring, Mark Rutland, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, devicetree, linux-kernel, linux-arm-kernel This patch adds DeviceTree Source for the i.MX6 UltraLite DART NAND/WIFI Signed-off-by: Oliver Graute <oliver.graute@gmail.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Neil Armstrong <narmstrong@baylibre.com> --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts | 196 ++++++++++++++++++++++++ 2 files changed, 197 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index a24a6a1..a2a69e4 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -579,6 +579,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-tx6ul-0010.dtb \ imx6ul-tx6ul-0011.dtb \ imx6ul-tx6ul-mainboard.dtb \ + imx6ul-var-6ulcustomboard.dtb \ imx6ull-14x14-evk.dtb \ imx6ull-colibri-eval-v3.dtb \ imx6ull-colibri-wifi-eval-v3.dtb \ diff --git a/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts b/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts new file mode 100644 index 00000000..1861b34 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * Support for Variscite DART-6UL Module + * + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright (C) 2015-2016 Variscite Ltd. - http://www.variscite.com + * Copyright (C) 2018-2019 Oliver Graute <oliver.graute@gmail.com> + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include "imx6ul-imx6ull-var-dart-common.dtsi" + +/ { + model = "Variscite i.MX6 UltraLite Carrier-board"; + compatible = "variscite,6ulcustomboard", "fsl,imx6ul"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 20000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + user { + gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + linux,code = <KEY_BACK>; + gpio-key,wakeup; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + d16-led { + gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "wm8731audio"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line Jack", + "Microphone", "Mic Jack"; + simple-audio-card,routing = + "Headphone Jack", "RHPOUT", + "Headphone Jack", "LHPOUT", + "LLINEIN", "Line Jack", + "RLINEIN", "Line Jack", + "MICIN", "Mic Bias", + "Mic Bias", "Mic Jack"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + + sound_master: simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + }; +}; + +&can1 { + status = "okay"; +}; + +&can2 { + status = "okay"; +}; + +&fec1 { + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&fec2 { + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + phy-handle = <ðphy1>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + wm8731: audio-codec@1a { + #sound-dai-cells = <0>; + compatible = "wlf,wm8731"; + reg = <0x1a>; + clocks = <&clks IMX6UL_CLK_SAI2>; + clock-names = "mclk"; + }; + + touchscreen@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + interrupt-parent = <&gpio3>; + interrupts = <4 0>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + wakeup-source; + }; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-parent = <&gpio5>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency =<35000000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <40>; + hback-porch = <40>; + hsync-len = <48>; + vback-porch = <29>; + vfront-porch = <13>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbotg1 { + dr_mode = "host"; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + status = "okay"; +}; + +&iomuxc { + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 + >; + }; +}; -- 2.7.4 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCHv5 2/2] ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard 2019-08-28 16:19 ` [PATCHv5 2/2] ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard Oliver Graute @ 2019-08-29 7:54 ` Marco Felsch 0 siblings, 0 replies; 5+ messages in thread From: Marco Felsch @ 2019-08-29 7:54 UTC (permalink / raw) To: Oliver Graute Cc: shawnguo, Mark Rutland, devicetree, narmstrong, Sascha Hauer, linux-kernel, Rob Herring, NXP Linux Team, Pengutronix Kernel Team, Fabio Estevam, linux-arm-kernel Hi Oliver, On 19-08-28 18:19, Oliver Graute wrote: > This patch adds DeviceTree Source for the i.MX6 UltraLite DART NAND/WIFI > > Signed-off-by: Oliver Graute <oliver.graute@gmail.com> > Cc: Shawn Guo <shawnguo@kernel.org> > Cc: Neil Armstrong <narmstrong@baylibre.com> > --- > arch/arm/boot/dts/Makefile | 1 + > arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts | 196 ++++++++++++++++++++++++ > 2 files changed, 197 insertions(+) > create mode 100644 arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index a24a6a1..a2a69e4 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -579,6 +579,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ > imx6ul-tx6ul-0010.dtb \ > imx6ul-tx6ul-0011.dtb \ > imx6ul-tx6ul-mainboard.dtb \ > + imx6ul-var-6ulcustomboard.dtb \ > imx6ull-14x14-evk.dtb \ > imx6ull-colibri-eval-v3.dtb \ > imx6ull-colibri-wifi-eval-v3.dtb \ > diff --git a/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts b/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts > new file mode 100644 > index 00000000..1861b34 > --- /dev/null > +++ b/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts > @@ -0,0 +1,196 @@ > +// SPDX-License-Identifier: (GPL-2.0) > +/* > + * Support for Variscite DART-6UL Module > + * > + * Copyright (C) 2015 Freescale Semiconductor, Inc. > + * Copyright (C) 2015-2016 Variscite Ltd. - http://www.variscite.com > + * Copyright (C) 2018-2019 Oliver Graute <oliver.graute@gmail.com> > + */ > + > +/dts-v1/; > + > +#include <dt-bindings/input/input.h> > +#include "imx6ul-imx6ull-var-dart-common.dtsi" > + > +/ { > + model = "Variscite i.MX6 UltraLite Carrier-board"; > + compatible = "variscite,6ulcustomboard", "fsl,imx6ul"; > + > + backlight { > + compatible = "pwm-backlight"; > + pwms = <&pwm1 0 20000>; > + brightness-levels = <0 4 8 16 32 64 128 255>; > + default-brightness-level = <6>; > + status = "okay"; > + }; > + > + gpio-keys { > + compatible = "gpio-keys"; > + > + user { > + gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; Please mux the gpios where you need them. In this case mux it within the gpio-keys node. > + linux,code = <KEY_BACK>; > + gpio-key,wakeup; > + }; > + }; > + > + gpio-leds { > + compatible = "gpio-leds"; > + > + d16-led { > + gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; The same applies here. > + linux,default-trigger = "heartbeat"; > + }; > + }; > + > + sound { > + compatible = "simple-audio-card"; > + simple-audio-card,name = "wm8731audio"; > + simple-audio-card,widgets = > + "Headphone", "Headphone Jack", > + "Line", "Line Jack", > + "Microphone", "Mic Jack"; > + simple-audio-card,routing = > + "Headphone Jack", "RHPOUT", > + "Headphone Jack", "LHPOUT", > + "LLINEIN", "Line Jack", > + "RLINEIN", "Line Jack", > + "MICIN", "Mic Bias", > + "Mic Bias", "Mic Jack"; > + simple-audio-card,format = "i2s"; > + simple-audio-card,bitclock-master = <&sound_master>; > + simple-audio-card,frame-master = <&sound_master>; > + > + sound_master: simple-audio-card,cpu { > + sound-dai = <&sai2>; > + }; Where is the codec node? > + }; > +}; > + > +&can1 { > + status = "okay"; We need to move the complete muxing from the SoM dtsi to the baseboard for all baseboard related nodes.. I tought that the Dart 6UL layout follows a specific standard but that isn't the case. > +}; > + > +&can2 { > + status = "okay"; > +}; > + > +&fec1 { > + phy-mode = "rgmii"; This avoid such re-assigning here too. Also the imx6ul only support 10/100 Mbit/s. So rgmii makes no sense here. > + phy-reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; > + phy-handle = <ðphy0>; > + status = "okay"; > +}; > + > +&fec2 { > + phy-mode = "rgmii"; > + phy-reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; > + phy-handle = <ðphy1>; > + status = "okay"; > +}; > + > +&i2c1 { > + clock-frequency = <400000>; > + status = "okay"; > +}; > + > +&i2c2 { > + clock_frequency = <100000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c2>; > + status = "okay"; > + > + wm8731: audio-codec@1a { > + #sound-dai-cells = <0>; Please move #sound-dai-cells below compatible and reg property. > + compatible = "wlf,wm8731"; > + reg = <0x1a>; > + clocks = <&clks IMX6UL_CLK_SAI2>; > + clock-names = "mclk"; > + }; > + > + touchscreen@38 { > + compatible = "edt,edt-ft5x06"; > + reg = <0x38>; > + interrupt-parent = <&gpio3>; > + interrupts = <4 0>; Make use of IRQ_TYPE_* > + touchscreen-size-x = <800>; > + touchscreen-size-y = <480>; > + touchscreen-inverted-x; > + touchscreen-inverted-y; > + wakeup-source; > + }; > + > + rtc@68 { > + compatible = "dallas,ds1337"; > + reg = <0x68>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_rtc>; > + interrupt-parent = <&gpio5>; > + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; > + }; > +}; > + > +&lcdif { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_lcdif>; > + display = <&display0>; > + status = "okay"; > + > + display0: display0 { > + bits-per-pixel = <16>; > + bus-width = <24>; > + > + display-timings { > + native-mode = <&timing0>; > + timing0: timing0 { > + clock-frequency =<35000000>; > + hactive = <800>; > + vactive = <480>; > + hfront-porch = <40>; > + hback-porch = <40>; > + hsync-len = <48>; > + vback-porch = <29>; > + vfront-porch = <13>; > + vsync-len = <3>; > + hsync-active = <0>; > + vsync-active = <0>; > + de-active = <1>; > + pixelclk-active = <0>; > + }; > + }; > + }; > +}; > + > +&pwm1 { > + status = "okay"; > +}; > + > +&uart1 { > + status = "okay"; > +}; > + > +&uart2 { > + status = "okay"; > +}; > + > +&uart3 { > + status = "okay"; > +}; > + > +&usbotg1 { > + dr_mode = "host"; > + status = "okay"; > +}; > + > +&usbotg2 { > + dr_mode = "host"; > + status = "okay"; > +}; > + > +&iomuxc { > + pinctrl_rtc: rtcgrp { > + fsl,pins = < > + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 > + >; > + }; As I said above, move the complete muxing pwm/usb/i2c/lcd/... from the som dtsi to the baseboard dts because it is only valid for this baseboard. Another baseboard using this som can have a complete different mux option. Regards, Marco > +}; > -- > 2.7.4 > > > -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2019-08-29 7:54 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-08-28 16:19 [PATCHv5 0/2] Variscite DART-6UL SoM support Oliver Graute 2019-08-28 16:19 ` [PATCHv5 1/2] ARM: dts: imx6ul: Add " Oliver Graute 2019-08-29 7:28 ` Marco Felsch 2019-08-28 16:19 ` [PATCHv5 2/2] ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard Oliver Graute 2019-08-29 7:54 ` Marco Felsch
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