* [PATCH v1 0/3] Runtime PM support for MT8183 mcucfg clock provider
@ 2019-09-02 8:35 Weiyi Lu
2019-09-02 8:35 ` [PATCH v1 1/3] clk: mediatek: Register clock gate with device Weiyi Lu
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Weiyi Lu @ 2019-09-02 8:35 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Stephen Boyd, Rob Herring
Cc: James Liao, Fan Chen, linux-arm-kernel, linux-kernel,
linux-mediatek, linux-clk, srv_heupstream, CK Hu, Weiyi Lu
This series is based on v5.3-rc1 and Mediatek MT8183 scpsys support v7[1].
Since Runtime PM is supported in Common Clock Framework which keeps
clock controller's power domain enabled to ensure clock status accessing correctly.
[1] https://patchwork.kernel.org/cover/11118371/
---
Weiyi Lu (3):
clk: mediatek: Register clock gate with device
clk: mediatek: Runtime PM support for MT8183 mcucfg clock provider
arm64: dts: Add power-domains properity to mfgcfg
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 1 +
drivers/clk/mediatek/clk-gate.c | 5 +++--
drivers/clk/mediatek/clk-gate.h | 3 ++-
drivers/clk/mediatek/clk-mt8183-mfgcfg.c | 7 +++++--
drivers/clk/mediatek/clk-mtk.c | 16 +++++++++++++---
drivers/clk/mediatek/clk-mtk.h | 5 +++++
6 files changed, 29 insertions(+), 8 deletions(-)
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v1 1/3] clk: mediatek: Register clock gate with device
2019-09-02 8:35 [PATCH v1 0/3] Runtime PM support for MT8183 mcucfg clock provider Weiyi Lu
@ 2019-09-02 8:35 ` Weiyi Lu
2019-09-02 8:35 ` [PATCH v1 2/3] clk: mediatek: Runtime PM support for MT8183 mcucfg clock provider Weiyi Lu
2019-09-02 8:35 ` [PATCH v1 3/3] arm64: dts: Add power-domains properity to mfgcfg Weiyi Lu
2 siblings, 0 replies; 5+ messages in thread
From: Weiyi Lu @ 2019-09-02 8:35 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Stephen Boyd, Rob Herring
Cc: James Liao, Fan Chen, linux-arm-kernel, linux-kernel,
linux-mediatek, linux-clk, srv_heupstream, CK Hu, Weiyi Lu
Allow those clocks under a power domain to do the runtime pm operation
by forwarding the struct device pointer from clock provider.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
drivers/clk/mediatek/clk-gate.c | 5 +++--
drivers/clk/mediatek/clk-gate.h | 3 ++-
drivers/clk/mediatek/clk-mtk.c | 16 +++++++++++++---
drivers/clk/mediatek/clk-mtk.h | 5 +++++
4 files changed, 23 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
index 803bf0a..a35cf0b 100644
--- a/drivers/clk/mediatek/clk-gate.c
+++ b/drivers/clk/mediatek/clk-gate.c
@@ -150,7 +150,8 @@ struct clk *mtk_clk_register_gate(
int sta_ofs,
u8 bit,
const struct clk_ops *ops,
- unsigned long flags)
+ unsigned long flags,
+ struct device *dev)
{
struct mtk_clk_gate *cg;
struct clk *clk;
@@ -174,7 +175,7 @@ struct clk *mtk_clk_register_gate(
cg->hw.init = &init;
- clk = clk_register(NULL, &cg->hw);
+ clk = clk_register(dev, &cg->hw);
if (IS_ERR(clk))
kfree(cg);
diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h
index e05c736..3c3329e 100644
--- a/drivers/clk/mediatek/clk-gate.h
+++ b/drivers/clk/mediatek/clk-gate.h
@@ -40,7 +40,8 @@ struct clk *mtk_clk_register_gate(
int sta_ofs,
u8 bit,
const struct clk_ops *ops,
- unsigned long flags);
+ unsigned long flags,
+ struct device *dev);
#define GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, \
_ops, _flags) { \
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index d28790c..cec1c8a 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -12,6 +12,7 @@
#include <linux/delay.h>
#include <linux/clkdev.h>
#include <linux/mfd/syscon.h>
+#include <linux/device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
@@ -93,9 +94,10 @@ void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
}
}
-int mtk_clk_register_gates(struct device_node *node,
+int mtk_clk_register_gates_with_dev(struct device_node *node,
const struct mtk_gate *clks,
- int num, struct clk_onecell_data *clk_data)
+ int num, struct clk_onecell_data *clk_data,
+ struct device *dev)
{
int i;
struct clk *clk;
@@ -122,7 +124,7 @@ int mtk_clk_register_gates(struct device_node *node,
gate->regs->set_ofs,
gate->regs->clr_ofs,
gate->regs->sta_ofs,
- gate->shift, gate->ops, gate->flags);
+ gate->shift, gate->ops, gate->flags, dev);
if (IS_ERR(clk)) {
pr_err("Failed to register clk %s: %ld\n",
@@ -136,6 +138,14 @@ int mtk_clk_register_gates(struct device_node *node,
return 0;
}
+int mtk_clk_register_gates(struct device_node *node,
+ const struct mtk_gate *clks,
+ int num, struct clk_onecell_data *clk_data)
+{
+ return mtk_clk_register_gates_with_dev(node,
+ clks, num, clk_data, NULL);
+}
+
struct clk *mtk_clk_register_composite(const struct mtk_composite *mc,
void __iomem *base, spinlock_t *lock)
{
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index 733a11d..0f8ada7 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -169,6 +169,11 @@ int mtk_clk_register_gates(struct device_node *node,
const struct mtk_gate *clks, int num,
struct clk_onecell_data *clk_data);
+int mtk_clk_register_gates_with_dev(struct device_node *node,
+ const struct mtk_gate *clks,
+ int num, struct clk_onecell_data *clk_data,
+ struct device *dev);
+
struct mtk_clk_divider {
int id;
const char *name;
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v1 2/3] clk: mediatek: Runtime PM support for MT8183 mcucfg clock provider
2019-09-02 8:35 [PATCH v1 0/3] Runtime PM support for MT8183 mcucfg clock provider Weiyi Lu
2019-09-02 8:35 ` [PATCH v1 1/3] clk: mediatek: Register clock gate with device Weiyi Lu
@ 2019-09-02 8:35 ` Weiyi Lu
2019-09-02 8:35 ` [PATCH v1 3/3] arm64: dts: Add power-domains properity to mfgcfg Weiyi Lu
2 siblings, 0 replies; 5+ messages in thread
From: Weiyi Lu @ 2019-09-02 8:35 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Stephen Boyd, Rob Herring
Cc: James Liao, Fan Chen, linux-arm-kernel, linux-kernel,
linux-mediatek, linux-clk, srv_heupstream, CK Hu, Weiyi Lu
Enable the runtime PM support and forward the struct device pointer for
registration of MT8183 mcucfg clocks.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
drivers/clk/mediatek/clk-mt8183-mfgcfg.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c b/drivers/clk/mediatek/clk-mt8183-mfgcfg.c
index 99a6b02..37b4162 100644
--- a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c
+++ b/drivers/clk/mediatek/clk-mt8183-mfgcfg.c
@@ -5,6 +5,7 @@
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include "clk-mtk.h"
#include "clk-gate.h"
@@ -30,10 +31,12 @@ static int clk_mt8183_mfg_probe(struct platform_device *pdev)
struct clk_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
+ pm_runtime_enable(&pdev->dev);
+
clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK);
- mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks),
- clk_data);
+ mtk_clk_register_gates_with_dev(node, mfg_clks, ARRAY_SIZE(mfg_clks),
+ clk_data, &pdev->dev);
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
}
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v1 3/3] arm64: dts: Add power-domains properity to mfgcfg
2019-09-02 8:35 [PATCH v1 0/3] Runtime PM support for MT8183 mcucfg clock provider Weiyi Lu
2019-09-02 8:35 ` [PATCH v1 1/3] clk: mediatek: Register clock gate with device Weiyi Lu
2019-09-02 8:35 ` [PATCH v1 2/3] clk: mediatek: Runtime PM support for MT8183 mcucfg clock provider Weiyi Lu
@ 2019-09-02 8:35 ` Weiyi Lu
2019-09-02 15:55 ` kbuild test robot
2 siblings, 1 reply; 5+ messages in thread
From: Weiyi Lu @ 2019-09-02 8:35 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Stephen Boyd, Rob Herring
Cc: James Liao, Fan Chen, linux-arm-kernel, linux-kernel,
linux-mediatek, linux-clk, srv_heupstream, CK Hu, Weiyi Lu
mfgcfg clock is under MFG_ASYNC power domain
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index c2749c4..3f948e9 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -388,6 +388,7 @@
compatible = "mediatek,mt8183-mfgcfg", "syscon";
reg = <0 0x13000000 0 0x1000>;
#clock-cells = <1>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_MFG_ASYNC>;
};
mmsys: syscon@14000000 {
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v1 3/3] arm64: dts: Add power-domains properity to mfgcfg
2019-09-02 8:35 ` [PATCH v1 3/3] arm64: dts: Add power-domains properity to mfgcfg Weiyi Lu
@ 2019-09-02 15:55 ` kbuild test robot
0 siblings, 0 replies; 5+ messages in thread
From: kbuild test robot @ 2019-09-02 15:55 UTC (permalink / raw)
To: Weiyi Lu
Cc: kbuild-all, Nicolas Boichat, Matthias Brugger, Stephen Boyd,
Rob Herring, James Liao, Fan Chen, linux-arm-kernel,
linux-kernel, linux-mediatek, linux-clk, srv_heupstream, CK Hu,
Weiyi Lu
[-- Attachment #1: Type: text/plain, Size: 1118 bytes --]
Hi Weiyi,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on linus/master]
[cannot apply to v5.3-rc6 next-20190902]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Weiyi-Lu/clk-mediatek-Register-clock-gate-with-device/20190902-174605
config: arm64-defconfig (attached as .config)
compiler: aarch64-linux-gcc (GCC) 7.4.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=7.4.0 make.cross ARCH=arm64
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> Error: arch/arm64/boot/dts/mediatek/mt8183.dtsi:391.29-30 syntax error
FATAL ERROR: Unable to parse input tree
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 45326 bytes --]
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2019-09-02 15:55 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2019-09-02 8:35 [PATCH v1 0/3] Runtime PM support for MT8183 mcucfg clock provider Weiyi Lu
2019-09-02 8:35 ` [PATCH v1 1/3] clk: mediatek: Register clock gate with device Weiyi Lu
2019-09-02 8:35 ` [PATCH v1 2/3] clk: mediatek: Runtime PM support for MT8183 mcucfg clock provider Weiyi Lu
2019-09-02 8:35 ` [PATCH v1 3/3] arm64: dts: Add power-domains properity to mfgcfg Weiyi Lu
2019-09-02 15:55 ` kbuild test robot
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