* [PATCH 0/2] Add support for ZRX-DC phy property [not found] <CGME20191028124238epcas5p451c77e6f4b37e4db69c87f839bd25574@epcas5p4.samsung.com> @ 2019-10-28 12:42 ` Anvesh Salveru [not found] ` <CGME20191028124253epcas5p3fd6b58e5ecd45bfd9c51dfdbd1a4ae40@epcas5p3.samsung.com> [not found] ` <CGME20191028124258epcas5p17861f4fdb40385a184fc397f45c898a5@epcas5p1.samsung.com> 0 siblings, 2 replies; 3+ messages in thread From: Anvesh Salveru @ 2019-10-28 12:42 UTC (permalink / raw) To: linux-pci, devicetree, linux-kernel, linux-tegra Cc: pankaj.dubey, thierry.reding, jonathanh, Anvesh Salveru DesignWare controller driver provides the support to handle the PHYs which are compliant to ZRX-DC specification based on "snps,phy-zrxdc-compliant" DT property. So, add "snps,phy-zrxdc-compliant" property in tegra pcie controller DT nodes and remove platform specific code from platform driver. Anvesh Salveru (2): PCI: tegra: Remove support for ZRX-DC compliant PHY from platform driver arm64: tegra: Add support for ZRX-DC phy property arch/arm64/boot/dts/nvidia/tegra194.dtsi | 6 ++++++ drivers/pci/controller/dwc/pcie-tegra194.c | 4 ---- 2 files changed, 6 insertions(+), 4 deletions(-) -- 2.17.1 ^ permalink raw reply [flat|nested] 3+ messages in thread
[parent not found: <CGME20191028124253epcas5p3fd6b58e5ecd45bfd9c51dfdbd1a4ae40@epcas5p3.samsung.com>]
* [PATCH 1/2] PCI: tegra: Remove support for ZRX-DC compliant PHY from platform driver [not found] ` <CGME20191028124253epcas5p3fd6b58e5ecd45bfd9c51dfdbd1a4ae40@epcas5p3.samsung.com> @ 2019-10-28 12:42 ` Anvesh Salveru 0 siblings, 0 replies; 3+ messages in thread From: Anvesh Salveru @ 2019-10-28 12:42 UTC (permalink / raw) To: linux-pci, devicetree, linux-kernel, linux-tegra Cc: pankaj.dubey, thierry.reding, jonathanh, Anvesh Salveru, Lorenzo Pieralisi, Andrew Murray, Bjorn Helgaas, Vidya Sagar As part of dw_pcie_setup(), PHYs which are compliant to ZRX-DC specification are already handled based on "snps,phy-zrxdc-compliant" property in controller DT node. So, instead of handling ZRX-DC compliant settings in each platform driver, remove this driver specific code. CC: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> CC: Andrew Murray <andrew.murray@arm.com> CC: Bjorn Helgaas <bhelgaas@google.com> CC: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Anvesh Salveru <anvesh.s@samsung.com> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> --- Depends on the following patch: https://patchwork.kernel.org/patch/11215241/ https://patchwork.kernel.org/patch/11215239/ drivers/pci/controller/dwc/pcie-tegra194.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index f89f5acee72d..f3a6ea89b8a8 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -782,10 +782,6 @@ static void tegra_pcie_prepare_host(struct pcie_port *pp) init_host_aspm(pcie); - val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); - val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; - dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); - if (pcie->update_fc_fixup) { val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF); val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT; -- 2.17.1 ^ permalink raw reply related [flat|nested] 3+ messages in thread
[parent not found: <CGME20191028124258epcas5p17861f4fdb40385a184fc397f45c898a5@epcas5p1.samsung.com>]
* [PATCH 2/2] arm64: tegra: Add support for ZRX-DC phy property [not found] ` <CGME20191028124258epcas5p17861f4fdb40385a184fc397f45c898a5@epcas5p1.samsung.com> @ 2019-10-28 12:42 ` Anvesh Salveru 0 siblings, 0 replies; 3+ messages in thread From: Anvesh Salveru @ 2019-10-28 12:42 UTC (permalink / raw) To: linux-pci, devicetree, linux-kernel, linux-tegra Cc: pankaj.dubey, thierry.reding, jonathanh, Anvesh Salveru, Rob Herring, Mark Rutland DesignWare controller driver provides the support to handle the PHYs which are compliant to ZRX-DC specification based on "snps,phy-zrxdc-compliant" DT property. So, add "snps,phy-zrxdc-compliant" property in tegra pcie controller DT nodes. CC: Rob Herring <robh+dt@kernel.org> CC: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Anvesh Salveru <anvesh.s@samsung.com> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> --- Depends on the following patch: https://patchwork.kernel.org/patch/11215241/ https://patchwork.kernel.org/patch/11215239/ arch/arm64/boot/dts/nvidia/tegra194.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 3c0cf54f0aab..bf2dbf84c8c9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1194,6 +1194,7 @@ ranges = <0x81000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000 /* downstream I/O (1MB) */ 0xc2000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 0x82000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ + snps,phy-zrxdc-compliant; }; pcie@14120000 { @@ -1240,6 +1241,7 @@ ranges = <0x81000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000 /* downstream I/O (1MB) */ 0xc2000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 0x82000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ + snps,phy-zrxdc-compliant; }; pcie@14140000 { @@ -1286,6 +1288,7 @@ ranges = <0x81000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000 /* downstream I/O (1MB) */ 0xc2000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 0x82000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ + snps,phy-zrxdc-compliant; }; pcie@14160000 { @@ -1332,6 +1335,7 @@ ranges = <0x81000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000 /* downstream I/O (1MB) */ 0xc2000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 0x82000000 0x0 0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ + snps,phy-zrxdc-compliant; }; pcie@14180000 { @@ -1378,6 +1382,7 @@ ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */ 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 0x82000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ + snps,phy-zrxdc-compliant; }; pcie@141a0000 { @@ -1428,6 +1433,7 @@ ranges = <0x81000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */ 0xc2000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ + snps,phy-zrxdc-compliant; }; sysram@40000000 { -- 2.17.1 ^ permalink raw reply related [flat|nested] 3+ messages in thread
end of thread, other threads:[~2019-10-28 12:44 UTC | newest] Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- [not found] <CGME20191028124238epcas5p451c77e6f4b37e4db69c87f839bd25574@epcas5p4.samsung.com> 2019-10-28 12:42 ` [PATCH 0/2] Add support for ZRX-DC phy property Anvesh Salveru [not found] ` <CGME20191028124253epcas5p3fd6b58e5ecd45bfd9c51dfdbd1a4ae40@epcas5p3.samsung.com> 2019-10-28 12:42 ` [PATCH 1/2] PCI: tegra: Remove support for ZRX-DC compliant PHY from platform driver Anvesh Salveru [not found] ` <CGME20191028124258epcas5p17861f4fdb40385a184fc397f45c898a5@epcas5p1.samsung.com> 2019-10-28 12:42 ` [PATCH 2/2] arm64: tegra: Add support for ZRX-DC phy property Anvesh Salveru
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