* [PATCH V2 net] net: hns3: fix a wrong reset interrupt status mask
@ 2019-11-20 2:07 Huazhong Tan
2019-11-20 3:11 ` David Miller
0 siblings, 1 reply; 4+ messages in thread
From: Huazhong Tan @ 2019-11-20 2:07 UTC (permalink / raw)
To: davem
Cc: netdev, linux-kernel, salil.mehta, yisen.zhuang, linuxarm,
jakub.kicinski, Huazhong Tan
According to hardware user manual, bits5~7 in register
HCLGE_MISC_VECTOR_INT_STS means reset interrupts status,
but HCLGE_RESET_INT_M is defined as bits0~2 now. So it
will make hclge_reset_err_handle() read the wrong reset
interrupt status.
This patch fixes this wrong bit mask.
Fixes: 2336f19d7892 ("net: hns3: check reset interrupt status when reset fails")
Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
---
Change log:
V1->V2: fixes comment from David Miller.
---
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
index 59b8243..615cde1 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
@@ -166,7 +166,7 @@ enum HLCGE_PORT_TYPE {
#define HCLGE_GLOBAL_RESET_BIT 0
#define HCLGE_CORE_RESET_BIT 1
#define HCLGE_IMP_RESET_BIT 2
-#define HCLGE_RESET_INT_M GENMASK(2, 0)
+#define HCLGE_RESET_INT_M GENMASK(7, 5)
#define HCLGE_FUN_RST_ING 0x20C00
#define HCLGE_FUN_RST_ING_B 0
--
2.7.4
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH V2 net] net: hns3: fix a wrong reset interrupt status mask
2019-11-20 2:07 [PATCH V2 net] net: hns3: fix a wrong reset interrupt status mask Huazhong Tan
@ 2019-11-20 3:11 ` David Miller
0 siblings, 0 replies; 4+ messages in thread
From: David Miller @ 2019-11-20 3:11 UTC (permalink / raw)
To: tanhuazhong
Cc: netdev, linux-kernel, salil.mehta, yisen.zhuang, linuxarm,
jakub.kicinski
From: Huazhong Tan <tanhuazhong@huawei.com>
Date: Wed, 20 Nov 2019 10:07:15 +0800
> According to hardware user manual, bits5~7 in register
> HCLGE_MISC_VECTOR_INT_STS means reset interrupts status,
> but HCLGE_RESET_INT_M is defined as bits0~2 now. So it
> will make hclge_reset_err_handle() read the wrong reset
> interrupt status.
>
> This patch fixes this wrong bit mask.
>
> Fixes: 2336f19d7892 ("net: hns3: check reset interrupt status when reset fails")
> Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
> ---
> Change log:
> V1->V2: fixes comment from David Miller.
Applied.
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH V2 net] net: hns3: fix a wrong reset interrupt status mask
2019-11-20 1:44 Huazhong Tan
@ 2019-11-20 1:48 ` tanhuazhong
0 siblings, 0 replies; 4+ messages in thread
From: tanhuazhong @ 2019-11-20 1:48 UTC (permalink / raw)
To: davem
Cc: netdev, linux-kernel, salil.mehta, yisen.zhuang, linuxarm,
jakub.kicinski
Sorry, please ignore this patch.
Will resend later.
On 2019/11/20 9:44, Huazhong Tan wrote:
> According to hardware user manual, bits5~7 in register
> HCLGE_MISC_VECTOR_INT_STS means reset interrupts status,
> but HCLGE_RESET_INT_M is defined as bits0~2 now. So it
> will make hclge_reset_err_handle() read the wrong reset
> interrupt status.
>
> This patch fixes this wrong bit mask.
>
> Fixes: 2336f19d7892 ("net: hns3: check reset interrupt status when reset fails")
> Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
> ---
> drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
> index 59b8243..615cde1 100644
> --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
> +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
> @@ -166,7 +166,7 @@ enum HLCGE_PORT_TYPE {
> #define HCLGE_GLOBAL_RESET_BIT 0
> #define HCLGE_CORE_RESET_BIT 1
> #define HCLGE_IMP_RESET_BIT 2
> -#define HCLGE_RESET_INT_M GENMASK(2, 0)
> +#define HCLGE_RESET_INT_M GENMASK(7, 5)
> #define HCLGE_FUN_RST_ING 0x20C00
> #define HCLGE_FUN_RST_ING_B 0
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH V2 net] net: hns3: fix a wrong reset interrupt status mask
@ 2019-11-20 1:44 Huazhong Tan
2019-11-20 1:48 ` tanhuazhong
0 siblings, 1 reply; 4+ messages in thread
From: Huazhong Tan @ 2019-11-20 1:44 UTC (permalink / raw)
To: davem
Cc: netdev, linux-kernel, salil.mehta, yisen.zhuang, linuxarm,
jakub.kicinski, Huazhong Tan
According to hardware user manual, bits5~7 in register
HCLGE_MISC_VECTOR_INT_STS means reset interrupts status,
but HCLGE_RESET_INT_M is defined as bits0~2 now. So it
will make hclge_reset_err_handle() read the wrong reset
interrupt status.
This patch fixes this wrong bit mask.
Fixes: 2336f19d7892 ("net: hns3: check reset interrupt status when reset fails")
Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
---
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
index 59b8243..615cde1 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
@@ -166,7 +166,7 @@ enum HLCGE_PORT_TYPE {
#define HCLGE_GLOBAL_RESET_BIT 0
#define HCLGE_CORE_RESET_BIT 1
#define HCLGE_IMP_RESET_BIT 2
-#define HCLGE_RESET_INT_M GENMASK(2, 0)
+#define HCLGE_RESET_INT_M GENMASK(7, 5)
#define HCLGE_FUN_RST_ING 0x20C00
#define HCLGE_FUN_RST_ING_B 0
--
2.7.4
^ permalink raw reply related [flat|nested] 4+ messages in thread
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