* [PATCH v3 0/6] Add GPU & Video Clock controller driver for SC7180
@ 2019-12-27 6:38 Taniya Das
2019-12-27 6:38 ` [PATCH v3 1/6] dt-bindings: clock: Add YAML schemas for the QCOM GPUCC clock bindings Taniya Das
` (5 more replies)
0 siblings, 6 replies; 15+ messages in thread
From: Taniya Das @ 2019-12-27 6:38 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette
Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, Andy Gross, devicetree, robh, robh+dt, Taniya Das
[v3]
* Update the clock items in Documentation binding with the GPLL0 branch names.
* Update gpu_cc_parent_data to remove .name for GCC GPLL0 source.
* Mark video_cc_xo_clk clock critical from videocc probe.
[v2]
* Split Fabia code cleanup and calibration code.
* Few cleanups for GPU/Video CC are
* header file inclusion, const for pll vco table.
* removal of always enabled clock from gpucc.
* compatibles added in sorted order.
* move from core_initcall to subsys_initcall().
* cleanup clk_parent_data for clocks to be provided from DT.
[v1]
* Fabia PLLs could fail latching in the case where the PLL is not
calibrated, so add support to calibrate in prepare clock ops.
* Add driver support for Graphics clock controller for SC7180 and also
update device tree bindings for the various clocks supported in the
clock controller.
* Add driver support for Video clock controller for SC7180 and also
update device tree bindings for the various clocks supported in the
clock controller.
Taniya Das (6):
dt-bindings: clock: Add YAML schemas for the QCOM GPUCC clock bindings
dt-bindings: clock: Introduce QCOM Graphics clock bindings
clk: qcom: Add graphics clock controller driver for SC7180
dt-bindings: clock: Add YAML schemas for the QCOM VIDEOCC clock
bindings
dt-bindings: clock: Introduce SC7180 QCOM Video clock bindings
clk: qcom: Add video clock controller driver for SC7180
.../devicetree/bindings/clock/qcom,gpucc.txt | 24 --
.../devicetree/bindings/clock/qcom,gpucc.yaml | 72 ++++++
.../devicetree/bindings/clock/qcom,videocc.txt | 18 --
.../devicetree/bindings/clock/qcom,videocc.yaml | 62 +++++
drivers/clk/qcom/Kconfig | 16 ++
drivers/clk/qcom/Makefile | 2 +
drivers/clk/qcom/gpucc-sc7180.c | 266 +++++++++++++++++++++
drivers/clk/qcom/videocc-sc7180.c | 259 ++++++++++++++++++++
include/dt-bindings/clock/qcom,gpucc-sc7180.h | 21 ++
include/dt-bindings/clock/qcom,videocc-sc7180.h | 23 ++
10 files changed, 721 insertions(+), 42 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/qcom,gpucc.txt
create mode 100644 Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
delete mode 100644 Documentation/devicetree/bindings/clock/qcom,videocc.txt
create mode 100644 Documentation/devicetree/bindings/clock/qcom,videocc.yaml
create mode 100644 drivers/clk/qcom/gpucc-sc7180.c
create mode 100644 drivers/clk/qcom/videocc-sc7180.c
create mode 100644 include/dt-bindings/clock/qcom,gpucc-sc7180.h
create mode 100644 include/dt-bindings/clock/qcom,videocc-sc7180.h
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the Linux Foundation.
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 1/6] dt-bindings: clock: Add YAML schemas for the QCOM GPUCC clock bindings
2019-12-27 6:38 [PATCH v3 0/6] Add GPU & Video Clock controller driver for SC7180 Taniya Das
@ 2019-12-27 6:38 ` Taniya Das
2020-01-04 0:33 ` Rob Herring
2020-01-05 7:26 ` Stephen Boyd
2019-12-27 6:38 ` [PATCH v3 2/6] dt-bindings: clock: Introduce QCOM Graphics " Taniya Das
` (4 subsequent siblings)
5 siblings, 2 replies; 15+ messages in thread
From: Taniya Das @ 2019-12-27 6:38 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette
Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, Andy Gross, devicetree, robh, robh+dt, Taniya Das
The GPUCC clock provider have a bunch of generic properties that
are needed in a device tree. Add a YAML schemas for those.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
---
.../devicetree/bindings/clock/qcom,gpucc.txt | 24 --------
.../devicetree/bindings/clock/qcom,gpucc.yaml | 71 ++++++++++++++++++++++
2 files changed, 71 insertions(+), 24 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/qcom,gpucc.txt
create mode 100644 Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt
deleted file mode 100644
index 269afe8a..0000000
--- a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-Qualcomm Graphics Clock & Reset Controller Binding
---------------------------------------------------
-
-Required properties :
-- compatible : shall contain "qcom,sdm845-gpucc" or "qcom,msm8998-gpucc"
-- reg : shall contain base register location and length
-- #clock-cells : from common clock binding, shall contain 1
-- #reset-cells : from common reset binding, shall contain 1
-- #power-domain-cells : from generic power domain binding, shall contain 1
-- clocks : shall contain the XO clock
- shall contain the gpll0 out main clock (msm8998)
-- clock-names : shall be "xo"
- shall be "gpll0" (msm8998)
-
-Example:
- gpucc: clock-controller@5090000 {
- compatible = "qcom,sdm845-gpucc";
- reg = <0x5090000 0x9000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
- clocks = <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "xo";
- };
diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
new file mode 100644
index 0000000..993913d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/clock/qcom,gpucc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Graphics Clock & Reset Controller Binding
+
+maintainers:
+ - Taniya Das <tdas@codeaurora.org>
+
+description: |
+ Qualcomm grpahics clock control module which supports the clocks, resets and
+ power domains.
+
+properties:
+ compatible:
+ enum:
+ - qcom,msm8998-gpucc
+ - qcom,sdm845-gpucc
+
+ clocks:
+ minItems: 1
+ maxItems: 3
+ items:
+ - description: Board XO source
+ - description: GPLL0 main branch source from GCC(gcc_gpu_gpll0_clk_src)
+ - description: GPLL0 div branch source from GCC(gcc_gpu_gpll0_div_clk_src)
+
+ clock-names:
+ minItems: 1
+ maxItems: 3
+ items:
+ - const: xo
+ - const: gpll0_main
+ - const: gpll0_div
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+ - '#power-domain-cells'
+
+examples:
+ # Example of GPUCC with clock node properties for SDM845:
+ - |
+ clock-controller@5090000 {
+ compatible = "qcom,sdm845-gpucc";
+ reg = <0x5090000 0x9000>;
+ clocks = <&rpmhcc 0>, <&gcc 31>, <&gcc 32>;
+ clock-names = "xo", "gpll0_main", "gpll0_div";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the Linux Foundation.
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 2/6] dt-bindings: clock: Introduce QCOM Graphics clock bindings
2019-12-27 6:38 [PATCH v3 0/6] Add GPU & Video Clock controller driver for SC7180 Taniya Das
2019-12-27 6:38 ` [PATCH v3 1/6] dt-bindings: clock: Add YAML schemas for the QCOM GPUCC clock bindings Taniya Das
@ 2019-12-27 6:38 ` Taniya Das
2020-01-05 7:26 ` Stephen Boyd
2019-12-27 6:38 ` [PATCH v3 3/6] clk: qcom: Add graphics clock controller driver for SC7180 Taniya Das
` (3 subsequent siblings)
5 siblings, 1 reply; 15+ messages in thread
From: Taniya Das @ 2019-12-27 6:38 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette
Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, Andy Gross, devicetree, robh, robh+dt, Taniya Das
Add device tree bindings for graphics clock controller for
Qualcomm Technology Inc's SC7180 SoCs.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/clock/qcom,gpucc.yaml | 1 +
include/dt-bindings/clock/qcom,gpucc-sc7180.h | 21 +++++++++++++++++++++
2 files changed, 22 insertions(+)
create mode 100644 include/dt-bindings/clock/qcom,gpucc-sc7180.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
index 993913d..622845a 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
@@ -17,6 +17,7 @@ properties:
compatible:
enum:
- qcom,msm8998-gpucc
+ - qcom,sc7180-gpucc
- qcom,sdm845-gpucc
clocks:
diff --git a/include/dt-bindings/clock/qcom,gpucc-sc7180.h b/include/dt-bindings/clock/qcom,gpucc-sc7180.h
new file mode 100644
index 0000000..0e4643b
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gpucc-sc7180.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SC7180_H
+#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SC7180_H
+
+#define GPU_CC_PLL1 0
+#define GPU_CC_AHB_CLK 1
+#define GPU_CC_CRC_AHB_CLK 2
+#define GPU_CC_CX_GMU_CLK 3
+#define GPU_CC_CX_SNOC_DVM_CLK 4
+#define GPU_CC_CXO_AON_CLK 5
+#define GPU_CC_CXO_CLK 6
+#define GPU_CC_GMU_CLK_SRC 7
+
+/* CAM_CC GDSCRs */
+#define CX_GDSC 0
+
+#endif
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the Linux Foundation.
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 3/6] clk: qcom: Add graphics clock controller driver for SC7180
2019-12-27 6:38 [PATCH v3 0/6] Add GPU & Video Clock controller driver for SC7180 Taniya Das
2019-12-27 6:38 ` [PATCH v3 1/6] dt-bindings: clock: Add YAML schemas for the QCOM GPUCC clock bindings Taniya Das
2019-12-27 6:38 ` [PATCH v3 2/6] dt-bindings: clock: Introduce QCOM Graphics " Taniya Das
@ 2019-12-27 6:38 ` Taniya Das
2020-01-05 7:26 ` Stephen Boyd
2019-12-27 6:38 ` [PATCH v3 4/6] dt-bindings: clock: Add YAML schemas for the QCOM VIDEOCC clock bindings Taniya Das
` (2 subsequent siblings)
5 siblings, 1 reply; 15+ messages in thread
From: Taniya Das @ 2019-12-27 6:38 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette
Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, Andy Gross, devicetree, robh, robh+dt, Taniya Das
Add support for the graphics clock controller found on SC7180
based devices. This would allow graphics drivers to probe and
control their clocks.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
---
drivers/clk/qcom/Kconfig | 8 ++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gpucc-sc7180.c | 266 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 275 insertions(+)
create mode 100644 drivers/clk/qcom/gpucc-sc7180.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 3b33ef1..e648a60 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -245,6 +245,14 @@ config SC_GCC_7180
Say Y if you want to use peripheral devices such as UART, SPI,
I2C, USB, UFS, SDCC, etc.
+config SC_GPUCC_7180
+ tristate "SC7180 Graphics Clock Controller"
+ select SC_GCC_7180
+ help
+ Support for the graphics clock controller on SC7180 devices.
+ Say Y if you want to support graphics controller devices and
+ functionality such as 3D graphics.
+
config SDM_CAMCC_845
tristate "SDM845 Camera Clock Controller"
select SDM_GCC_845
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index d899661..5477482 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_QCS_GCC_404) += gcc-qcs404.o
obj-$(CONFIG_QCS_Q6SSTOP_404) += q6sstop-qcs404.o
obj-$(CONFIG_QCS_TURING_404) += turingcc-qcs404.o
obj-$(CONFIG_SC_GCC_7180) += gcc-sc7180.o
+obj-$(CONFIG_SC_GPUCC_7180) += gpucc-sc7180.o
obj-$(CONFIG_SDM_CAMCC_845) += camcc-sdm845.o
obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o
obj-$(CONFIG_SDM_GCC_660) += gcc-sdm660.o
diff --git a/drivers/clk/qcom/gpucc-sc7180.c b/drivers/clk/qcom/gpucc-sc7180.c
new file mode 100644
index 0000000..ec61194
--- /dev/null
+++ b/drivers/clk/qcom/gpucc-sc7180.c
@@ -0,0 +1,266 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,gpucc-sc7180.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "common.h"
+#include "gdsc.h"
+
+#define CX_GMU_CBCR_SLEEP_MASK 0xF
+#define CX_GMU_CBCR_SLEEP_SHIFT 4
+#define CX_GMU_CBCR_WAKE_MASK 0xF
+#define CX_GMU_CBCR_WAKE_SHIFT 8
+#define CLK_DIS_WAIT_SHIFT 12
+#define CLK_DIS_WAIT_MASK (0xf << CLK_DIS_WAIT_SHIFT)
+
+enum {
+ P_BI_TCXO,
+ P_CORE_BI_PLL_TEST_SE,
+ P_GPLL0_OUT_MAIN,
+ P_GPLL0_OUT_MAIN_DIV,
+ P_GPU_CC_PLL1_OUT_EVEN,
+ P_GPU_CC_PLL1_OUT_MAIN,
+ P_GPU_CC_PLL1_OUT_ODD,
+};
+
+static const struct pll_vco fabia_vco[] = {
+ { 249600000, 2000000000, 0 },
+};
+
+static struct clk_alpha_pll gpu_cc_pll1 = {
+ .offset = 0x100,
+ .vco_table = fabia_vco,
+ .num_vco = ARRAY_SIZE(fabia_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "gpu_cc_pll1",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "bi_tcxo",
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_fabia_ops,
+ },
+ },
+};
+
+static const struct parent_map gpu_cc_parent_map_0[] = {
+ { P_BI_TCXO, 0 },
+ { P_GPU_CC_PLL1_OUT_MAIN, 3 },
+ { P_GPLL0_OUT_MAIN, 5 },
+ { P_GPLL0_OUT_MAIN_DIV, 6 },
+ { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const struct clk_parent_data gpu_cc_parent_data_0[] = {
+ { .fw_name = "bi_tcxo" },
+ { .hw = &gpu_cc_pll1.clkr.hw },
+ { .fw_name = "gcc_gpu_gpll0_clk_src" },
+ { .fw_name = "gcc_gpu_gpll0_div_clk_src" },
+ { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
+};
+
+static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gpu_cc_gmu_clk_src = {
+ .cmd_rcgr = 0x1120,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gpu_cc_parent_map_0,
+ .freq_tbl = ftbl_gpu_cc_gmu_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpu_cc_gmu_clk_src",
+ .parent_data = gpu_cc_parent_data_0,
+ .num_parents = 5,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_branch gpu_cc_crc_ahb_clk = {
+ .halt_reg = 0x107c,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x107c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpu_cc_crc_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_cx_gmu_clk = {
+ .halt_reg = 0x1098,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1098,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpu_cc_cx_gmu_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gpu_cc_gmu_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
+ .halt_reg = 0x108c,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x108c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpu_cc_cx_snoc_dvm_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_cxo_aon_clk = {
+ .halt_reg = 0x1004,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x1004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpu_cc_cxo_aon_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_cxo_clk = {
+ .halt_reg = 0x109c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x109c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpu_cc_cxo_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct gdsc cx_gdsc = {
+ .gdscr = 0x106c,
+ .gds_hw_ctrl = 0x1540,
+ .pd = {
+ .name = "cx_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = VOTABLE,
+};
+
+static struct gdsc *gpu_cc_sc7180_gdscs[] = {
+ [CX_GDSC] = &cx_gdsc,
+};
+
+static struct clk_regmap *gpu_cc_sc7180_clocks[] = {
+ [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
+ [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
+ [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
+ [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
+ [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
+ [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
+ [GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
+};
+
+static const struct regmap_config gpu_cc_sc7180_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x8008,
+ .fast_io = true,
+};
+
+static const struct qcom_cc_desc gpu_cc_sc7180_desc = {
+ .config = &gpu_cc_sc7180_regmap_config,
+ .clks = gpu_cc_sc7180_clocks,
+ .num_clks = ARRAY_SIZE(gpu_cc_sc7180_clocks),
+ .gdscs = gpu_cc_sc7180_gdscs,
+ .num_gdscs = ARRAY_SIZE(gpu_cc_sc7180_gdscs),
+};
+
+static const struct of_device_id gpu_cc_sc7180_match_table[] = {
+ { .compatible = "qcom,sc7180-gpucc" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, gpu_cc_sc7180_match_table);
+
+static int gpu_cc_sc7180_probe(struct platform_device *pdev)
+{
+ struct regmap *regmap;
+ struct alpha_pll_config gpu_cc_pll_config = {};
+ unsigned int value, mask;
+
+ regmap = qcom_cc_map(pdev, &gpu_cc_sc7180_desc);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ /* 360MHz Configuration */
+ gpu_cc_pll_config.l = 0x12;
+ gpu_cc_pll_config.alpha = 0xc000;
+ gpu_cc_pll_config.config_ctl_val = 0x20485699;
+ gpu_cc_pll_config.config_ctl_hi_val = 0x00002067;
+ gpu_cc_pll_config.user_ctl_val = 0x00000001;
+ gpu_cc_pll_config.user_ctl_hi_val = 0x00004805;
+ gpu_cc_pll_config.test_ctl_hi_val = 0x40000000;
+
+ clk_fabia_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll_config);
+
+ /* Recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */
+ mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;
+ mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
+ value = 0xF << CX_GMU_CBCR_WAKE_SHIFT | 0xF << CX_GMU_CBCR_SLEEP_SHIFT;
+ regmap_update_bits(regmap, 0x1098, mask, value);
+
+ /* Configure clk_dis_wait for gpu_cx_gdsc */
+ regmap_update_bits(regmap, 0x106c, CLK_DIS_WAIT_MASK,
+ 8 << CLK_DIS_WAIT_SHIFT);
+
+ return qcom_cc_really_probe(pdev, &gpu_cc_sc7180_desc, regmap);
+}
+
+static struct platform_driver gpu_cc_sc7180_driver = {
+ .probe = gpu_cc_sc7180_probe,
+ .driver = {
+ .name = "sc7180-gpucc",
+ .of_match_table = gpu_cc_sc7180_match_table,
+ },
+};
+
+static int __init gpu_cc_sc7180_init(void)
+{
+ return platform_driver_register(&gpu_cc_sc7180_driver);
+}
+subsys_initcall(gpu_cc_sc7180_init);
+
+static void __exit gpu_cc_sc7180_exit(void)
+{
+ platform_driver_unregister(&gpu_cc_sc7180_driver);
+}
+module_exit(gpu_cc_sc7180_exit);
+
+MODULE_DESCRIPTION("QTI GPU_CC SC7180 Driver");
+MODULE_LICENSE("GPL v2");
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the Linux Foundation.
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 4/6] dt-bindings: clock: Add YAML schemas for the QCOM VIDEOCC clock bindings
2019-12-27 6:38 [PATCH v3 0/6] Add GPU & Video Clock controller driver for SC7180 Taniya Das
` (2 preceding siblings ...)
2019-12-27 6:38 ` [PATCH v3 3/6] clk: qcom: Add graphics clock controller driver for SC7180 Taniya Das
@ 2019-12-27 6:38 ` Taniya Das
2020-01-05 7:26 ` Stephen Boyd
2019-12-27 6:38 ` [PATCH v3 5/6] dt-bindings: clock: Introduce SC7180 QCOM Video " Taniya Das
2019-12-27 6:38 ` [PATCH v3 6/6] clk: qcom: Add video clock controller driver for SC7180 Taniya Das
5 siblings, 1 reply; 15+ messages in thread
From: Taniya Das @ 2019-12-27 6:38 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette
Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, Andy Gross, devicetree, robh, robh+dt, Taniya Das
The VIDEOCC clock provider have a bunch of generic properties that
are needed in a device tree. Add a YAML schemas for those.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/clock/qcom,videocc.txt | 18 -------
.../devicetree/bindings/clock/qcom,videocc.yaml | 61 ++++++++++++++++++++++
2 files changed, 61 insertions(+), 18 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/qcom,videocc.txt
create mode 100644 Documentation/devicetree/bindings/clock/qcom,videocc.yaml
diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.txt b/Documentation/devicetree/bindings/clock/qcom,videocc.txt
deleted file mode 100644
index 8a8622c..0000000
--- a/Documentation/devicetree/bindings/clock/qcom,videocc.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-Qualcomm Video Clock & Reset Controller Binding
------------------------------------------------
-
-Required properties :
-- compatible : shall contain "qcom,sdm845-videocc"
-- reg : shall contain base register location and length
-- #clock-cells : from common clock binding, shall contain 1.
-- #power-domain-cells : from generic power domain binding, shall contain 1.
-- #reset-cells : from common reset binding, shall contain 1.
-
-Example:
- videocc: clock-controller@ab00000 {
- compatible = "qcom,sdm845-videocc";
- reg = <0xab00000 0x10000>;
- #clock-cells = <1>;
- #power-domain-cells = <1>;
- #reset-cells = <1>;
- };
diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml
new file mode 100644
index 0000000..fc3fcca
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/clock/qcom,videocc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Video Clock & Reset Controller Binding
+
+maintainers:
+ - Taniya Das <tdas@codeaurora.org>
+
+description: |
+ Qualcomm video clock control module which supports the clocks, resets and
+ power domains.
+
+properties:
+ compatible:
+ enum:
+ - qcom,sdm845-videocc
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: xo
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+ - '#power-domain-cells'
+
+examples:
+ # Example of VIDEOCC with clock node properties for SDM845:
+ - |
+ clock-controller@ab00000 {
+ compatible = "qcom,sdm845-videocc";
+ reg = <0xab00000 0x10000>;
+ clocks = <&rpmhcc 0>;
+ clock-names = "xo";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the Linux Foundation.
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 5/6] dt-bindings: clock: Introduce SC7180 QCOM Video clock bindings
2019-12-27 6:38 [PATCH v3 0/6] Add GPU & Video Clock controller driver for SC7180 Taniya Das
` (3 preceding siblings ...)
2019-12-27 6:38 ` [PATCH v3 4/6] dt-bindings: clock: Add YAML schemas for the QCOM VIDEOCC clock bindings Taniya Das
@ 2019-12-27 6:38 ` Taniya Das
2020-01-05 7:26 ` Stephen Boyd
2019-12-27 6:38 ` [PATCH v3 6/6] clk: qcom: Add video clock controller driver for SC7180 Taniya Das
5 siblings, 1 reply; 15+ messages in thread
From: Taniya Das @ 2019-12-27 6:38 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette
Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, Andy Gross, devicetree, robh, robh+dt, Taniya Das
Add device tree bindings for video clock controller for
Qualcomm Technology Inc's SC7180 SoCs.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/clock/qcom,videocc.yaml | 1 +
include/dt-bindings/clock/qcom,videocc-sc7180.h | 23 ++++++++++++++++++++++
2 files changed, 24 insertions(+)
create mode 100644 include/dt-bindings/clock/qcom,videocc-sc7180.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml
index fc3fcca..43cfc89 100644
--- a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml
@@ -16,6 +16,7 @@ description: |
properties:
compatible:
enum:
+ - qcom,sc7180-videocc
- qcom,sdm845-videocc
clocks:
diff --git a/include/dt-bindings/clock/qcom,videocc-sc7180.h b/include/dt-bindings/clock/qcom,videocc-sc7180.h
new file mode 100644
index 0000000..7acaf13
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,videocc-sc7180.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SC7180_H
+#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SC7180_H
+
+/* VIDEO_CC clocks */
+#define VIDEO_PLL0 0
+#define VIDEO_CC_VCODEC0_AXI_CLK 1
+#define VIDEO_CC_VCODEC0_CORE_CLK 2
+#define VIDEO_CC_VENUS_AHB_CLK 3
+#define VIDEO_CC_VENUS_CLK_SRC 4
+#define VIDEO_CC_VENUS_CTL_AXI_CLK 5
+#define VIDEO_CC_VENUS_CTL_CORE_CLK 6
+#define VIDEO_CC_XO_CLK 7
+
+/* VIDEO_CC GDSCRs */
+#define VENUS_GDSC 0
+#define VCODEC0_GDSC 1
+
+#endif
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the Linux Foundation.
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 6/6] clk: qcom: Add video clock controller driver for SC7180
2019-12-27 6:38 [PATCH v3 0/6] Add GPU & Video Clock controller driver for SC7180 Taniya Das
` (4 preceding siblings ...)
2019-12-27 6:38 ` [PATCH v3 5/6] dt-bindings: clock: Introduce SC7180 QCOM Video " Taniya Das
@ 2019-12-27 6:38 ` Taniya Das
2019-12-29 17:33 ` Stanimir Varbanov
2020-01-05 7:26 ` Stephen Boyd
5 siblings, 2 replies; 15+ messages in thread
From: Taniya Das @ 2019-12-27 6:38 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette
Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, Andy Gross, devicetree, robh, robh+dt, Taniya Das
Add support for the video clock controller found on SC7180
based devices. This would allow video drivers to probe
and control their clocks.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
---
drivers/clk/qcom/Kconfig | 8 ++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/videocc-sc7180.c | 259 ++++++++++++++++++++++++++++++++++++++
3 files changed, 268 insertions(+)
create mode 100644 drivers/clk/qcom/videocc-sc7180.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index e648a60..cf21d5c 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -253,6 +253,14 @@ config SC_GPUCC_7180
Say Y if you want to support graphics controller devices and
functionality such as 3D graphics.
+config SC_VIDEOCC_7180
+ tristate "SC7180 Video Clock Controller"
+ select SC_GCC_7180
+ help
+ Support for the video clock controller on SC7180 devices.
+ Say Y if you want to support video devices and functionality such as
+ video encode and decode.
+
config SDM_CAMCC_845
tristate "SDM845 Camera Clock Controller"
select SDM_GCC_845
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 5477482..4cdd08f 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_QCS_Q6SSTOP_404) += q6sstop-qcs404.o
obj-$(CONFIG_QCS_TURING_404) += turingcc-qcs404.o
obj-$(CONFIG_SC_GCC_7180) += gcc-sc7180.o
obj-$(CONFIG_SC_GPUCC_7180) += gpucc-sc7180.o
+obj-$(CONFIG_SC_VIDEOCC_7180) += videocc-sc7180.o
obj-$(CONFIG_SDM_CAMCC_845) += camcc-sdm845.o
obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o
obj-$(CONFIG_SDM_GCC_660) += gcc-sdm660.o
diff --git a/drivers/clk/qcom/videocc-sc7180.c b/drivers/clk/qcom/videocc-sc7180.c
new file mode 100644
index 0000000..76add30
--- /dev/null
+++ b/drivers/clk/qcom/videocc-sc7180.c
@@ -0,0 +1,259 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,videocc-sc7180.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "common.h"
+#include "gdsc.h"
+
+enum {
+ P_BI_TCXO,
+ P_CHIP_SLEEP_CLK,
+ P_CORE_BI_PLL_TEST_SE,
+ P_VIDEO_PLL0_OUT_EVEN,
+ P_VIDEO_PLL0_OUT_MAIN,
+ P_VIDEO_PLL0_OUT_ODD,
+};
+
+static const struct pll_vco fabia_vco[] = {
+ { 249600000, 2000000000, 0 },
+};
+
+static struct clk_alpha_pll video_pll0 = {
+ .offset = 0x42c,
+ .vco_table = fabia_vco,
+ .num_vco = ARRAY_SIZE(fabia_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "video_pll0",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "bi_tcxo",
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_fabia_ops,
+ },
+ },
+};
+
+static const struct parent_map video_cc_parent_map_1[] = {
+ { P_BI_TCXO, 0 },
+ { P_VIDEO_PLL0_OUT_MAIN, 1 },
+ { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const struct clk_parent_data video_cc_parent_data_1[] = {
+ { .fw_name = "bi_tcxo" },
+ { .hw = &video_pll0.clkr.hw },
+ { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
+};
+
+static const struct freq_tbl ftbl_video_cc_venus_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(150000000, P_VIDEO_PLL0_OUT_MAIN, 4, 0, 0),
+ F(270000000, P_VIDEO_PLL0_OUT_MAIN, 2.5, 0, 0),
+ F(340000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
+ F(434000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
+ F(500000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 video_cc_venus_clk_src = {
+ .cmd_rcgr = 0x7f0,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = video_cc_parent_map_1,
+ .freq_tbl = ftbl_video_cc_venus_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "video_cc_venus_clk_src",
+ .parent_data = video_cc_parent_data_1,
+ .num_parents = 3,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_branch video_cc_vcodec0_axi_clk = {
+ .halt_reg = 0x9ec,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x9ec,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "video_cc_vcodec0_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch video_cc_vcodec0_core_clk = {
+ .halt_reg = 0x890,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x890,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "video_cc_vcodec0_core_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &video_cc_venus_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch video_cc_venus_ahb_clk = {
+ .halt_reg = 0xa4c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xa4c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "video_cc_venus_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch video_cc_venus_ctl_axi_clk = {
+ .halt_reg = 0x9cc,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x9cc,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "video_cc_venus_ctl_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch video_cc_venus_ctl_core_clk = {
+ .halt_reg = 0x850,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x850,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "video_cc_venus_ctl_core_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &video_cc_venus_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct gdsc venus_gdsc = {
+ .gdscr = 0x814,
+ .pd = {
+ .name = "venus_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc vcodec0_gdsc = {
+ .gdscr = 0x874,
+ .pd = {
+ .name = "vcodec0_gdsc",
+ },
+ .flags = HW_CTRL,
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct clk_regmap *video_cc_sc7180_clocks[] = {
+ [VIDEO_CC_VCODEC0_AXI_CLK] = &video_cc_vcodec0_axi_clk.clkr,
+ [VIDEO_CC_VCODEC0_CORE_CLK] = &video_cc_vcodec0_core_clk.clkr,
+ [VIDEO_CC_VENUS_AHB_CLK] = &video_cc_venus_ahb_clk.clkr,
+ [VIDEO_CC_VENUS_CLK_SRC] = &video_cc_venus_clk_src.clkr,
+ [VIDEO_CC_VENUS_CTL_AXI_CLK] = &video_cc_venus_ctl_axi_clk.clkr,
+ [VIDEO_CC_VENUS_CTL_CORE_CLK] = &video_cc_venus_ctl_core_clk.clkr,
+ [VIDEO_PLL0] = &video_pll0.clkr,
+};
+
+static struct gdsc *video_cc_sc7180_gdscs[] = {
+ [VENUS_GDSC] = &venus_gdsc,
+ [VCODEC0_GDSC] = &vcodec0_gdsc,
+};
+
+static const struct regmap_config video_cc_sc7180_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0xb94,
+ .fast_io = true,
+};
+
+static const struct qcom_cc_desc video_cc_sc7180_desc = {
+ .config = &video_cc_sc7180_regmap_config,
+ .clks = video_cc_sc7180_clocks,
+ .num_clks = ARRAY_SIZE(video_cc_sc7180_clocks),
+ .gdscs = video_cc_sc7180_gdscs,
+ .num_gdscs = ARRAY_SIZE(video_cc_sc7180_gdscs),
+};
+
+static const struct of_device_id video_cc_sc7180_match_table[] = {
+ { .compatible = "qcom,sc7180-videocc" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, video_cc_sc7180_match_table);
+
+static int video_cc_sc7180_probe(struct platform_device *pdev)
+{
+ struct regmap *regmap;
+ struct alpha_pll_config video_pll0_config = {};
+
+ regmap = qcom_cc_map(pdev, &video_cc_sc7180_desc);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ video_pll0_config.l = 0x1f;
+ video_pll0_config.alpha = 0x4000;
+ video_pll0_config.user_ctl_val = 0x00000001;
+ video_pll0_config.user_ctl_hi_val = 0x00004805;
+
+ clk_fabia_pll_configure(&video_pll0, regmap, &video_pll0_config);
+
+ /* Keep VIDEO_CC_XO_CLK ALWAYS-ON */
+ regmap_update_bits(regmap, 0x984, 0x1, 0x1);
+
+ return qcom_cc_really_probe(pdev, &video_cc_sc7180_desc, regmap);
+}
+
+static struct platform_driver video_cc_sc7180_driver = {
+ .probe = video_cc_sc7180_probe,
+ .driver = {
+ .name = "sc7180-videocc",
+ .of_match_table = video_cc_sc7180_match_table,
+ },
+};
+
+static int __init video_cc_sc7180_init(void)
+{
+ return platform_driver_register(&video_cc_sc7180_driver);
+}
+subsys_initcall(video_cc_sc7180_init);
+
+static void __exit video_cc_sc7180_exit(void)
+{
+ platform_driver_unregister(&video_cc_sc7180_driver);
+}
+module_exit(video_cc_sc7180_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("QTI VIDEOCC SC7180 Driver");
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the Linux Foundation.
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v3 6/6] clk: qcom: Add video clock controller driver for SC7180
2019-12-27 6:38 ` [PATCH v3 6/6] clk: qcom: Add video clock controller driver for SC7180 Taniya Das
@ 2019-12-29 17:33 ` Stanimir Varbanov
2020-01-05 7:26 ` Stephen Boyd
1 sibling, 0 replies; 15+ messages in thread
From: Stanimir Varbanov @ 2019-12-29 17:33 UTC (permalink / raw)
To: Taniya Das, Stephen Boyd, Michael Turquette
Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, Andy Gross, devicetree, robh, robh+dt
Hi Taniya,
On 12/27/19 8:38 AM, Taniya Das wrote:
> Add support for the video clock controller found on SC7180
> based devices. This would allow video drivers to probe
> and control their clocks.
>
> Signed-off-by: Taniya Das <tdas@codeaurora.org>
> ---
> drivers/clk/qcom/Kconfig | 8 ++
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/videocc-sc7180.c | 259 ++++++++++++++++++++++++++++++++++++++
> 3 files changed, 268 insertions(+)
> create mode 100644 drivers/clk/qcom/videocc-sc7180.c
>
<cut>
> +static const struct freq_tbl ftbl_video_cc_venus_clk_src[] = {
> + F(19200000, P_BI_TCXO, 1, 0, 0),
Do you know is this frequency (19.2MHz) has real usage? The lower freq
I've seen for Venus was 75MHz.
> + F(150000000, P_VIDEO_PLL0_OUT_MAIN, 4, 0, 0),
> + F(270000000, P_VIDEO_PLL0_OUT_MAIN, 2.5, 0, 0),
> + F(340000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
> + F(434000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
> + F(500000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
> + { }
> +};
> +
--
regards,
Stan
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 1/6] dt-bindings: clock: Add YAML schemas for the QCOM GPUCC clock bindings
2019-12-27 6:38 ` [PATCH v3 1/6] dt-bindings: clock: Add YAML schemas for the QCOM GPUCC clock bindings Taniya Das
@ 2020-01-04 0:33 ` Rob Herring
2020-01-05 7:26 ` Stephen Boyd
1 sibling, 0 replies; 15+ messages in thread
From: Rob Herring @ 2020-01-04 0:33 UTC (permalink / raw)
To: Taniya Das
Cc: Stephen Boyd, Michael Turquette ,
David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, Andy Gross, devicetree, robh, robh+dt, Taniya Das
On Fri, 27 Dec 2019 12:08:29 +0530, Taniya Das wrote:
> The GPUCC clock provider have a bunch of generic properties that
> are needed in a device tree. Add a YAML schemas for those.
>
> Signed-off-by: Taniya Das <tdas@codeaurora.org>
> ---
> .../devicetree/bindings/clock/qcom,gpucc.txt | 24 --------
> .../devicetree/bindings/clock/qcom,gpucc.yaml | 71 ++++++++++++++++++++++
> 2 files changed, 71 insertions(+), 24 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/qcom,gpucc.txt
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 1/6] dt-bindings: clock: Add YAML schemas for the QCOM GPUCC clock bindings
2019-12-27 6:38 ` [PATCH v3 1/6] dt-bindings: clock: Add YAML schemas for the QCOM GPUCC clock bindings Taniya Das
2020-01-04 0:33 ` Rob Herring
@ 2020-01-05 7:26 ` Stephen Boyd
1 sibling, 0 replies; 15+ messages in thread
From: Stephen Boyd @ 2020-01-05 7:26 UTC (permalink / raw)
To: Michael Turquette, Taniya Das
Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, Andy Gross, devicetree, robh, robh+dt, Taniya Das
Quoting Taniya Das (2019-12-26 22:38:29)
> The GPUCC clock provider have a bunch of generic properties that
> are needed in a device tree. Add a YAML schemas for those.
>
> Signed-off-by: Taniya Das <tdas@codeaurora.org>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 2/6] dt-bindings: clock: Introduce QCOM Graphics clock bindings
2019-12-27 6:38 ` [PATCH v3 2/6] dt-bindings: clock: Introduce QCOM Graphics " Taniya Das
@ 2020-01-05 7:26 ` Stephen Boyd
0 siblings, 0 replies; 15+ messages in thread
From: Stephen Boyd @ 2020-01-05 7:26 UTC (permalink / raw)
To: Michael Turquette, Taniya Das
Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, Andy Gross, devicetree, robh, robh+dt, Taniya Das
Quoting Taniya Das (2019-12-26 22:38:30)
> Add device tree bindings for graphics clock controller for
> Qualcomm Technology Inc's SC7180 SoCs.
>
> Signed-off-by: Taniya Das <tdas@codeaurora.org>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 3/6] clk: qcom: Add graphics clock controller driver for SC7180
2019-12-27 6:38 ` [PATCH v3 3/6] clk: qcom: Add graphics clock controller driver for SC7180 Taniya Das
@ 2020-01-05 7:26 ` Stephen Boyd
0 siblings, 0 replies; 15+ messages in thread
From: Stephen Boyd @ 2020-01-05 7:26 UTC (permalink / raw)
To: Michael Turquette, Taniya Das
Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, Andy Gross, devicetree, robh, robh+dt, Taniya Das
Quoting Taniya Das (2019-12-26 22:38:31)
> Add support for the graphics clock controller found on SC7180
> based devices. This would allow graphics drivers to probe and
> control their clocks.
>
> Signed-off-by: Taniya Das <tdas@codeaurora.org>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 4/6] dt-bindings: clock: Add YAML schemas for the QCOM VIDEOCC clock bindings
2019-12-27 6:38 ` [PATCH v3 4/6] dt-bindings: clock: Add YAML schemas for the QCOM VIDEOCC clock bindings Taniya Das
@ 2020-01-05 7:26 ` Stephen Boyd
0 siblings, 0 replies; 15+ messages in thread
From: Stephen Boyd @ 2020-01-05 7:26 UTC (permalink / raw)
To: Michael Turquette, Taniya Das
Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, Andy Gross, devicetree, robh, robh+dt, Taniya Das
Quoting Taniya Das (2019-12-26 22:38:32)
> The VIDEOCC clock provider have a bunch of generic properties that
> are needed in a device tree. Add a YAML schemas for those.
>
> Signed-off-by: Taniya Das <tdas@codeaurora.org>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 5/6] dt-bindings: clock: Introduce SC7180 QCOM Video clock bindings
2019-12-27 6:38 ` [PATCH v3 5/6] dt-bindings: clock: Introduce SC7180 QCOM Video " Taniya Das
@ 2020-01-05 7:26 ` Stephen Boyd
0 siblings, 0 replies; 15+ messages in thread
From: Stephen Boyd @ 2020-01-05 7:26 UTC (permalink / raw)
To: Michael Turquette, Taniya Das
Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, Andy Gross, devicetree, robh, robh+dt, Taniya Das
Quoting Taniya Das (2019-12-26 22:38:33)
> Add device tree bindings for video clock controller for
> Qualcomm Technology Inc's SC7180 SoCs.
>
> Signed-off-by: Taniya Das <tdas@codeaurora.org>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 6/6] clk: qcom: Add video clock controller driver for SC7180
2019-12-27 6:38 ` [PATCH v3 6/6] clk: qcom: Add video clock controller driver for SC7180 Taniya Das
2019-12-29 17:33 ` Stanimir Varbanov
@ 2020-01-05 7:26 ` Stephen Boyd
1 sibling, 0 replies; 15+ messages in thread
From: Stephen Boyd @ 2020-01-05 7:26 UTC (permalink / raw)
To: Michael Turquette, Taniya Das
Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, Andy Gross, devicetree, robh, robh+dt, Taniya Das
Quoting Taniya Das (2019-12-26 22:38:34)
> Add support for the video clock controller found on SC7180
> based devices. This would allow video drivers to probe
> and control their clocks.
>
> Signed-off-by: Taniya Das <tdas@codeaurora.org>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2020-01-05 7:26 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-12-27 6:38 [PATCH v3 0/6] Add GPU & Video Clock controller driver for SC7180 Taniya Das
2019-12-27 6:38 ` [PATCH v3 1/6] dt-bindings: clock: Add YAML schemas for the QCOM GPUCC clock bindings Taniya Das
2020-01-04 0:33 ` Rob Herring
2020-01-05 7:26 ` Stephen Boyd
2019-12-27 6:38 ` [PATCH v3 2/6] dt-bindings: clock: Introduce QCOM Graphics " Taniya Das
2020-01-05 7:26 ` Stephen Boyd
2019-12-27 6:38 ` [PATCH v3 3/6] clk: qcom: Add graphics clock controller driver for SC7180 Taniya Das
2020-01-05 7:26 ` Stephen Boyd
2019-12-27 6:38 ` [PATCH v3 4/6] dt-bindings: clock: Add YAML schemas for the QCOM VIDEOCC clock bindings Taniya Das
2020-01-05 7:26 ` Stephen Boyd
2019-12-27 6:38 ` [PATCH v3 5/6] dt-bindings: clock: Introduce SC7180 QCOM Video " Taniya Das
2020-01-05 7:26 ` Stephen Boyd
2019-12-27 6:38 ` [PATCH v3 6/6] clk: qcom: Add video clock controller driver for SC7180 Taniya Das
2019-12-29 17:33 ` Stanimir Varbanov
2020-01-05 7:26 ` Stephen Boyd
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