* [PATCH 1/3] perf/x86/intel: Add Elkhart Lake support
@ 2020-01-28 18:31 kan.liang
2020-01-28 18:31 ` [PATCH 2/3] perf/x86/cstate: Add Tremont support kan.liang
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: kan.liang @ 2020-01-28 18:31 UTC (permalink / raw)
To: peterz, mingo, linux-kernel; +Cc: ak, Kan Liang
From: Kan Liang <kan.liang@linux.intel.com>
Elkhart Lake also uses Tremont CPU. From the perspective of Intel PMU,
there is nothing changed compared with Jacobsville.
Share the perf code with Jacobsville.
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
arch/x86/events/intel/core.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index f43ec24..b5b04164 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -4746,6 +4746,7 @@ __init int intel_pmu_init(void)
break;
case INTEL_FAM6_ATOM_TREMONT_D:
+ case INTEL_FAM6_ATOM_TREMONT:
x86_pmu.late_ack = true;
memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
sizeof(hw_cache_event_ids));
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 2/3] perf/x86/cstate: Add Tremont support 2020-01-28 18:31 [PATCH 1/3] perf/x86/intel: Add Elkhart Lake support kan.liang @ 2020-01-28 18:31 ` kan.liang 2020-02-11 12:47 ` [tip: perf/core] " tip-bot2 for Kan Liang 2020-01-28 18:31 ` [PATCH 3/3] perf/x86/msr: " kan.liang 2020-02-11 12:47 ` [tip: perf/core] perf/x86/intel: Add Elkhart Lake support tip-bot2 for Kan Liang 2 siblings, 1 reply; 6+ messages in thread From: kan.liang @ 2020-01-28 18:31 UTC (permalink / raw) To: peterz, mingo, linux-kernel; +Cc: ak, Kan Liang From: Kan Liang <kan.liang@linux.intel.com> Tremont is Intel's successor to Goldmont Plus. From the perspective of Intel cstate residency counters, there is nothing changed compared with Goldmont Plus and Goldmont. Share glm_cstates with Goldmont Plus and Goldmont. Update the comments for Tremont. Reviewed-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Kan Liang <kan.liang@linux.intel.com> --- arch/x86/events/intel/cstate.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c index e1daf41..4814c96 100644 --- a/arch/x86/events/intel/cstate.c +++ b/arch/x86/events/intel/cstate.c @@ -40,17 +40,18 @@ * Model specific counters: * MSR_CORE_C1_RES: CORE C1 Residency Counter * perf code: 0x00 - * Available model: SLM,AMT,GLM,CNL + * Available model: SLM,AMT,GLM,CNL,TNT * Scope: Core (each processor core has a MSR) * MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter * perf code: 0x01 * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM, - * CNL,KBL,CML + * CNL,KBL,CML,TNT * Scope: Core * MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter * perf code: 0x02 * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW, - * SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL + * SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL, + * TNT * Scope: Core * MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter * perf code: 0x03 @@ -60,17 +61,18 @@ * MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter. * perf code: 0x00 * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL, - * KBL,CML,ICL,TGL + * KBL,CML,ICL,TGL,TNT * Scope: Package (physical package) * MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter. * perf code: 0x01 * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL, - * GLM,CNL,KBL,CML,ICL,TGL + * GLM,CNL,KBL,CML,ICL,TGL,TNT * Scope: Package (physical package) * MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter. * perf code: 0x02 - * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW - * SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL + * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW, + * SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL, + * TNT * Scope: Package (physical package) * MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter. * perf code: 0x03 @@ -87,7 +89,8 @@ * Scope: Package (physical package) * MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter. * perf code: 0x06 - * Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL + * Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL, + * TNT * Scope: Package (physical package) * */ @@ -640,8 +643,9 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT, glm_cstates), X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_D, glm_cstates), - X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_PLUS, glm_cstates), + X86_CSTATES_MODEL(INTEL_FAM6_ATOM_TREMONT_D, glm_cstates), + X86_CSTATES_MODEL(INTEL_FAM6_ATOM_TREMONT, glm_cstates), X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_L, icl_cstates), X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE, icl_cstates), -- 2.7.4 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [tip: perf/core] perf/x86/cstate: Add Tremont support 2020-01-28 18:31 ` [PATCH 2/3] perf/x86/cstate: Add Tremont support kan.liang @ 2020-02-11 12:47 ` tip-bot2 for Kan Liang 0 siblings, 0 replies; 6+ messages in thread From: tip-bot2 for Kan Liang @ 2020-02-11 12:47 UTC (permalink / raw) To: linux-tip-commits Cc: Kan Liang, Peter Zijlstra (Intel), Ingo Molnar, Andi Kleen, x86, LKML The following commit has been merged into the perf/core branch of tip: Commit-ID: ecf71fbccb9ac5cb964eb7de59bb9da3755b7885 Gitweb: https://git.kernel.org/tip/ecf71fbccb9ac5cb964eb7de59bb9da3755b7885 Author: Kan Liang <kan.liang@linux.intel.com> AuthorDate: Tue, 28 Jan 2020 10:31:18 -08:00 Committer: Ingo Molnar <mingo@kernel.org> CommitterDate: Tue, 11 Feb 2020 13:17:49 +01:00 perf/x86/cstate: Add Tremont support Tremont is Intel's successor to Goldmont Plus. From the perspective of Intel cstate residency counters, there is nothing changed compared with Goldmont Plus and Goldmont. Share glm_cstates with Goldmont Plus and Goldmont. Update the comments for Tremont. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Ingo Molnar <mingo@kernel.org> Reviewed-by: Andi Kleen <ak@linux.intel.com> Link: https://lkml.kernel.org/r/1580236279-35492-2-git-send-email-kan.liang@linux.intel.com --- arch/x86/events/intel/cstate.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c index e1daf41..4814c96 100644 --- a/arch/x86/events/intel/cstate.c +++ b/arch/x86/events/intel/cstate.c @@ -40,17 +40,18 @@ * Model specific counters: * MSR_CORE_C1_RES: CORE C1 Residency Counter * perf code: 0x00 - * Available model: SLM,AMT,GLM,CNL + * Available model: SLM,AMT,GLM,CNL,TNT * Scope: Core (each processor core has a MSR) * MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter * perf code: 0x01 * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM, - * CNL,KBL,CML + * CNL,KBL,CML,TNT * Scope: Core * MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter * perf code: 0x02 * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW, - * SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL + * SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL, + * TNT * Scope: Core * MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter * perf code: 0x03 @@ -60,17 +61,18 @@ * MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter. * perf code: 0x00 * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL, - * KBL,CML,ICL,TGL + * KBL,CML,ICL,TGL,TNT * Scope: Package (physical package) * MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter. * perf code: 0x01 * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL, - * GLM,CNL,KBL,CML,ICL,TGL + * GLM,CNL,KBL,CML,ICL,TGL,TNT * Scope: Package (physical package) * MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter. * perf code: 0x02 - * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW - * SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL + * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW, + * SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL, + * TNT * Scope: Package (physical package) * MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter. * perf code: 0x03 @@ -87,7 +89,8 @@ * Scope: Package (physical package) * MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter. * perf code: 0x06 - * Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL + * Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL, + * TNT * Scope: Package (physical package) * */ @@ -640,8 +643,9 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT, glm_cstates), X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_D, glm_cstates), - X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_PLUS, glm_cstates), + X86_CSTATES_MODEL(INTEL_FAM6_ATOM_TREMONT_D, glm_cstates), + X86_CSTATES_MODEL(INTEL_FAM6_ATOM_TREMONT, glm_cstates), X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_L, icl_cstates), X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE, icl_cstates), ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/3] perf/x86/msr: Add Tremont support 2020-01-28 18:31 [PATCH 1/3] perf/x86/intel: Add Elkhart Lake support kan.liang 2020-01-28 18:31 ` [PATCH 2/3] perf/x86/cstate: Add Tremont support kan.liang @ 2020-01-28 18:31 ` kan.liang 2020-02-11 12:47 ` [tip: perf/core] " tip-bot2 for Kan Liang 2020-02-11 12:47 ` [tip: perf/core] perf/x86/intel: Add Elkhart Lake support tip-bot2 for Kan Liang 2 siblings, 1 reply; 6+ messages in thread From: kan.liang @ 2020-01-28 18:31 UTC (permalink / raw) To: peterz, mingo, linux-kernel; +Cc: ak, Kan Liang From: Kan Liang <kan.liang@linux.intel.com> Tremont is Intel's successor to Goldmont Plus. SMI_COUNT MSR is also supported. Reviewed-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Kan Liang <kan.liang@linux.intel.com> --- arch/x86/events/msr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c index 6f86650..a949f6f 100644 --- a/arch/x86/events/msr.c +++ b/arch/x86/events/msr.c @@ -75,8 +75,9 @@ static bool test_intel(int idx, void *data) case INTEL_FAM6_ATOM_GOLDMONT: case INTEL_FAM6_ATOM_GOLDMONT_D: - case INTEL_FAM6_ATOM_GOLDMONT_PLUS: + case INTEL_FAM6_ATOM_TREMONT_D: + case INTEL_FAM6_ATOM_TREMONT: case INTEL_FAM6_XEON_PHI_KNL: case INTEL_FAM6_XEON_PHI_KNM: -- 2.7.4 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [tip: perf/core] perf/x86/msr: Add Tremont support 2020-01-28 18:31 ` [PATCH 3/3] perf/x86/msr: " kan.liang @ 2020-02-11 12:47 ` tip-bot2 for Kan Liang 0 siblings, 0 replies; 6+ messages in thread From: tip-bot2 for Kan Liang @ 2020-02-11 12:47 UTC (permalink / raw) To: linux-tip-commits Cc: Kan Liang, Peter Zijlstra (Intel), Ingo Molnar, Andi Kleen, x86, LKML The following commit has been merged into the perf/core branch of tip: Commit-ID: 0aa0e0d6b34b89649e6b5882a7e025a0eb9bd832 Gitweb: https://git.kernel.org/tip/0aa0e0d6b34b89649e6b5882a7e025a0eb9bd832 Author: Kan Liang <kan.liang@linux.intel.com> AuthorDate: Tue, 28 Jan 2020 10:31:19 -08:00 Committer: Ingo Molnar <mingo@kernel.org> CommitterDate: Tue, 11 Feb 2020 13:17:50 +01:00 perf/x86/msr: Add Tremont support Tremont is Intel's successor to Goldmont Plus. SMI_COUNT MSR is also supported. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Ingo Molnar <mingo@kernel.org> Reviewed-by: Andi Kleen <ak@linux.intel.com> Link: https://lkml.kernel.org/r/1580236279-35492-3-git-send-email-kan.liang@linux.intel.com --- arch/x86/events/msr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c index 6f86650..a949f6f 100644 --- a/arch/x86/events/msr.c +++ b/arch/x86/events/msr.c @@ -75,8 +75,9 @@ static bool test_intel(int idx, void *data) case INTEL_FAM6_ATOM_GOLDMONT: case INTEL_FAM6_ATOM_GOLDMONT_D: - case INTEL_FAM6_ATOM_GOLDMONT_PLUS: + case INTEL_FAM6_ATOM_TREMONT_D: + case INTEL_FAM6_ATOM_TREMONT: case INTEL_FAM6_XEON_PHI_KNL: case INTEL_FAM6_XEON_PHI_KNM: ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [tip: perf/core] perf/x86/intel: Add Elkhart Lake support 2020-01-28 18:31 [PATCH 1/3] perf/x86/intel: Add Elkhart Lake support kan.liang 2020-01-28 18:31 ` [PATCH 2/3] perf/x86/cstate: Add Tremont support kan.liang 2020-01-28 18:31 ` [PATCH 3/3] perf/x86/msr: " kan.liang @ 2020-02-11 12:47 ` tip-bot2 for Kan Liang 2 siblings, 0 replies; 6+ messages in thread From: tip-bot2 for Kan Liang @ 2020-02-11 12:47 UTC (permalink / raw) To: linux-tip-commits Cc: Kan Liang, Peter Zijlstra (Intel), Ingo Molnar, Andi Kleen, x86, LKML The following commit has been merged into the perf/core branch of tip: Commit-ID: eda23b387f6c4bb2971ac7e874a09913f533b22c Gitweb: https://git.kernel.org/tip/eda23b387f6c4bb2971ac7e874a09913f533b22c Author: Kan Liang <kan.liang@linux.intel.com> AuthorDate: Tue, 28 Jan 2020 10:31:17 -08:00 Committer: Ingo Molnar <mingo@kernel.org> CommitterDate: Tue, 11 Feb 2020 13:17:48 +01:00 perf/x86/intel: Add Elkhart Lake support Elkhart Lake also uses Tremont CPU. From the perspective of Intel PMU, there is nothing changed compared with Jacobsville. Share the perf code with Jacobsville. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Ingo Molnar <mingo@kernel.org> Reviewed-by: Andi Kleen <ak@linux.intel.com> Link: https://lkml.kernel.org/r/1580236279-35492-1-git-send-email-kan.liang@linux.intel.com --- arch/x86/events/intel/core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 3be51aa..dff6623 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -4765,6 +4765,7 @@ __init int intel_pmu_init(void) break; case INTEL_FAM6_ATOM_TREMONT_D: + case INTEL_FAM6_ATOM_TREMONT: x86_pmu.late_ack = true; memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, sizeof(hw_cache_event_ids)); ^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-02-11 12:50 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-01-28 18:31 [PATCH 1/3] perf/x86/intel: Add Elkhart Lake support kan.liang 2020-01-28 18:31 ` [PATCH 2/3] perf/x86/cstate: Add Tremont support kan.liang 2020-02-11 12:47 ` [tip: perf/core] " tip-bot2 for Kan Liang 2020-01-28 18:31 ` [PATCH 3/3] perf/x86/msr: " kan.liang 2020-02-11 12:47 ` [tip: perf/core] " tip-bot2 for Kan Liang 2020-02-11 12:47 ` [tip: perf/core] perf/x86/intel: Add Elkhart Lake support tip-bot2 for Kan Liang
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