* [PATCH 1/2] arm64: dts: mt8183: Add gce setting in display node
@ 2020-02-12 9:55 Bibby Hsieh
2020-02-12 9:55 ` [PATCH 2/2] drm/mediatek: move gce event property to mutex device node Bibby Hsieh
2020-02-12 10:48 ` [PATCH 1/2] arm64: dts: mt8183: Add gce setting in display node CK Hu
0 siblings, 2 replies; 6+ messages in thread
From: Bibby Hsieh @ 2020-02-12 9:55 UTC (permalink / raw)
To: David Airlie, Matthias Brugger, Daniel Vetter, dri-devel, linux-mediatek
Cc: Philipp Zabel, YT Shen, Thierry Reding, CK Hu, linux-arm-kernel,
tfiga, drinkcat, linux-kernel, srv_heupstream, Bibby Hsieh,
Yongqiang Niu
In order to use GCE function, we need add some information
into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).
Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index be4428c92f35..1f0fc281bc2d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/mt8183-power.h>
+#include <dt-bindings/gce/mt8183-gce.h>
#include "mt8183-pinfunc.h"
/ {
@@ -664,6 +665,9 @@
reg = <0 0x14000000 0 0x1000>;
power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
#clock-cells = <1>;
+ mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
+ <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
};
ovl0: ovl@14008000 {
@@ -672,6 +676,7 @@
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_OVL0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
};
ovl_2l0: ovl@14009000 {
@@ -680,6 +685,7 @@
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
};
ovl_2l1: ovl@1400a000 {
@@ -688,6 +694,7 @@
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
};
rdma0: rdma@1400b000 {
@@ -697,6 +704,7 @@
power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_RDMA0>;
mediatek,rdma_fifo_size = <5120>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
};
rdma1: rdma@1400c000 {
@@ -706,6 +714,7 @@
power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_RDMA1>;
mediatek,rdma_fifo_size = <2048>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
};
color0: color@1400e000 {
@@ -715,6 +724,7 @@
interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
};
ccorr0: ccorr@1400f000 {
@@ -723,6 +733,7 @@
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
};
aal0: aal@14010000 {
@@ -732,6 +743,7 @@
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_AAL0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
};
gamma0: gamma@14011000 {
@@ -741,6 +753,7 @@
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
};
dither0: dither@14012000 {
@@ -749,6 +762,7 @@
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
};
mutex: mutex@14016000 {
@@ -756,6 +770,8 @@
reg = <0 0x14016000 0 0x1000>;
interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
+ <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
};
smi_common: smi@14019000 {
--
2.18.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 2/2] drm/mediatek: move gce event property to mutex device node
2020-02-12 9:55 [PATCH 1/2] arm64: dts: mt8183: Add gce setting in display node Bibby Hsieh
@ 2020-02-12 9:55 ` Bibby Hsieh
2020-02-12 10:44 ` CK Hu
2020-02-12 10:48 ` [PATCH 1/2] arm64: dts: mt8183: Add gce setting in display node CK Hu
1 sibling, 1 reply; 6+ messages in thread
From: Bibby Hsieh @ 2020-02-12 9:55 UTC (permalink / raw)
To: David Airlie, Matthias Brugger, Daniel Vetter, dri-devel, linux-mediatek
Cc: Philipp Zabel, YT Shen, Thierry Reding, CK Hu, linux-arm-kernel,
tfiga, drinkcat, linux-kernel, srv_heupstream, Bibby Hsieh
According mtk hardware design, stream_done0 and stream_done1 are
generated by mutex, so we move gce event property to mutex device mode.
Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 3c53ea22208c..8a31e5b983db 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -819,7 +819,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
drm_crtc_index(&mtk_crtc->base));
mtk_crtc->cmdq_client = NULL;
}
- ret = of_property_read_u32_index(dev->of_node, "mediatek,gce-events",
+ ret = of_property_read_u32_index(priv->mutex_node, "mediatek,gce-events",
drm_crtc_index(&mtk_crtc->base),
&mtk_crtc->cmdq_event);
if (ret)
--
2.18.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] drm/mediatek: move gce event property to mutex device node
2020-02-12 9:55 ` [PATCH 2/2] drm/mediatek: move gce event property to mutex device node Bibby Hsieh
@ 2020-02-12 10:44 ` CK Hu
2020-02-18 7:59 ` CK Hu
0 siblings, 1 reply; 6+ messages in thread
From: CK Hu @ 2020-02-12 10:44 UTC (permalink / raw)
To: Bibby Hsieh
Cc: David Airlie, Matthias Brugger, Daniel Vetter, dri-devel,
linux-mediatek, Philipp Zabel, YT Shen, Thierry Reding,
linux-arm-kernel, tfiga, drinkcat, linux-kernel, srv_heupstream
Hi, Bibby:
On Wed, 2020-02-12 at 17:55 +0800, Bibby Hsieh wrote:
> According mtk hardware design, stream_done0 and stream_done1 are
> generated by mutex, so we move gce event property to mutex device mode.
>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index 3c53ea22208c..8a31e5b983db 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -819,7 +819,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> drm_crtc_index(&mtk_crtc->base));
> mtk_crtc->cmdq_client = NULL;
> }
> - ret = of_property_read_u32_index(dev->of_node, "mediatek,gce-events",
> + ret = of_property_read_u32_index(priv->mutex_node, "mediatek,gce-events",
> drm_crtc_index(&mtk_crtc->base),
> &mtk_crtc->cmdq_event);
> if (ret)
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] drm/mediatek: move gce event property to mutex device node
2020-02-12 10:44 ` CK Hu
@ 2020-02-18 7:59 ` CK Hu
0 siblings, 0 replies; 6+ messages in thread
From: CK Hu @ 2020-02-18 7:59 UTC (permalink / raw)
To: Bibby Hsieh
Cc: David Airlie, Matthias Brugger, Daniel Vetter, dri-devel,
linux-mediatek, Philipp Zabel, YT Shen, Thierry Reding,
linux-arm-kernel, tfiga, drinkcat, linux-kernel, srv_heupstream
Hi, Bibby:
On Wed, 2020-02-12 at 18:44 +0800, CK Hu wrote:
> Hi, Bibby:
>
> On Wed, 2020-02-12 at 17:55 +0800, Bibby Hsieh wrote:
> > According mtk hardware design, stream_done0 and stream_done1 are
> > generated by mutex, so we move gce event property to mutex device mode.
> >
>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
>
Applied to mediatek-drm-fixes-5.6 [1], thanks.
[1]
https://github.com/ckhu-mediatek/linux.git-tags/commits/mediatek-drm-fixes-5.6
Regards,
CK
> > Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > index 3c53ea22208c..8a31e5b983db 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > @@ -819,7 +819,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > drm_crtc_index(&mtk_crtc->base));
> > mtk_crtc->cmdq_client = NULL;
> > }
> > - ret = of_property_read_u32_index(dev->of_node, "mediatek,gce-events",
> > + ret = of_property_read_u32_index(priv->mutex_node, "mediatek,gce-events",
> > drm_crtc_index(&mtk_crtc->base),
> > &mtk_crtc->cmdq_event);
> > if (ret)
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] arm64: dts: mt8183: Add gce setting in display node
2020-02-12 9:55 [PATCH 1/2] arm64: dts: mt8183: Add gce setting in display node Bibby Hsieh
2020-02-12 9:55 ` [PATCH 2/2] drm/mediatek: move gce event property to mutex device node Bibby Hsieh
@ 2020-02-12 10:48 ` CK Hu
2020-02-13 1:26 ` Bibby Hsieh
1 sibling, 1 reply; 6+ messages in thread
From: CK Hu @ 2020-02-12 10:48 UTC (permalink / raw)
To: Bibby Hsieh
Cc: David Airlie, Matthias Brugger, Daniel Vetter, dri-devel,
linux-mediatek, Philipp Zabel, YT Shen, Thierry Reding,
linux-arm-kernel, tfiga, drinkcat, linux-kernel, srv_heupstream,
Yongqiang Niu
On Wed, 2020-02-12 at 17:55 +0800, Bibby Hsieh wrote:
> In order to use GCE function, we need add some information
> into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).
>
> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index be4428c92f35..1f0fc281bc2d 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -9,6 +9,7 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/power/mt8183-power.h>
> +#include <dt-bindings/gce/mt8183-gce.h>
> #include "mt8183-pinfunc.h"
>
> / {
> @@ -664,6 +665,9 @@
> reg = <0 0x14000000 0 0x1000>;
> power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> #clock-cells = <1>;
> + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
I would like to remove atomic parameter, so please follow [1] to remove
it.
[1] https://patchwork.kernel.org/patch/10765419/
Regards,
CK
> + <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
> };
>
> ovl0: ovl@14008000 {
> @@ -672,6 +676,7 @@
> interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_OVL0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
> };
>
> ovl_2l0: ovl@14009000 {
> @@ -680,6 +685,7 @@
> interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
> };
>
> ovl_2l1: ovl@1400a000 {
> @@ -688,6 +694,7 @@
> interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
> };
>
> rdma0: rdma@1400b000 {
> @@ -697,6 +704,7 @@
> power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> mediatek,rdma_fifo_size = <5120>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
> };
>
> rdma1: rdma@1400c000 {
> @@ -706,6 +714,7 @@
> power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_RDMA1>;
> mediatek,rdma_fifo_size = <2048>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
> };
>
> color0: color@1400e000 {
> @@ -715,6 +724,7 @@
> interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
> };
>
> ccorr0: ccorr@1400f000 {
> @@ -723,6 +733,7 @@
> interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
> };
>
> aal0: aal@14010000 {
> @@ -732,6 +743,7 @@
> interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_AAL0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
> };
>
> gamma0: gamma@14011000 {
> @@ -741,6 +753,7 @@
> interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
> };
>
> dither0: dither@14012000 {
> @@ -749,6 +762,7 @@
> interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
> };
>
> mutex: mutex@14016000 {
> @@ -756,6 +770,8 @@
> reg = <0 0x14016000 0 0x1000>;
> interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> + mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
> + <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
> };
>
> smi_common: smi@14019000 {
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH 1/2] arm64: dts: mt8183: Add gce setting in display node
2020-02-12 10:48 ` [PATCH 1/2] arm64: dts: mt8183: Add gce setting in display node CK Hu
@ 2020-02-13 1:26 ` Bibby Hsieh
0 siblings, 0 replies; 6+ messages in thread
From: Bibby Hsieh @ 2020-02-13 1:26 UTC (permalink / raw)
To: CK Hu
Cc: David Airlie, Matthias Brugger, Daniel Vetter, dri-devel,
linux-mediatek, Philipp Zabel, YT Shen, Thierry Reding,
linux-arm-kernel, tfiga, drinkcat, linux-kernel, srv_heupstream,
Yongqiang Niu
On Wed, 2020-02-12 at 18:48 +0800, CK Hu wrote:
> On Wed, 2020-02-12 at 17:55 +0800, Bibby Hsieh wrote:
> > In order to use GCE function, we need add some information
> > into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).
> >
> > Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16 ++++++++++++++++
> > 1 file changed, 16 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > index be4428c92f35..1f0fc281bc2d 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > @@ -9,6 +9,7 @@
> > #include <dt-bindings/interrupt-controller/arm-gic.h>
> > #include <dt-bindings/interrupt-controller/irq.h>
> > #include <dt-bindings/power/mt8183-power.h>
> > +#include <dt-bindings/gce/mt8183-gce.h>
> > #include "mt8183-pinfunc.h"
> >
> > / {
> > @@ -664,6 +665,9 @@
> > reg = <0 0x14000000 0 0x1000>;
> > power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> > #clock-cells = <1>;
> > + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
>
> I would like to remove atomic parameter, so please follow [1] to remove
> it.
>
> [1] https://patchwork.kernel.org/patch/10765419/
Hi, CK,
Yeah, I'm trying remove atomic feature.
Thanks
Bibby
>
> Regards,
> CK
>
> > + <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
> > };
> >
> > ovl0: ovl@14008000 {
> > @@ -672,6 +676,7 @@
> > interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
> > power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> > clocks = <&mmsys CLK_MM_DISP_OVL0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
> > };
> >
> > ovl_2l0: ovl@14009000 {
> > @@ -680,6 +685,7 @@
> > interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
> > power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> > clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
> > };
> >
> > ovl_2l1: ovl@1400a000 {
> > @@ -688,6 +694,7 @@
> > interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
> > power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> > clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
> > };
> >
> > rdma0: rdma@1400b000 {
> > @@ -697,6 +704,7 @@
> > power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> > clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> > mediatek,rdma_fifo_size = <5120>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
> > };
> >
> > rdma1: rdma@1400c000 {
> > @@ -706,6 +714,7 @@
> > power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> > clocks = <&mmsys CLK_MM_DISP_RDMA1>;
> > mediatek,rdma_fifo_size = <2048>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
> > };
> >
> > color0: color@1400e000 {
> > @@ -715,6 +724,7 @@
> > interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
> > power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> > clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
> > };
> >
> > ccorr0: ccorr@1400f000 {
> > @@ -723,6 +733,7 @@
> > interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
> > power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> > clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
> > };
> >
> > aal0: aal@14010000 {
> > @@ -732,6 +743,7 @@
> > interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
> > power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> > clocks = <&mmsys CLK_MM_DISP_AAL0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
> > };
> >
> > gamma0: gamma@14011000 {
> > @@ -741,6 +753,7 @@
> > interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
> > power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> > clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
> > };
> >
> > dither0: dither@14012000 {
> > @@ -749,6 +762,7 @@
> > interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
> > power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> > clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
> > };
> >
> > mutex: mutex@14016000 {
> > @@ -756,6 +770,8 @@
> > reg = <0 0x14016000 0 0x1000>;
> > interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
> > power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> > + mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
> > + <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
> > };
> >
> > smi_common: smi@14019000 {
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-02-18 7:59 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-12 9:55 [PATCH 1/2] arm64: dts: mt8183: Add gce setting in display node Bibby Hsieh
2020-02-12 9:55 ` [PATCH 2/2] drm/mediatek: move gce event property to mutex device node Bibby Hsieh
2020-02-12 10:44 ` CK Hu
2020-02-18 7:59 ` CK Hu
2020-02-12 10:48 ` [PATCH 1/2] arm64: dts: mt8183: Add gce setting in display node CK Hu
2020-02-13 1:26 ` Bibby Hsieh
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).