* [PATCHv2 0/3] clk: agilex: add clock driver
@ 2020-03-09 17:16 Dinh Nguyen
2020-03-09 17:16 ` [PATCH RESEND 1/3] clk: socfpga: stratix10: use new parent data scheme Dinh Nguyen
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Dinh Nguyen @ 2020-03-09 17:16 UTC (permalink / raw)
To: linux-clk
Cc: dinguyen, linux-kernel, devicetree, sboyd, mturquette, robh+dt,
mark.rutland
Hi,
This is version 2 of the patchset to add clock driver to the Agilex
platform. It's been while since I posted v1 so I want clarify the
patches a bit in this cover letter.
Since the Agilex clocking is very similar to Stratix10, the
driver is very similar and will re-use the clock data structures of
Stratix10. Thus, there needs to be updates to the Stratix10 clock
driver.
Patch 1/3 : update the Stratix10 clock driver to make use of the new
parent data scheme
Patch 2/3 : version 2 of the documenation, converted to YAML
Patch 3/4 : version 2 of the clock driver with comments from v1
addressed
Thanks,
Dinh
Dinh Nguyen (3):
clk: socfpga: stratix10: use new parent data scheme
dt-bindings: documentation: add clock bindings information for Agilex
clk: socfpga: agilex: add clock driver for the Agilex platform
.../bindings/clock/intc,agilex.yaml | 79 ++++
drivers/clk/Makefile | 1 +
drivers/clk/socfpga/Makefile | 2 +
drivers/clk/socfpga/clk-agilex.c | 369 ++++++++++++++++++
drivers/clk/socfpga/clk-gate-s10.c | 5 +-
drivers/clk/socfpga/clk-periph-s10.c | 10 +-
drivers/clk/socfpga/clk-pll-s10.c | 74 +++-
drivers/clk/socfpga/clk-s10.c | 110 ++++--
drivers/clk/socfpga/stratix10-clk.h | 10 +-
include/dt-bindings/clock/agilex-clock.h | 70 ++++
10 files changed, 689 insertions(+), 41 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/intc,agilex.yaml
create mode 100644 drivers/clk/socfpga/clk-agilex.c
create mode 100644 include/dt-bindings/clock/agilex-clock.h
--
2.17.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH RESEND 1/3] clk: socfpga: stratix10: use new parent data scheme
2020-03-09 17:16 [PATCHv2 0/3] clk: agilex: add clock driver Dinh Nguyen
@ 2020-03-09 17:16 ` Dinh Nguyen
2020-03-09 17:16 ` [PATCHv2 2/3] dt-bindings: documentation: add clock bindings information for Agilex Dinh Nguyen
2020-03-09 17:16 ` [PATCHv2 3/3] clk: socfpga: agilex: add clock driver for the Agilex platform Dinh Nguyen
2 siblings, 0 replies; 7+ messages in thread
From: Dinh Nguyen @ 2020-03-09 17:16 UTC (permalink / raw)
To: linux-clk
Cc: dinguyen, linux-kernel, devicetree, sboyd, mturquette, robh+dt,
mark.rutland
Convert, where possible, the stratix10 clock driver to the new parent
data scheme by specifying the parent data for clocks that have multiple
parents.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
drivers/clk/socfpga/clk-gate-s10.c | 5 +-
drivers/clk/socfpga/clk-periph-s10.c | 10 ++-
drivers/clk/socfpga/clk-pll-s10.c | 4 +-
drivers/clk/socfpga/clk-s10.c | 110 ++++++++++++++++++++-------
drivers/clk/socfpga/stratix10-clk.h | 8 +-
5 files changed, 96 insertions(+), 41 deletions(-)
diff --git a/drivers/clk/socfpga/clk-gate-s10.c b/drivers/clk/socfpga/clk-gate-s10.c
index 8be4722f6064..083b2ec21fdd 100644
--- a/drivers/clk/socfpga/clk-gate-s10.c
+++ b/drivers/clk/socfpga/clk-gate-s10.c
@@ -70,7 +70,6 @@ struct clk *s10_register_gate(const struct stratix10_gate_clock *clks, void __io
struct clk *clk;
struct socfpga_gate_clk *socfpga_clk;
struct clk_init_data init;
- const char * const *parent_names = clks->parent_names;
const char *parent_name = clks->parent_name;
socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
@@ -108,7 +107,9 @@ struct clk *s10_register_gate(const struct stratix10_gate_clock *clks, void __io
init.flags = clks->flags;
init.num_parents = clks->num_parents;
- init.parent_names = parent_names ? parent_names : &parent_name;
+ init.parent_names = parent_name ? &parent_name : NULL;
+ if (init.parent_names == NULL)
+ init.parent_data = clks->parent_data;
socfpga_clk->hw.hw.init = &init;
clk = clk_register(NULL, &socfpga_clk->hw.hw);
diff --git a/drivers/clk/socfpga/clk-periph-s10.c b/drivers/clk/socfpga/clk-periph-s10.c
index dd6d4056e9de..397b77b89b16 100644
--- a/drivers/clk/socfpga/clk-periph-s10.c
+++ b/drivers/clk/socfpga/clk-periph-s10.c
@@ -81,7 +81,6 @@ struct clk *s10_register_periph(const struct stratix10_perip_c_clock *clks,
struct clk_init_data init;
const char *name = clks->name;
const char *parent_name = clks->parent_name;
- const char * const *parent_names = clks->parent_names;
periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
if (WARN_ON(!periph_clk))
@@ -94,7 +93,9 @@ struct clk *s10_register_periph(const struct stratix10_perip_c_clock *clks,
init.flags = clks->flags;
init.num_parents = clks->num_parents;
- init.parent_names = parent_names ? parent_names : &parent_name;
+ init.parent_names = parent_name ? &parent_name : NULL;
+ if (init.parent_names == NULL)
+ init.parent_data = clks->parent_data;
periph_clk->hw.hw.init = &init;
@@ -114,7 +115,6 @@ struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *clks
struct clk_init_data init;
const char *name = clks->name;
const char *parent_name = clks->parent_name;
- const char * const *parent_names = clks->parent_names;
periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
if (WARN_ON(!periph_clk))
@@ -137,7 +137,9 @@ struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *clks
init.flags = clks->flags;
init.num_parents = clks->num_parents;
- init.parent_names = parent_names ? parent_names : &parent_name;
+ init.parent_names = parent_name ? &parent_name : NULL;
+ if (init.parent_names == NULL)
+ init.parent_data = clks->parent_data;
periph_clk->hw.hw.init = &init;
diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pll-s10.c
index a301bb22f36c..bcd3f14e9145 100644
--- a/drivers/clk/socfpga/clk-pll-s10.c
+++ b/drivers/clk/socfpga/clk-pll-s10.c
@@ -117,7 +117,6 @@ struct clk *s10_register_pll(const struct stratix10_pll_clock *clks,
struct socfpga_pll *pll_clk;
struct clk_init_data init;
const char *name = clks->name;
- const char * const *parent_names = clks->parent_names;
pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
if (WARN_ON(!pll_clk))
@@ -134,7 +133,8 @@ struct clk *s10_register_pll(const struct stratix10_pll_clock *clks,
init.flags = clks->flags;
init.num_parents = clks->num_parents;
- init.parent_names = parent_names;
+ init.parent_names = NULL;
+ init.parent_data = clks->parent_data;
pll_clk->hw.hw.init = &init;
pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
diff --git a/drivers/clk/socfpga/clk-s10.c b/drivers/clk/socfpga/clk-s10.c
index dea7c6c7d269..ed11c8509a15 100644
--- a/drivers/clk/socfpga/clk-s10.c
+++ b/drivers/clk/socfpga/clk-s10.c
@@ -12,35 +12,87 @@
#include "stratix10-clk.h"
-static const char * const pll_mux[] = { "osc1", "cb-intosc-hs-div2-clk",
- "f2s-free-clk",};
-static const char * const cntr_mux[] = { "main_pll", "periph_pll",
- "osc1", "cb-intosc-hs-div2-clk",
- "f2s-free-clk"};
-static const char * const boot_mux[] = { "osc1", "cb-intosc-hs-div2-clk",};
-
-static const char * const noc_free_mux[] = {"main_noc_base_clk",
- "peri_noc_base_clk",
- "osc1", "cb-intosc-hs-div2-clk",
- "f2s-free-clk"};
-
-static const char * const emaca_free_mux[] = {"peri_emaca_clk", "boot_clk"};
-static const char * const emacb_free_mux[] = {"peri_emacb_clk", "boot_clk"};
-static const char * const emac_ptp_free_mux[] = {"peri_emac_ptp_clk", "boot_clk"};
-static const char * const gpio_db_free_mux[] = {"peri_gpio_db_clk", "boot_clk"};
-static const char * const sdmmc_free_mux[] = {"main_sdmmc_clk", "boot_clk"};
-static const char * const s2f_usr1_free_mux[] = {"peri_s2f_usr1_clk", "boot_clk"};
-static const char * const psi_ref_free_mux[] = {"peri_psi_ref_clk", "boot_clk"};
-static const char * const mpu_mux[] = { "mpu_free_clk", "boot_clk",};
-
-static const char * const s2f_usr0_mux[] = {"f2s-free-clk", "boot_clk"};
-static const char * const emac_mux[] = {"emaca_free_clk", "emacb_free_clk"};
-static const char * const noc_mux[] = {"noc_free_clk", "boot_clk"};
-
-static const char * const mpu_free_mux[] = {"main_mpu_base_clk",
- "peri_mpu_base_clk",
- "osc1", "cb-intosc-hs-div2-clk",
- "f2s-free-clk"};
+static const struct clk_parent_data pll_mux[] = {
+ { .name = "osc1" },
+ { .name = "cb-intosc-hs-div2-clk" },
+ { .name = "f2s-free-clk" },
+};
+
+static const struct clk_parent_data cntr_mux[] = {
+ { .name = "main_pll", },
+ { .name = "periph_pll", },
+ { .name = "osc1", },
+ { .name = "cb-intosc-hs-div2-clk", },
+ { .name = "f2s-free-clk", },
+};
+
+static const struct clk_parent_data boot_mux[] = {
+ { .name = "osc1" },
+ { .name = "cb-intosc-hs-div2-clk" },
+};
+
+static const struct clk_parent_data noc_free_mux[] = {
+ { .name = "main_noc_base_clk", },
+ { .name = "peri_noc_base_clk", },
+ { .name = "osc1", },
+ { .name = "cb-intosc-hs-div2-clk", },
+ { .name = "f2s-free-clk", },
+};
+
+static const struct clk_parent_data emaca_free_mux[] = {
+ { .name = "peri_emaca_clk", },
+ { .name = "boot_clk", },
+};
+
+static const struct clk_parent_data emacb_free_mux[] = {
+ { .name = "peri_emacb_clk", },
+ { .name = "boot_clk", },
+};
+static const struct clk_parent_data emac_ptp_free_mux[] = {
+ { .name = "peri_emac_ptp_clk", },
+ { .name = "boot_clk", },
+};
+static const struct clk_parent_data gpio_db_free_mux[] = {
+ { .name = "peri_gpio_db_clk", },
+ { .name = "boot_clk", },
+};
+static const struct clk_parent_data sdmmc_free_mux[] = {
+ { .name = "main_sdmmc_clk", },
+ { .name = "boot_clk", },
+};
+static const struct clk_parent_data s2f_usr1_free_mux[] = {
+ { .name = "peri_s2f_usr1_clk", },
+ { .name = "boot_clk", },
+};
+static const struct clk_parent_data psi_ref_free_mux[] = {
+ { .name = "peri_psi_ref_clk", },
+ { .name = "boot_clk", },
+};
+static const struct clk_parent_data mpu_mux[] = {
+ { .name = "mpu_free_clk", },
+ { .name = "boot_clk", },
+};
+
+static const struct clk_parent_data s2f_usr0_mux[] = {
+ { .name = "f2s-free-clk", },
+ { .name = "boot_clk", },
+};
+static const struct clk_parent_data emac_mux[] = {
+ { .name = "emaca_free_clk", },
+ { .name = "emacb_free_clk", },
+};
+static const struct clk_parent_data noc_mux[] = {
+ { .name = "noc_free_clk", },
+ { .name = "boot_clk", },
+};
+
+static const struct clk_parent_data mpu_free_mux[] = {
+ { .name = "main_mpu_base_clk", },
+ { .name = "peri_mpu_base_clk", },
+ { .name = "osc1", },
+ { .name = "cb-intosc-hs-div2-clk", },
+ { .name = "f2s-free-clk", },
+};
/* clocks in AO (always on) controller */
static const struct stratix10_pll_clock s10_pll_clks[] = {
diff --git a/drivers/clk/socfpga/stratix10-clk.h b/drivers/clk/socfpga/stratix10-clk.h
index fcabef42249c..ffbd1fb2c8ef 100644
--- a/drivers/clk/socfpga/stratix10-clk.h
+++ b/drivers/clk/socfpga/stratix10-clk.h
@@ -14,7 +14,7 @@ struct stratix10_clock_data {
struct stratix10_pll_clock {
unsigned int id;
const char *name;
- const char *const *parent_names;
+ const struct clk_parent_data *parent_data;
u8 num_parents;
unsigned long flags;
unsigned long offset;
@@ -24,7 +24,7 @@ struct stratix10_perip_c_clock {
unsigned int id;
const char *name;
const char *parent_name;
- const char *const *parent_names;
+ const struct clk_parent_data *parent_data;
u8 num_parents;
unsigned long flags;
unsigned long offset;
@@ -34,7 +34,7 @@ struct stratix10_perip_cnt_clock {
unsigned int id;
const char *name;
const char *parent_name;
- const char *const *parent_names;
+ const struct clk_parent_data *parent_data;
u8 num_parents;
unsigned long flags;
unsigned long offset;
@@ -47,7 +47,7 @@ struct stratix10_gate_clock {
unsigned int id;
const char *name;
const char *parent_name;
- const char *const *parent_names;
+ const struct clk_parent_data *parent_data;
u8 num_parents;
unsigned long flags;
unsigned long gate_reg;
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCHv2 2/3] dt-bindings: documentation: add clock bindings information for Agilex
2020-03-09 17:16 [PATCHv2 0/3] clk: agilex: add clock driver Dinh Nguyen
2020-03-09 17:16 ` [PATCH RESEND 1/3] clk: socfpga: stratix10: use new parent data scheme Dinh Nguyen
@ 2020-03-09 17:16 ` Dinh Nguyen
2020-03-09 22:30 ` Stephen Boyd
2020-03-10 18:36 ` Rob Herring
2020-03-09 17:16 ` [PATCHv2 3/3] clk: socfpga: agilex: add clock driver for the Agilex platform Dinh Nguyen
2 siblings, 2 replies; 7+ messages in thread
From: Dinh Nguyen @ 2020-03-09 17:16 UTC (permalink / raw)
To: linux-clk
Cc: dinguyen, linux-kernel, devicetree, sboyd, mturquette, robh+dt,
mark.rutland
Document the Agilex clock bindings, and add the clock header file. The
clock header is an enumeration of all the different clocks on the Agilex
platform.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v2: convert original document to YAML
---
.../bindings/clock/intc,agilex.yaml | 79 +++++++++++++++++++
include/dt-bindings/clock/agilex-clock.h | 70 ++++++++++++++++
2 files changed, 149 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/intc,agilex.yaml
create mode 100644 include/dt-bindings/clock/agilex-clock.h
diff --git a/Documentation/devicetree/bindings/clock/intc,agilex.yaml b/Documentation/devicetree/bindings/clock/intc,agilex.yaml
new file mode 100644
index 000000000000..bd5c4f590e12
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/intc,agilex.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/intc,agilex.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel SoCFPGA Agilex platform clock controller binding
+
+maintainers:
+ - Dinh Nguyen <dinguyen@kernel.org>
+
+description: |
+ The Intel Agilex Clock controller is an integrated clock controller, which
+ generates and supplies to all modules.
+
+ This binding uses the common clock binding[1].
+ [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - intel,agilex-clkmgr
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+examples:
+ # Clock controller node
+ - |
+ clkmgr: clock-controller@ffd10000 {
+ compatible = "intel,agilex-clkmgr";
+ reg = <0xffd10000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ # External clocks
+ - |
+ clocks {
+ cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ cb_intosc_ls_clk: cb-intosc-ls-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ f2s_free_clk: f2s-free-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ osc1: osc1 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+ };
+
+ # The clock consumer shall specify the desired clock-output of the clock
+ # controller as below by specifying output-id in its "clk" phandle cell.
+ - |
+ i2c0: i2c@ffc02800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0xffc02800 0x100>;
+ interrupts = <0 103 4>;
+ resets = <&rst I2C0_RESET>;
+ clocks = <&clkmgr AGILEX_L4_SP_CLK>;
+ };
+...
diff --git a/include/dt-bindings/clock/agilex-clock.h b/include/dt-bindings/clock/agilex-clock.h
new file mode 100644
index 000000000000..f19cf8ccbdd2
--- /dev/null
+++ b/include/dt-bindings/clock/agilex-clock.h
@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019, Intel Corporation
+ */
+
+#ifndef __AGILEX_CLOCK_H
+#define __AGILEX_CLOCK_H
+
+/* fixed rate clocks */
+#define AGILEX_OSC1 0
+#define AGILEX_CB_INTOSC_HS_DIV2_CLK 1
+#define AGILEX_CB_INTOSC_LS_CLK 2
+#define AGILEX_L4_SYS_FREE_CLK 3
+#define AGILEX_F2S_FREE_CLK 4
+
+/* PLL clocks */
+#define AGILEX_MAIN_PLL_CLK 5
+#define AGILEX_MAIN_PLL_C0_CLK 6
+#define AGILEX_MAIN_PLL_C1_CLK 7
+#define AGILEX_MAIN_PLL_C2_CLK 8
+#define AGILEX_MAIN_PLL_C3_CLK 9
+#define AGILEX_PERIPH_PLL_CLK 10
+#define AGILEX_PERIPH_PLL_C0_CLK 11
+#define AGILEX_PERIPH_PLL_C1_CLK 12
+#define AGILEX_PERIPH_PLL_C2_CLK 13
+#define AGILEX_PERIPH_PLL_C3_CLK 14
+#define AGILEX_MPU_FREE_CLK 15
+#define AGILEX_MPU_CCU_CLK 16
+#define AGILEX_BOOT_CLK 17
+
+/* fixed factor clocks */
+#define AGILEX_L3_MAIN_FREE_CLK 18
+#define AGILEX_NOC_FREE_CLK 19
+#define AGILEX_S2F_USR0_CLK 20
+#define AGILEX_NOC_CLK 21
+#define AGILEX_EMAC_A_FREE_CLK 22
+#define AGILEX_EMAC_B_FREE_CLK 23
+#define AGILEX_EMAC_PTP_FREE_CLK 24
+#define AGILEX_GPIO_DB_FREE_CLK 25
+#define AGILEX_SDMMC_FREE_CLK 26
+#define AGILEX_S2F_USER0_FREE_CLK 27
+#define AGILEX_S2F_USER1_FREE_CLK 28
+#define AGILEX_PSI_REF_FREE_CLK 29
+
+/* Gate clocks */
+#define AGILEX_MPU_CLK 30
+#define AGILEX_MPU_L2RAM_CLK 31
+#define AGILEX_MPU_PERIPH_CLK 32
+#define AGILEX_L4_MAIN_CLK 33
+#define AGILEX_L4_MP_CLK 34
+#define AGILEX_L4_SP_CLK 35
+#define AGILEX_CS_AT_CLK 36
+#define AGILEX_CS_TRACE_CLK 37
+#define AGILEX_CS_PDBG_CLK 38
+#define AGILEX_CS_TIMER_CLK 39
+#define AGILEX_S2F_USER0_CLK 40
+#define AGILEX_EMAC0_CLK 41
+#define AGILEX_EMAC1_CLK 43
+#define AGILEX_EMAC2_CLK 44
+#define AGILEX_EMAC_PTP_CLK 45
+#define AGILEX_GPIO_DB_CLK 46
+#define AGILEX_NAND_CLK 47
+#define AGILEX_PSI_REF_CLK 48
+#define AGILEX_S2F_USER1_CLK 49
+#define AGILEX_SDMMC_CLK 50
+#define AGILEX_SPI_M_CLK 51
+#define AGILEX_USB_CLK 52
+#define AGILEX_NUM_CLKS 53
+
+#endif /* __AGILEX_CLOCK_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCHv2 3/3] clk: socfpga: agilex: add clock driver for the Agilex platform
2020-03-09 17:16 [PATCHv2 0/3] clk: agilex: add clock driver Dinh Nguyen
2020-03-09 17:16 ` [PATCH RESEND 1/3] clk: socfpga: stratix10: use new parent data scheme Dinh Nguyen
2020-03-09 17:16 ` [PATCHv2 2/3] dt-bindings: documentation: add clock bindings information for Agilex Dinh Nguyen
@ 2020-03-09 17:16 ` Dinh Nguyen
2020-03-09 22:36 ` Stephen Boyd
2 siblings, 1 reply; 7+ messages in thread
From: Dinh Nguyen @ 2020-03-09 17:16 UTC (permalink / raw)
To: linux-clk
Cc: dinguyen, linux-kernel, devicetree, sboyd, mturquette, robh+dt,
mark.rutland
For the most part the Agilex clock structure is very similar to
Stratix10, so we re-use most of the Stratix10 clock driver.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v2: update to use clk_parent_data
---
drivers/clk/Makefile | 1 +
drivers/clk/socfpga/Makefile | 2 +
drivers/clk/socfpga/clk-agilex.c | 369 ++++++++++++++++++++++++++++
drivers/clk/socfpga/clk-pll-s10.c | 70 ++++++
drivers/clk/socfpga/stratix10-clk.h | 2 +
5 files changed, 444 insertions(+)
create mode 100644 drivers/clk/socfpga/clk-agilex.c
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index f4169cc2fd31..d9ddc0bd91c0 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -18,6 +18,7 @@ endif
# hardware specific clock types
# please keep this section sorted lexicographically by file path name
+obj-$(CONFIG_ARCH_AGILEX) += socfpga/
obj-$(CONFIG_MACH_ASM9260) += clk-asm9260.o
obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o
obj-$(CONFIG_ARCH_AXXIA) += clk-axm5516.o
diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile
index ce5aa7802eb8..bf736f8d201a 100644
--- a/drivers/clk/socfpga/Makefile
+++ b/drivers/clk/socfpga/Makefile
@@ -3,3 +3,5 @@ obj-$(CONFIG_ARCH_SOCFPGA) += clk.o clk-gate.o clk-pll.o clk-periph.o
obj-$(CONFIG_ARCH_SOCFPGA) += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o
obj-$(CONFIG_ARCH_STRATIX10) += clk-s10.o
obj-$(CONFIG_ARCH_STRATIX10) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o
+obj-$(CONFIG_ARCH_AGILEX) += clk-agilex.o
+obj-$(CONFIG_ARCH_AGILEX) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o
diff --git a/drivers/clk/socfpga/clk-agilex.c b/drivers/clk/socfpga/clk-agilex.c
new file mode 100644
index 000000000000..6789892085db
--- /dev/null
+++ b/drivers/clk/socfpga/clk-agilex.c
@@ -0,0 +1,369 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019, Intel Corporation
+ */
+#include <linux/slab.h>
+#include <linux/clk-provider.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/clock/agilex-clock.h>
+
+#include "stratix10-clk.h"
+
+static const struct clk_parent_data pll_mux[] = {
+ { .name = "osc1", },
+ { .name = "cb-intosc-hs-div2-clk", },
+ { .name = "f2s-free-clk", },
+};
+static const struct clk_parent_data cntr_mux[] = {
+ { .name = "main_pll", },
+ { .name = "periph_pll", },
+ { .name = "osc1", },
+ { .name = "cb-intosc-hs-div2-clk", },
+ { .name = "f2s-free-clk", },
+};
+static const struct clk_parent_data boot_mux[] = {
+ { .name = "osc1", },
+ { .name = "cb-intosc-hs-div2-clk", },
+};
+static const struct clk_parent_data mpu_free_mux[] = {
+ { .name = "main_pll_c0", },
+ { .name = "peri_pll_c0", },
+ { .name = "osc1", },
+ { .name = "cb-intosc-hs-div2-clk", },
+ { .name = "f2s-free-clk", },
+};
+static const struct clk_parent_data noc_free_mux[] = {
+ { .name = "main_pll_c1", },
+ { .name = "peri_pll_c1", },
+ { .name = "osc1", },
+ { .name = "cb-intosc-hs-div2-clk", },
+ { .name = "f2s-free-clk", },
+};
+static const struct clk_parent_data emaca_free_mux[] = {
+ { .name = "main_pll_c2", },
+ { .name = "peri_pll_c2", },
+ { .name = "osc1", },
+ { .name = "cb-intosc-hs-div2-clk", },
+ { .name = "f2s-free-clk", },
+};
+static const struct clk_parent_data emacb_free_mux[] = {
+ { .name = "main_pll_c3", },
+ { .name = "peri_pll_c3", },
+ { .name = "osc1", },
+ { .name = "cb-intosc-hs-div2-clk", },
+ { .name = "f2s-free-clk", },
+};
+static const struct clk_parent_data emac_ptp_free_mux[] = {
+ { .name = "main_pll_c3", },
+ { .name = "peri_pll_c3", },
+ { .name = "osc1", },
+ { .name = "cb-intosc-hs-div2-clk", },
+ { .name = "f2s-free-clk", },
+};
+static const struct clk_parent_data gpio_db_free_mux[] = {
+ { .name = "main_pll_c3", },
+ { .name = "peri_pll_c3", },
+ { .name = "osc1", },
+ { .name = "cb-intosc-hs-div2-clk", },
+ { .name = "f2s-free-clk", },
+};
+static const struct clk_parent_data psi_ref_free_mux[] = {
+ { .name = "main_pll_c3", },
+ { .name = "peri_pll_c3", },
+ { .name = "osc1", },
+ { .name = "cb-intosc-hs-div2-clk", },
+ { .name = "f2s-free-clk", },
+};
+static const struct clk_parent_data sdmmc_free_mux[] = {
+ { .name = "main_pll_c3", },
+ { .name = "peri_pll_c3", },
+ { .name = "osc1", },
+ { .name = "cb-intosc-hs-div2-clk", },
+ { .name = "f2s-free-clk", },
+};
+static const struct clk_parent_data s2f_usr0_free_mux[] = {
+ { .name = "main_pll_c2", },
+ { .name = "peri_pll_c2", },
+ { .name = "osc1", },
+ { .name = "cb-intosc-hs-div2-clk", },
+ { .name = "f2s-free-clk", },
+};
+static const struct clk_parent_data s2f_usr1_free_mux[] = {
+ { .name = "main_pll_c2", },
+ { .name = "peri_pll_c2", },
+ { .name = "osc1", },
+ { .name = "cb-intosc-hs-div2-clk", },
+ { .name = "f2s-free-clk", },
+};
+static const struct clk_parent_data mpu_mux[] = {
+ { .name = "mpu_free_clk", },
+ { .name = "boot_clk", },
+};
+static const struct clk_parent_data s2f_usr0_mux[] = {
+ { .name = "f2s-free-clk", },
+ { .name = "boot_clk", },
+};
+static const struct clk_parent_data emac_mux[] = {
+ { .name = "emaca_free_clk", },
+ { .name = "emacb_free_clk", },
+};
+static const struct clk_parent_data noc_mux[] = {
+ { .name = "noc_free_clk", },
+ { .name = "boot_clk", },
+};
+
+/* clocks in AO (always on) controller */
+static const struct stratix10_pll_clock agilex_pll_clks[] = {
+ { AGILEX_BOOT_CLK, "boot_clk", boot_mux, ARRAY_SIZE(boot_mux), 0,
+ 0x0},
+ { AGILEX_MAIN_PLL_CLK, "main_pll", pll_mux, ARRAY_SIZE(pll_mux),
+ 0, 0x48},
+ { AGILEX_PERIPH_PLL_CLK, "periph_pll", pll_mux, ARRAY_SIZE(pll_mux),
+ 0, 0x9c},
+};
+
+static const struct stratix10_perip_c_clock agilex_main_perip_c_clks[] = {
+ { AGILEX_MAIN_PLL_C0_CLK, "main_pll_c0", "main_pll", NULL, 1, 0, 0x58},
+ { AGILEX_MAIN_PLL_C1_CLK, "main_pll_c1", "main_pll", NULL, 1, 0, 0x5C},
+ { AGILEX_MAIN_PLL_C2_CLK, "main_pll_c2", "main_pll", NULL, 1, 0, 0x64},
+ { AGILEX_MAIN_PLL_C3_CLK, "main_pll_c3", "main_pll", NULL, 1, 0, 0x68},
+ { AGILEX_PERIPH_PLL_C0_CLK, "peri_pll_c0", "periph_pll", NULL, 1, 0, 0xAC},
+ { AGILEX_PERIPH_PLL_C1_CLK, "peri_pll_c1", "periph_pll", NULL, 1, 0, 0xB0},
+ { AGILEX_PERIPH_PLL_C2_CLK, "peri_pll_c2", "periph_pll", NULL, 1, 0, 0xB8},
+ { AGILEX_PERIPH_PLL_C3_CLK, "peri_pll_c3", "periph_pll", NULL, 1, 0, 0xBC},
+};
+
+static const struct stratix10_perip_cnt_clock agilex_main_perip_cnt_clks[] = {
+ { AGILEX_MPU_FREE_CLK, "mpu_free_clk", NULL, mpu_free_mux, ARRAY_SIZE(mpu_free_mux),
+ 0, 0x3C, 0, 0, 0},
+ { AGILEX_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux, ARRAY_SIZE(noc_free_mux),
+ 0, 0x40, 0, 0, 1},
+ { AGILEX_L4_SYS_FREE_CLK, "l4_sys_free_clk", "noc_free_clk", NULL, 1, 0,
+ 0, 4, 0, 0},
+ { AGILEX_NOC_CLK, "noc_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux),
+ 0, 0, 0, 0x30, 1},
+ { AGILEX_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux, ARRAY_SIZE(emaca_free_mux),
+ 0, 0xD4, 0, 0x88, 0},
+ { AGILEX_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux, ARRAY_SIZE(emacb_free_mux),
+ 0, 0xD8, 0, 0x88, 1},
+ { AGILEX_EMAC_PTP_FREE_CLK, "emac_ptp_free_clk", NULL, emac_ptp_free_mux,
+ ARRAY_SIZE(emac_ptp_free_mux), 0, 0xDC, 0, 0x88, 2},
+ { AGILEX_GPIO_DB_FREE_CLK, "gpio_db_free_clk", NULL, gpio_db_free_mux,
+ ARRAY_SIZE(gpio_db_free_mux), 0, 0xE0, 0, 0x88, 3},
+ { AGILEX_SDMMC_FREE_CLK, "sdmmc_free_clk", NULL, sdmmc_free_mux,
+ ARRAY_SIZE(sdmmc_free_mux), 0, 0xE4, 0, 0x88, 4},
+ { AGILEX_S2F_USER0_FREE_CLK, "s2f_user0_free_clk", NULL, s2f_usr0_free_mux,
+ ARRAY_SIZE(s2f_usr0_free_mux), 0, 0xE8, 0, 0, 0},
+ { AGILEX_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL, s2f_usr1_free_mux,
+ ARRAY_SIZE(s2f_usr1_free_mux), 0, 0xEC, 0, 0x88, 5},
+ { AGILEX_PSI_REF_FREE_CLK, "psi_ref_free_clk", NULL, psi_ref_free_mux,
+ ARRAY_SIZE(psi_ref_free_mux), 0, 0xF0, 0, 0x88, 6},
+};
+
+static const struct stratix10_gate_clock agilex_gate_clks[] = {
+ { AGILEX_MPU_CLK, "mpu_clk", NULL, mpu_mux, ARRAY_SIZE(mpu_mux), 0, 0x24,
+ 0, 0, 0, 0, 0x30, 0, 0},
+ { AGILEX_MPU_PERIPH_CLK, "mpu_periph_clk", "mpu_clk", NULL, 1, 0, 0x24,
+ 0, 0, 0, 0, 0, 0, 4},
+ { AGILEX_MPU_L2RAM_CLK, "mpu_l2ram_clk", "mpu_clk", NULL, 1, 0, 0x24,
+ 0, 0, 0, 0, 0, 0, 2},
+ { AGILEX_L4_MAIN_CLK, "l4_main_clk", "noc_clk", NULL, 1, 0, 0x24,
+ 1, 0x44, 0, 2, 0, 0, 0},
+ { AGILEX_L4_MP_CLK, "l4_mp_clk", "noc_clk", NULL, 1, 0, 0x24,
+ 2, 0x44, 8, 2, 0, 0, 0},
+ { AGILEX_L4_SP_CLK, "l4_sp_clk", "noc_clk", NULL, 1, CLK_IS_CRITICAL, 0x24,
+ 3, 0x44, 16, 2, 0, 0, 0},
+ { AGILEX_CS_AT_CLK, "cs_at_clk", "noc_clk", NULL, 1, 0, 0x24,
+ 4, 0x44, 24, 2, 0, 0, 0},
+ { AGILEX_CS_TRACE_CLK, "cs_trace_clk", "noc_clk", NULL, 1, 0, 0x24,
+ 4, 0x44, 26, 2, 0, 0, 0},
+ { AGILEX_CS_PDBG_CLK, "cs_pdbg_clk", "cs_at_clk", NULL, 1, 0, 0x24,
+ 4, 0x44, 28, 1, 0, 0, 0},
+ { AGILEX_CS_TIMER_CLK, "cs_timer_clk", "noc_clk", NULL, 1, 0, 0x24,
+ 5, 0, 0, 0, 0, 0, 0},
+ { AGILEX_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_usr0_mux, ARRAY_SIZE(s2f_usr0_mux), 0, 0x24,
+ 6, 0, 0, 0, 0, 0, 0},
+ { AGILEX_EMAC0_CLK, "emac0_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C,
+ 0, 0, 0, 0, 0x94, 26, 0},
+ { AGILEX_EMAC1_CLK, "emac1_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C,
+ 1, 0, 0, 0, 0x94, 27, 0},
+ { AGILEX_EMAC2_CLK, "emac2_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C,
+ 2, 0, 0, 0, 0x94, 28, 0},
+ { AGILEX_EMAC_PTP_CLK, "emac_ptp_clk", "emac_ptp_free_clk", NULL, 1, 0, 0x7C,
+ 3, 0, 0, 0, 0, 0, 0},
+ { AGILEX_GPIO_DB_CLK, "gpio_db_clk", "gpio_db_free_clk", NULL, 1, 0, 0x7C,
+ 4, 0x98, 0, 16, 0, 0, 0},
+ { AGILEX_SDMMC_CLK, "sdmmc_clk", "sdmmc_free_clk", NULL, 1, 0, 0x7C,
+ 5, 0, 0, 0, 0, 0, 4},
+ { AGILEX_S2F_USER1_CLK, "s2f_user1_clk", "s2f_user1_free_clk", NULL, 1, 0, 0x7C,
+ 6, 0, 0, 0, 0, 0, 0},
+ { AGILEX_PSI_REF_CLK, "psi_ref_clk", "psi_ref_free_clk", NULL, 1, 0, 0x7C,
+ 7, 0, 0, 0, 0, 0, 0},
+ { AGILEX_USB_CLK, "usb_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
+ 8, 0, 0, 0, 0, 0, 0},
+ { AGILEX_SPI_M_CLK, "spi_m_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
+ 9, 0, 0, 0, 0, 0, 0},
+ { AGILEX_NAND_CLK, "nand_clk", "l4_main_clk", NULL, 1, 0, 0x7C,
+ 10, 0, 0, 0, 0, 0, 0},
+};
+
+static int agilex_clk_register_c_perip(const struct stratix10_perip_c_clock *clks,
+ int nums, struct stratix10_clock_data *data)
+{
+ struct clk *clk;
+ void __iomem *base = data->base;
+ int i;
+
+ for (i = 0; i < nums; i++) {
+ clk = s10_register_periph(&clks[i], base);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock %s\n",
+ __func__, clks[i].name);
+ continue;
+ }
+ data->clk_data.clks[clks[i].id] = clk;
+ }
+ return 0;
+}
+
+static int agilex_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *clks,
+ int nums, struct stratix10_clock_data *data)
+{
+ struct clk *clk;
+ void __iomem *base = data->base;
+ int i;
+
+ for (i = 0; i < nums; i++) {
+ clk = s10_register_cnt_periph(&clks[i], base);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock %s\n",
+ __func__, clks[i].name);
+ continue;
+ }
+ data->clk_data.clks[clks[i].id] = clk;
+ }
+
+ return 0;
+}
+
+static int agilex_clk_register_gate(const struct stratix10_gate_clock *clks, int nums, struct stratix10_clock_data *data)
+{
+ struct clk *clk;
+ void __iomem *base = data->base;
+ int i;
+
+ for (i = 0; i < nums; i++) {
+ clk = s10_register_gate(&clks[i], base);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock %s\n",
+ __func__, clks[i].name);
+ continue;
+ }
+ data->clk_data.clks[clks[i].id] = clk;
+ }
+
+ return 0;
+}
+
+static int agilex_clk_register_pll(const struct stratix10_pll_clock *clks,
+ int nums, struct stratix10_clock_data *data)
+{
+ struct clk *clk;
+ void __iomem *base = data->base;
+ int i;
+
+ for (i = 0; i < nums; i++) {
+ clk = agilex_register_pll(&clks[i], base);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock %s\n",
+ __func__, clks[i].name);
+ continue;
+ }
+ data->clk_data.clks[clks[i].id] = clk;
+ }
+
+ return 0;
+}
+
+static struct stratix10_clock_data *__socfpga_agilex_clk_init(struct platform_device *pdev,
+ int nr_clks)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct device *dev = &pdev->dev;
+ struct stratix10_clock_data *clk_data;
+ struct clk **clk_table;
+ struct resource *res;
+ void __iomem *base;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(base)) {
+ pr_err("%s: failed to map clock registers\n", __func__);
+ return ERR_CAST(base);
+ }
+
+ clk_data = devm_kzalloc(dev, sizeof(*clk_data), GFP_KERNEL);
+ if (!clk_data)
+ return ERR_PTR(-ENOMEM);
+
+ clk_data->base = base;
+ clk_table = devm_kcalloc(dev, nr_clks, sizeof(*clk_table), GFP_KERNEL);
+ if (!clk_table)
+ return ERR_PTR(-ENOMEM);
+
+ clk_data->clk_data.clks = clk_table;
+ clk_data->clk_data.clk_num = nr_clks;
+ of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data);
+ return clk_data;
+}
+
+static int agilex_clkmgr_init(struct platform_device *pdev)
+{
+ struct stratix10_clock_data *clk_data;
+
+ clk_data = __socfpga_agilex_clk_init(pdev, AGILEX_NUM_CLKS);
+ if (IS_ERR(clk_data))
+ return PTR_ERR(clk_data);
+
+ agilex_clk_register_pll(agilex_pll_clks, ARRAY_SIZE(agilex_pll_clks), clk_data);
+
+ agilex_clk_register_c_perip(agilex_main_perip_c_clks,
+ ARRAY_SIZE(agilex_main_perip_c_clks), clk_data);
+
+ agilex_clk_register_cnt_perip(agilex_main_perip_cnt_clks,
+ ARRAY_SIZE(agilex_main_perip_cnt_clks),
+ clk_data);
+
+ agilex_clk_register_gate(agilex_gate_clks, ARRAY_SIZE(agilex_gate_clks),
+ clk_data);
+ return 0;
+}
+
+static int agilex_clkmgr_probe(struct platform_device *pdev)
+{
+ return agilex_clkmgr_init(pdev);
+}
+
+static const struct of_device_id agilex_clkmgr_match_table[] = {
+ { .compatible = "intel,agilex-clkmgr",
+ .data = agilex_clkmgr_init },
+ { }
+};
+
+static struct platform_driver agilex_clkmgr_driver = {
+ .probe = agilex_clkmgr_probe,
+ .driver = {
+ .name = "agilex-clkmgr",
+ .suppress_bind_attrs = true,
+ .of_match_table = agilex_clkmgr_match_table,
+ },
+};
+
+static int __init agilex_clk_init(void)
+{
+ return platform_driver_register(&agilex_clkmgr_driver);
+}
+core_initcall(agilex_clk_init);
diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pll-s10.c
index bcd3f14e9145..17fe5bd2c0e1 100644
--- a/drivers/clk/socfpga/clk-pll-s10.c
+++ b/drivers/clk/socfpga/clk-pll-s10.c
@@ -18,8 +18,12 @@
#define SOCFPGA_PLL_RESET_MASK 0x2
#define SOCFPGA_PLL_REFDIV_MASK 0x00003F00
#define SOCFPGA_PLL_REFDIV_SHIFT 8
+#define SOCFPGA_PLL_AREFDIV_MASK 0x00000F00
+#define SOCFPGA_PLL_DREFDIV_MASK 0x00003000
+#define SOCFPGA_PLL_DREFDIV_SHIFT 12
#define SOCFPGA_PLL_MDIV_MASK 0xFF000000
#define SOCFPGA_PLL_MDIV_SHIFT 24
+#define SOCFPGA_AGILEX_PLL_MDIV_MASK 0x000003FF
#define SWCTRLBTCLKSEL_MASK 0x200
#define SWCTRLBTCLKSEL_SHIFT 9
@@ -27,6 +31,27 @@
#define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw)
+static unsigned long agilex_clk_pll_recalc_rate(struct clk_hw *hwclk,
+ unsigned long parent_rate)
+{
+ struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
+ unsigned long arefdiv, reg, mdiv;
+ unsigned long long vco_freq;
+
+ /* read VCO1 reg for numerator and denominator */
+ reg = readl(socfpgaclk->hw.reg);
+ arefdiv = (reg & SOCFPGA_PLL_AREFDIV_MASK) >> SOCFPGA_PLL_REFDIV_SHIFT;
+
+ vco_freq = (unsigned long long)parent_rate / arefdiv;
+
+ /* Read mdiv and fdiv from the fdbck register */
+ reg = readl(socfpgaclk->hw.reg + 0x24);
+ mdiv = (reg & SOCFPGA_AGILEX_PLL_MDIV_MASK);
+
+ vco_freq = (unsigned long long)vco_freq * mdiv;
+ return (unsigned long)vco_freq;
+}
+
static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
unsigned long parent_rate)
{
@@ -98,6 +123,12 @@ static int clk_pll_prepare(struct clk_hw *hwclk)
return 0;
}
+static struct clk_ops agilex_clk_pll_ops = {
+ .recalc_rate = agilex_clk_pll_recalc_rate,
+ .get_parent = clk_pll_get_parent,
+ .prepare = clk_pll_prepare,
+};
+
static struct clk_ops clk_pll_ops = {
.recalc_rate = clk_pll_recalc_rate,
.get_parent = clk_pll_get_parent,
@@ -148,3 +179,42 @@ struct clk *s10_register_pll(const struct stratix10_pll_clock *clks,
}
return clk;
}
+
+struct clk *agilex_register_pll(const struct stratix10_pll_clock *clks,
+ void __iomem *reg)
+{
+ struct clk *clk;
+ struct socfpga_pll *pll_clk;
+ struct clk_init_data init;
+ const char *name = clks->name;
+
+ pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
+ if (WARN_ON(!pll_clk))
+ return NULL;
+
+ pll_clk->hw.reg = reg + clks->offset;
+
+ if (streq(name, SOCFPGA_BOOT_CLK))
+ init.ops = &clk_boot_ops;
+ else
+ init.ops = &agilex_clk_pll_ops;
+
+ init.name = name;
+ init.flags = clks->flags;
+
+ init.num_parents = clks->num_parents;
+ init.parent_names = NULL;
+ init.parent_data = clks->parent_data;
+ pll_clk->hw.hw.init = &init;
+
+ pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
+ clk_pll_ops.enable = clk_gate_ops.enable;
+ clk_pll_ops.disable = clk_gate_ops.disable;
+
+ clk = clk_register(NULL, &pll_clk->hw.hw);
+ if (WARN_ON(IS_ERR(clk))) {
+ kfree(pll_clk);
+ return NULL;
+ }
+ return clk;
+}
diff --git a/drivers/clk/socfpga/stratix10-clk.h b/drivers/clk/socfpga/stratix10-clk.h
index ffbd1fb2c8ef..f9d5d724c694 100644
--- a/drivers/clk/socfpga/stratix10-clk.h
+++ b/drivers/clk/socfpga/stratix10-clk.h
@@ -62,6 +62,8 @@ struct stratix10_gate_clock {
struct clk *s10_register_pll(const struct stratix10_pll_clock *,
void __iomem *);
+struct clk *agilex_register_pll(const struct stratix10_pll_clock *,
+ void __iomem *);
struct clk *s10_register_periph(const struct stratix10_perip_c_clock *,
void __iomem *);
struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *,
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCHv2 2/3] dt-bindings: documentation: add clock bindings information for Agilex
2020-03-09 17:16 ` [PATCHv2 2/3] dt-bindings: documentation: add clock bindings information for Agilex Dinh Nguyen
@ 2020-03-09 22:30 ` Stephen Boyd
2020-03-10 18:36 ` Rob Herring
1 sibling, 0 replies; 7+ messages in thread
From: Stephen Boyd @ 2020-03-09 22:30 UTC (permalink / raw)
To: Dinh Nguyen, linux-clk
Cc: dinguyen, linux-kernel, devicetree, mturquette, robh+dt, mark.rutland
Quoting Dinh Nguyen (2020-03-09 10:16:52)
> diff --git a/Documentation/devicetree/bindings/clock/intc,agilex.yaml b/Documentation/devicetree/bindings/clock/intc,agilex.yaml
> new file mode 100644
> index 000000000000..bd5c4f590e12
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/intc,agilex.yaml
> @@ -0,0 +1,79 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/intc,agilex.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Intel SoCFPGA Agilex platform clock controller binding
> +
> +maintainers:
> + - Dinh Nguyen <dinguyen@kernel.org>
> +
> +description: |
> + The Intel Agilex Clock controller is an integrated clock controller, which
> + generates and supplies to all modules.
> +
> + This binding uses the common clock binding[1].
> + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
I think you can remove this last sentence, and drop the | on the
description because formatting doesn't matter.
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - enum:
> + - intel,agilex-clkmgr
> +
Just use
compatible:
const: intel,agilex-clkmgr
> + '#clock-cells':
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> + - '#clock-cells'
> +
> +examples:
> + # Clock controller node
> + - |
> + clkmgr: clock-controller@ffd10000 {
> + compatible = "intel,agilex-clkmgr";
> + reg = <0xffd10000 0x1000>;
> + #clock-cells = <1>;
Does it consume any clks?
> + };
> +
> + # External clocks
Everything below here is not necessary and shouldn't be in the binding.
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCHv2 3/3] clk: socfpga: agilex: add clock driver for the Agilex platform
2020-03-09 17:16 ` [PATCHv2 3/3] clk: socfpga: agilex: add clock driver for the Agilex platform Dinh Nguyen
@ 2020-03-09 22:36 ` Stephen Boyd
0 siblings, 0 replies; 7+ messages in thread
From: Stephen Boyd @ 2020-03-09 22:36 UTC (permalink / raw)
To: Dinh Nguyen, linux-clk
Cc: dinguyen, linux-kernel, devicetree, mturquette, robh+dt, mark.rutland
Quoting Dinh Nguyen (2020-03-09 10:16:53)
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index f4169cc2fd31..d9ddc0bd91c0 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -18,6 +18,7 @@ endif
>
> # hardware specific clock types
> # please keep this section sorted lexicographically by file path name
> +obj-$(CONFIG_ARCH_AGILEX) += socfpga/
This is not sorted by file path name.
> obj-$(CONFIG_MACH_ASM9260) += clk-asm9260.o
> obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o
> obj-$(CONFIG_ARCH_AXXIA) += clk-axm5516.o
> diff --git a/drivers/clk/socfpga/clk-agilex.c b/drivers/clk/socfpga/clk-agilex.c
> new file mode 100644
> index 000000000000..6789892085db
> --- /dev/null
> +++ b/drivers/clk/socfpga/clk-agilex.c
> @@ -0,0 +1,369 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2019, Intel Corporation
> + */
> +#include <linux/slab.h>
> +#include <linux/clk-provider.h>
> +#include <linux/of_device.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +
> +#include <dt-bindings/clock/agilex-clock.h>
> +
> +#include "stratix10-clk.h"
[...]
> +static const struct clk_parent_data emac_mux[] = {
> + { .name = "emaca_free_clk", },
> + { .name = "emacb_free_clk", },
> +};
Why no newlines between structures?
> +static const struct clk_parent_data noc_mux[] = {
> + { .name = "noc_free_clk", },
> + { .name = "boot_clk", },
> +};
As stated before, please use actual pointers for clks within the
controller and use .fw_name for clks outside of the controller.
> +
> +/* clocks in AO (always on) controller */
> +static const struct stratix10_pll_clock agilex_pll_clks[] = {
> + { AGILEX_BOOT_CLK, "boot_clk", boot_mux, ARRAY_SIZE(boot_mux), 0,
> + 0x0},
> + { AGILEX_MAIN_PLL_CLK, "main_pll", pll_mux, ARRAY_SIZE(pll_mux),
> + 0, 0x48},
> + { AGILEX_PERIPH_PLL_CLK, "periph_pll", pll_mux, ARRAY_SIZE(pll_mux),
> + 0, 0x9c},
> +};
> +
> +static const struct stratix10_perip_c_clock agilex_main_perip_c_clks[] = {
> + { AGILEX_MAIN_PLL_C0_CLK, "main_pll_c0", "main_pll", NULL, 1, 0, 0x58},
> + { AGILEX_MAIN_PLL_C1_CLK, "main_pll_c1", "main_pll", NULL, 1, 0, 0x5C},
> + { AGILEX_MAIN_PLL_C2_CLK, "main_pll_c2", "main_pll", NULL, 1, 0, 0x64},
> + { AGILEX_MAIN_PLL_C3_CLK, "main_pll_c3", "main_pll", NULL, 1, 0, 0x68},
> + { AGILEX_PERIPH_PLL_C0_CLK, "peri_pll_c0", "periph_pll", NULL, 1, 0, 0xAC},
> + { AGILEX_PERIPH_PLL_C1_CLK, "peri_pll_c1", "periph_pll", NULL, 1, 0, 0xB0},
> + { AGILEX_PERIPH_PLL_C2_CLK, "peri_pll_c2", "periph_pll", NULL, 1, 0, 0xB8},
> + { AGILEX_PERIPH_PLL_C3_CLK, "peri_pll_c3", "periph_pll", NULL, 1, 0, 0xBC},
> +};
> +
> +static const struct stratix10_perip_cnt_clock agilex_main_perip_cnt_clks[] = {
> + { AGILEX_MPU_FREE_CLK, "mpu_free_clk", NULL, mpu_free_mux, ARRAY_SIZE(mpu_free_mux),
> + 0, 0x3C, 0, 0, 0},
> + { AGILEX_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux, ARRAY_SIZE(noc_free_mux),
> + 0, 0x40, 0, 0, 1},
> + { AGILEX_L4_SYS_FREE_CLK, "l4_sys_free_clk", "noc_free_clk", NULL, 1, 0,
> + 0, 4, 0, 0},
> + { AGILEX_NOC_CLK, "noc_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux),
> + 0, 0, 0, 0x30, 1},
> + { AGILEX_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux, ARRAY_SIZE(emaca_free_mux),
> + 0, 0xD4, 0, 0x88, 0},
> + { AGILEX_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux, ARRAY_SIZE(emacb_free_mux),
> + 0, 0xD8, 0, 0x88, 1},
> + { AGILEX_EMAC_PTP_FREE_CLK, "emac_ptp_free_clk", NULL, emac_ptp_free_mux,
> + ARRAY_SIZE(emac_ptp_free_mux), 0, 0xDC, 0, 0x88, 2},
> + { AGILEX_GPIO_DB_FREE_CLK, "gpio_db_free_clk", NULL, gpio_db_free_mux,
> + ARRAY_SIZE(gpio_db_free_mux), 0, 0xE0, 0, 0x88, 3},
> + { AGILEX_SDMMC_FREE_CLK, "sdmmc_free_clk", NULL, sdmmc_free_mux,
> + ARRAY_SIZE(sdmmc_free_mux), 0, 0xE4, 0, 0x88, 4},
> + { AGILEX_S2F_USER0_FREE_CLK, "s2f_user0_free_clk", NULL, s2f_usr0_free_mux,
> + ARRAY_SIZE(s2f_usr0_free_mux), 0, 0xE8, 0, 0, 0},
> + { AGILEX_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL, s2f_usr1_free_mux,
> + ARRAY_SIZE(s2f_usr1_free_mux), 0, 0xEC, 0, 0x88, 5},
> + { AGILEX_PSI_REF_FREE_CLK, "psi_ref_free_clk", NULL, psi_ref_free_mux,
> + ARRAY_SIZE(psi_ref_free_mux), 0, 0xF0, 0, 0x88, 6},
> +};
> +
> +static const struct stratix10_gate_clock agilex_gate_clks[] = {
> + { AGILEX_MPU_CLK, "mpu_clk", NULL, mpu_mux, ARRAY_SIZE(mpu_mux), 0, 0x24,
> + 0, 0, 0, 0, 0x30, 0, 0},
> + { AGILEX_MPU_PERIPH_CLK, "mpu_periph_clk", "mpu_clk", NULL, 1, 0, 0x24,
> + 0, 0, 0, 0, 0, 0, 4},
> + { AGILEX_MPU_L2RAM_CLK, "mpu_l2ram_clk", "mpu_clk", NULL, 1, 0, 0x24,
> + 0, 0, 0, 0, 0, 0, 2},
> + { AGILEX_L4_MAIN_CLK, "l4_main_clk", "noc_clk", NULL, 1, 0, 0x24,
> + 1, 0x44, 0, 2, 0, 0, 0},
> + { AGILEX_L4_MP_CLK, "l4_mp_clk", "noc_clk", NULL, 1, 0, 0x24,
> + 2, 0x44, 8, 2, 0, 0, 0},
> + { AGILEX_L4_SP_CLK, "l4_sp_clk", "noc_clk", NULL, 1, CLK_IS_CRITICAL, 0x24,
Please comment in the code why CLK_IS_CRITICAL is used.
> + 3, 0x44, 16, 2, 0, 0, 0},
> + { AGILEX_CS_AT_CLK, "cs_at_clk", "noc_clk", NULL, 1, 0, 0x24,
> + 4, 0x44, 24, 2, 0, 0, 0},
> + { AGILEX_CS_TRACE_CLK, "cs_trace_clk", "noc_clk", NULL, 1, 0, 0x24,
> + 4, 0x44, 26, 2, 0, 0, 0},
> + { AGILEX_CS_PDBG_CLK, "cs_pdbg_clk", "cs_at_clk", NULL, 1, 0, 0x24,
> + 4, 0x44, 28, 1, 0, 0, 0},
> + { AGILEX_CS_TIMER_CLK, "cs_timer_clk", "noc_clk", NULL, 1, 0, 0x24,
> + 5, 0, 0, 0, 0, 0, 0},
> + { AGILEX_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_usr0_mux, ARRAY_SIZE(s2f_usr0_mux), 0, 0x24,
> + 6, 0, 0, 0, 0, 0, 0},
> + { AGILEX_EMAC0_CLK, "emac0_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C,
> + 0, 0, 0, 0, 0x94, 26, 0},
> + { AGILEX_EMAC1_CLK, "emac1_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C,
> + 1, 0, 0, 0, 0x94, 27, 0},
[..]
> +
> +static struct stratix10_clock_data *__socfpga_agilex_clk_init(struct platform_device *pdev,
> + int nr_clks)
> +{
> + struct device_node *np = pdev->dev.of_node;
> + struct device *dev = &pdev->dev;
> + struct stratix10_clock_data *clk_data;
> + struct clk **clk_table;
> + struct resource *res;
> + void __iomem *base;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(base)) {
> + pr_err("%s: failed to map clock registers\n", __func__);
ioremap fail usually prints an error message already. This is not
needed.
> + return ERR_CAST(base);
> + }
> +
> + clk_data = devm_kzalloc(dev, sizeof(*clk_data), GFP_KERNEL);
> + if (!clk_data)
> + return ERR_PTR(-ENOMEM);
> +
> + clk_data->base = base;
> + clk_table = devm_kcalloc(dev, nr_clks, sizeof(*clk_table), GFP_KERNEL);
> + if (!clk_table)
> + return ERR_PTR(-ENOMEM);
> +
> + clk_data->clk_data.clks = clk_table;
> + clk_data->clk_data.clk_num = nr_clks;
> + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data);
What if this fails?
> + return clk_data;
> +}
> +
> +static int agilex_clkmgr_init(struct platform_device *pdev)
> +{
> + struct stratix10_clock_data *clk_data;
> +
> + clk_data = __socfpga_agilex_clk_init(pdev, AGILEX_NUM_CLKS);
> + if (IS_ERR(clk_data))
> + return PTR_ERR(clk_data);
> +
> + agilex_clk_register_pll(agilex_pll_clks, ARRAY_SIZE(agilex_pll_clks), clk_data);
> +
> + agilex_clk_register_c_perip(agilex_main_perip_c_clks,
> + ARRAY_SIZE(agilex_main_perip_c_clks), clk_data);
> +
> + agilex_clk_register_cnt_perip(agilex_main_perip_cnt_clks,
> + ARRAY_SIZE(agilex_main_perip_cnt_clks),
> + clk_data);
> +
> + agilex_clk_register_gate(agilex_gate_clks, ARRAY_SIZE(agilex_gate_clks),
> + clk_data);
> + return 0;
> +}
> +
> +static int agilex_clkmgr_probe(struct platform_device *pdev)
> +{
> + return agilex_clkmgr_init(pdev);
Why not just put the contents of that here in probe?
> +}
> +
> +static const struct of_device_id agilex_clkmgr_match_table[] = {
> + { .compatible = "intel,agilex-clkmgr",
> + .data = agilex_clkmgr_init },
> + { }
> +};
> +
> +static struct platform_driver agilex_clkmgr_driver = {
> + .probe = agilex_clkmgr_probe,
> + .driver = {
> + .name = "agilex-clkmgr",
> + .suppress_bind_attrs = true,
> + .of_match_table = agilex_clkmgr_match_table,
> + },
> +};
> +
> +static int __init agilex_clk_init(void)
> +{
> + return platform_driver_register(&agilex_clkmgr_driver);
> +}
> +core_initcall(agilex_clk_init);
> diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pll-s10.c
> index bcd3f14e9145..17fe5bd2c0e1 100644
> --- a/drivers/clk/socfpga/clk-pll-s10.c
> +++ b/drivers/clk/socfpga/clk-pll-s10.c
> @@ -27,6 +31,27 @@
>
> #define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw)
>
> +static unsigned long agilex_clk_pll_recalc_rate(struct clk_hw *hwclk,
> + unsigned long parent_rate)
> +{
> + struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
> + unsigned long arefdiv, reg, mdiv;
> + unsigned long long vco_freq;
> +
> + /* read VCO1 reg for numerator and denominator */
> + reg = readl(socfpgaclk->hw.reg);
> + arefdiv = (reg & SOCFPGA_PLL_AREFDIV_MASK) >> SOCFPGA_PLL_REFDIV_SHIFT;
> +
> + vco_freq = (unsigned long long)parent_rate / arefdiv;
> +
> + /* Read mdiv and fdiv from the fdbck register */
> + reg = readl(socfpgaclk->hw.reg + 0x24);
> + mdiv = (reg & SOCFPGA_AGILEX_PLL_MDIV_MASK);
Please remove useless parenthesis.
> +
> + vco_freq = (unsigned long long)vco_freq * mdiv;
> + return (unsigned long)vco_freq;
Drop the cast, it's implicit.
> +}
> +
> static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
> unsigned long parent_rate)
> {
> @@ -98,6 +123,12 @@ static int clk_pll_prepare(struct clk_hw *hwclk)
> return 0;
> }
>
> +static struct clk_ops agilex_clk_pll_ops = {
Can it be const?
> + .recalc_rate = agilex_clk_pll_recalc_rate,
> + .get_parent = clk_pll_get_parent,
> + .prepare = clk_pll_prepare,
> +};
> +
> static struct clk_ops clk_pll_ops = {
I guess this one could be const too, but in a different patch?
> .recalc_rate = clk_pll_recalc_rate,
> .get_parent = clk_pll_get_parent,
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCHv2 2/3] dt-bindings: documentation: add clock bindings information for Agilex
2020-03-09 17:16 ` [PATCHv2 2/3] dt-bindings: documentation: add clock bindings information for Agilex Dinh Nguyen
2020-03-09 22:30 ` Stephen Boyd
@ 2020-03-10 18:36 ` Rob Herring
1 sibling, 0 replies; 7+ messages in thread
From: Rob Herring @ 2020-03-10 18:36 UTC (permalink / raw)
To: Dinh Nguyen
Cc: linux-clk, dinguyen, linux-kernel, devicetree, sboyd, mturquette,
robh+dt, mark.rutland
On Mon, 9 Mar 2020 12:16:52 -0500, Dinh Nguyen wrote:
> Document the Agilex clock bindings, and add the clock header file. The
> clock header is an enumeration of all the different clocks on the Agilex
> platform.
>
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---
> v2: convert original document to YAML
> ---
> .../bindings/clock/intc,agilex.yaml | 79 +++++++++++++++++++
> include/dt-bindings/clock/agilex-clock.h | 70 ++++++++++++++++
> 2 files changed, 149 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/intc,agilex.yaml
> create mode 100644 include/dt-bindings/clock/agilex-clock.h
>
My bot found errors running 'make dt_binding_check' on your patch:
Documentation/devicetree/bindings/clock/intc,agilex.yaml: while scanning a block scalar
in "<unicode string>", line 36, column 5
found a tab character where an indentation space is expected
in "<unicode string>", line 37, column 1
Documentation/devicetree/bindings/Makefile:12: recipe for target 'Documentation/devicetree/bindings/clock/intc,agilex.example.dts' failed
make[1]: *** [Documentation/devicetree/bindings/clock/intc,agilex.example.dts] Error 1
make[1]: *** Waiting for unfinished jobs....
warning: no schema found in file: Documentation/devicetree/bindings/clock/intc,agilex.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/clock/intc,agilex.yaml: ignoring, error parsing file
Makefile:1262: recipe for target 'dt_binding_check' failed
make: *** [dt_binding_check] Error 2
See https://patchwork.ozlabs.org/patch/1251669
Please check and re-submit.
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2020-03-10 18:36 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-03-09 17:16 [PATCHv2 0/3] clk: agilex: add clock driver Dinh Nguyen
2020-03-09 17:16 ` [PATCH RESEND 1/3] clk: socfpga: stratix10: use new parent data scheme Dinh Nguyen
2020-03-09 17:16 ` [PATCHv2 2/3] dt-bindings: documentation: add clock bindings information for Agilex Dinh Nguyen
2020-03-09 22:30 ` Stephen Boyd
2020-03-10 18:36 ` Rob Herring
2020-03-09 17:16 ` [PATCHv2 3/3] clk: socfpga: agilex: add clock driver for the Agilex platform Dinh Nguyen
2020-03-09 22:36 ` Stephen Boyd
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