* [PATCH V2 0/3] iio: adc: Add support for QCOM SPMI PMIC7 ADC
@ 2020-04-15 9:17 Jishnu Prakash
2020-04-15 9:17 ` [PATCH V2 1/3] iio: adc: Convert the QCOM SPMI ADC bindings to .yaml format Jishnu Prakash
` (2 more replies)
0 siblings, 3 replies; 15+ messages in thread
From: Jishnu Prakash @ 2020-04-15 9:17 UTC (permalink / raw)
To: agross, bjorn.andersson, devicetree, linux-kernel, mka,
linus.walleij, Jonathan.Cameron, smohanad, kgunda, aghayal
Cc: linux-arm-msm, linux-arm-msm-owner, Jishnu Prakash
The following changes are made in V2 for the three patches:
Added checks for the values of some ADC DT properties in the first patch,
wherever applicable. Also updated channel node regex and provided example.
Added the DT header files in the second patch, previously
added in third patch.
Removed the DT header files and made several recommended minor changes
in the third patch.
Jishnu Prakash (3):
iio: adc: Convert the QCOM SPMI ADC bindings to .yaml format
iio: adc: Add PMIC7 ADC bindings
iio: adc: Add support for PMIC7 ADC
.../devicetree/bindings/iio/adc/qcom,spmi-vadc.txt | 173 --------------
.../bindings/iio/adc/qcom,spmi-vadc.yaml | 214 +++++++++++++++++
drivers/iio/adc/qcom-spmi-adc5.c | 257 ++++++++++++++++++--
drivers/iio/adc/qcom-vadc-common.c | 258 +++++++++++++++++++++
drivers/iio/adc/qcom-vadc-common.h | 15 ++
include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h | 67 ++++++
include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h | 88 +++++++
include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h | 46 ++++
include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h | 28 +++
include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h | 28 +++
include/dt-bindings/iio/qcom,spmi-vadc.h | 78 ++++++-
11 files changed, 1065 insertions(+), 187 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt
create mode 100644 Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
create mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h
create mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h
create mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h
create mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h
create mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH V2 1/3] iio: adc: Convert the QCOM SPMI ADC bindings to .yaml format 2020-04-15 9:17 [PATCH V2 0/3] iio: adc: Add support for QCOM SPMI PMIC7 ADC Jishnu Prakash @ 2020-04-15 9:17 ` Jishnu Prakash 2020-04-16 20:42 ` Rob Herring 2020-04-18 16:22 ` Jonathan Cameron 2020-04-15 9:17 ` [PATCH V2 2/3] iio: adc: Add PMIC7 ADC bindings Jishnu Prakash 2020-04-15 9:17 ` [PATCH V2 3/3] iio: adc: Add support for PMIC7 ADC Jishnu Prakash 2 siblings, 2 replies; 15+ messages in thread From: Jishnu Prakash @ 2020-04-15 9:17 UTC (permalink / raw) To: agross, bjorn.andersson, devicetree, linux-kernel, mka, linus.walleij, Jonathan.Cameron, smohanad, kgunda, aghayal, Jonathan Cameron, Hartmut Knaack, Lars-Peter Clausen, Peter Meerwald-Stadler, Rob Herring, Mark Rutland, Jishnu Prakash, linux-iio Cc: linux-arm-msm, linux-arm-msm-owner Convert the adc bindings from .txt to .yaml format. Signed-off-by: Jishnu Prakash <jprakash@codeaurora.org> --- .../devicetree/bindings/iio/adc/qcom,spmi-vadc.txt | 173 ------------- .../bindings/iio/adc/qcom,spmi-vadc.yaml | 288 +++++++++++++++++++++ 2 files changed, 288 insertions(+), 173 deletions(-) delete mode 100644 Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt create mode 100644 Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt deleted file mode 100644 index c878768..0000000 --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt +++ /dev/null @@ -1,173 +0,0 @@ -Qualcomm's SPMI PMIC ADC - -- SPMI PMIC voltage ADC (VADC) provides interface to clients to read - voltage. The VADC is a 15-bit sigma-delta ADC. -- SPMI PMIC5 voltage ADC (ADC) provides interface to clients to read - voltage. The VADC is a 16-bit sigma-delta ADC. - -VADC node: - -- compatible: - Usage: required - Value type: <string> - Definition: Should contain "qcom,spmi-vadc". - Should contain "qcom,spmi-adc5" for PMIC5 ADC driver. - Should contain "qcom,spmi-adc-rev2" for PMIC rev2 ADC driver. - Should contain "qcom,pms405-adc" for PMS405 PMIC - -- reg: - Usage: required - Value type: <prop-encoded-array> - Definition: VADC base address in the SPMI PMIC register map. - -- #address-cells: - Usage: required - Value type: <u32> - Definition: Must be one. Child node 'reg' property should define ADC - channel number. - -- #size-cells: - Usage: required - Value type: <u32> - Definition: Must be zero. - -- #io-channel-cells: - Usage: required - Value type: <u32> - Definition: Must be one. For details about IIO bindings see: - Documentation/devicetree/bindings/iio/iio-bindings.txt - -- interrupts: - Usage: optional - Value type: <prop-encoded-array> - Definition: End of conversion interrupt. - -Channel node properties: - -- reg: - Usage: required - Value type: <u32> - Definition: ADC channel number. - See include/dt-bindings/iio/qcom,spmi-vadc.h - -- label: - Usage: required for "qcom,spmi-adc5" and "qcom,spmi-adc-rev2" - Value type: <empty> - Definition: ADC input of the platform as seen in the schematics. - For thermistor inputs connected to generic AMUX or GPIO inputs - these can vary across platform for the same pins. Hence select - the platform schematics name for this channel. - -- qcom,decimation: - Usage: optional - Value type: <u32> - Definition: This parameter is used to decrease ADC sampling rate. - Quicker measurements can be made by reducing decimation ratio. - - For compatible property "qcom,spmi-vadc", valid values are - 512, 1024, 2048, 4096. If property is not found, default value - of 512 will be used. - - For compatible property "qcom,spmi-adc5", valid values are 250, 420 - and 840. If property is not found, default value of 840 is used. - - For compatible property "qcom,spmi-adc-rev2", valid values are 256, - 512 and 1024. If property is not present, default value is 1024. - -- qcom,pre-scaling: - Usage: optional - Value type: <u32 array> - Definition: Used for scaling the channel input signal before the signal is - fed to VADC. The configuration for this node is to know the - pre-determined ratio and use it for post scaling. Select one from - the following options. - <1 1>, <1 3>, <1 4>, <1 6>, <1 20>, <1 8>, <10 81>, <1 10> - If property is not found default value depending on chip will be used. - -- qcom,ratiometric: - Usage: optional - Value type: <empty> - Definition: Channel calibration type. - - For compatible property "qcom,spmi-vadc", if this property is - specified VADC will use the VDD reference (1.8V) and GND for - channel calibration. If property is not found, channel will be - calibrated with 0.625V and 1.25V reference channels, also - known as absolute calibration. - - For compatible property "qcom,spmi-adc5" and "qcom,spmi-adc-rev2", - if this property is specified VADC will use the VDD reference - (1.875V) and GND for channel calibration. If property is not found, - channel will be calibrated with 0V and 1.25V reference channels, - also known as absolute calibration. - -- qcom,hw-settle-time: - Usage: optional - Value type: <u32> - Definition: Time between AMUX getting configured and the ADC starting - conversion. The 'hw_settle_time' is an index used from valid values - and programmed in hardware to achieve the hardware settling delay. - - For compatible property "qcom,spmi-vadc" and "qcom,spmi-adc-rev2", - Delay = 100us * (hw_settle_time) for hw_settle_time < 11, - and 2ms * (hw_settle_time - 10) otherwise. - Valid values are: 0, 100, 200, 300, 400, 500, 600, 700, 800, - 900 us and 1, 2, 4, 6, 8, 10 ms. - If property is not found, channel will use 0us. - - For compatible property "qcom,spmi-adc5", delay = 15us for - value 0, 100us * (value) for values < 11, - and 2ms * (value - 10) otherwise. - Valid values are: 15, 100, 200, 300, 400, 500, 600, 700, 800, - 900 us and 1, 2, 4, 6, 8, 10 ms - Certain controller digital versions have valid values of - 15, 100, 200, 300, 400, 500, 600, 700, 1, 2, 4, 8, 16, 32, 64, 128 ms - If property is not found, channel will use 15us. - -- qcom,avg-samples: - Usage: optional - Value type: <u32> - Definition: Number of samples to be used for measurement. - Averaging provides the option to obtain a single measurement - from the ADC that is an average of multiple samples. The value - selected is 2^(value). - - For compatible property "qcom,spmi-vadc", valid values - are: 1, 2, 4, 8, 16, 32, 64, 128, 256, 512 - If property is not found, 1 sample will be used. - - For compatible property "qcom,spmi-adc5" and "qcom,spmi-adc-rev2", - valid values are: 1, 2, 4, 8, 16 - If property is not found, 1 sample will be used. - -NOTE: - -For compatible property "qcom,spmi-vadc" following channels, also known as -reference point channels, are used for result calibration and their channel -configuration nodes should be defined: -VADC_REF_625MV and/or VADC_SPARE1(based on PMIC version) VADC_REF_1250MV, -VADC_GND_REF and VADC_VDD_VADC. - -Example: - -#include <dt-bindings/iio/qcom,spmi-vadc.h> -#include <linux/irq.h> -/* ... */ - - /* VADC node */ - pmic_vadc: vadc@3100 { - compatible = "qcom,spmi-vadc"; - reg = <0x3100>; - interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - #io-channel-cells = <1>; - io-channel-ranges; - - /* Channel node */ - adc-chan@VADC_LR_MUX10_USB_ID { - reg = <VADC_LR_MUX10_USB_ID>; - qcom,decimation = <512>; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - qcom,avg-samples = <1>; - qcom,pre-scaling = <1 3>; - }; - }; - - /* IIO client node */ - usb { - io-channels = <&pmic_vadc VADC_LR_MUX10_USB_ID>; - io-channel-names = "vadc"; - }; diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml new file mode 100644 index 0000000..8273981 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml @@ -0,0 +1,288 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/qcom,spmi-vadc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm's SPMI PMIC ADC + +maintainers: + - Andy Gross <agross@kernel.org> + - Bjorn Andersson <bjorn.andersson@linaro.org> + +description: | + SPMI PMIC voltage ADC (VADC) provides interface to clients to read + voltage. The VADC is a 15-bit sigma-delta ADC. + SPMI PMIC5 voltage ADC (ADC) provides interface to clients to read + voltage. The VADC is a 16-bit sigma-delta ADC. + +properties: + compatible: + oneOf: + - items: + - const: qcom,pms405-adc + - const: qcom,spmi-adc-rev2 + + - items: + - enum: + - qcom,spmi-vadc + - qcom,spmi-adc5 + - qcom,spmi-adc-rev2 + + reg: + description: VADC base address in the SPMI PMIC register map + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + '#io-channel-cells': + const: 1 + + interrupts: + maxItems: 1 + description: + End of conversion interrupt. + +required: + - compatible + - reg + - '#address-cells' + - '#size-cells' + - '#io-channel-cells' + +patternProperties: + "^.*@[0-9a-fx]+$": + type: object + description: | + Represents the external channels which are connected to the ADC. + For compatible property "qcom,spmi-vadc" following channels, also known as + reference point channels, are used for result calibration and their channel + configuration nodes should be defined: + VADC_REF_625MV and/or VADC_SPARE1(based on PMIC version) VADC_REF_1250MV, + VADC_GND_REF and VADC_VDD_VADC. + + properties: + reg: + description: | + ADC channel number. + See include/dt-bindings/iio/qcom,spmi-vadc.h + + label: + $ref: /schemas/types.yaml#/definitions/string + description: | + ADC input of the platform as seen in the schematics. + For thermistor inputs connected to generic AMUX or GPIO inputs + these can vary across platform for the same pins. Hence select + the platform schematics name for this channel. + + qcom,decimation: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + This parameter is used to decrease ADC sampling rate. + Quicker measurements can be made by reducing decimation ratio. + - For compatible property "qcom,spmi-vadc", valid values are + 512, 1024, 2048, 4096. If property is not found, default value + of 512 will be used. + - For compatible property "qcom,spmi-adc5", valid values are 250, 420 + and 840. If property is not found, default value of 840 is used. + - For compatible property "qcom,spmi-adc-rev2", valid values are 256, + 512 and 1024. If property is not present, default value is 1024. + + qcom,pre-scaling: + description: | + Used for scaling the channel input signal before the signal is + fed to VADC. The configuration for this node is to know the + pre-determined ratio and use it for post scaling. It is a pair of + integers, denoting the numerator and denominator of the fraction by which + input signal is multiplied. For example, <1 3> indicates the signal is scaled + down to 1/3 of its value before ADC measurement. Select one from + the following options. + <1 1>, <1 3>, <1 4>, <1 6>, <1 20>, <1 8>, <10 81>, <1 10> + If property is not found default value depending on chip will be used. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + oneOf: + - items: + - const: 1 + - enum: [ 1, 3, 4, 6, 20, 8, 10 ] + + - items: + - const: 10 + - const: 81 + + qcom,ratiometric: + description: | + Channel calibration type. + - For compatible property "qcom,spmi-vadc", if this property is + specified VADC will use the VDD reference (1.8V) and GND for + channel calibration. If property is not found, channel will be + calibrated with 0.625V and 1.25V reference channels, also + known as absolute calibration. + - For compatible property "qcom,spmi-adc5" and "qcom,spmi-adc-rev2", + if this property is specified VADC will use the VDD reference (1.875V) + and GND for channel calibration. If property is not found, channel + will be calibrated with 0V and 1.25V reference channels, also known + as absolute calibration. + type: boolean + + qcom,hw-settle-time: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Time between AMUX getting configured and the ADC starting + conversion. The 'hw_settle_time' is an index used from valid values + and programmed in hardware to achieve the hardware settling delay. + - For compatible property "qcom,spmi-vadc" and "qcom,spmi-adc-rev2", + Delay = 100us * (hw_settle_time) for hw_settle_time < 11, + and 2ms * (hw_settle_time - 10) otherwise. + Valid values are: 0, 100, 200, 300, 400, 500, 600, 700, 800, + 900 us and 1, 2, 4, 6, 8, 10 ms. + If property is not found, channel will use 0us. + - For compatible property "qcom,spmi-adc5", delay = 15us for + value 0, 100us * (value) for values < 11, + and 2ms * (value - 10) otherwise. + Valid values are: 15, 100, 200, 300, 400, 500, 600, 700, 800, + 900 us and 1, 2, 4, 6, 8, 10 ms + Certain controller digital versions have valid values of + 15, 100, 200, 300, 400, 500, 600, 700, 1, 2, 4, 8, 16, 32, 64, 128 ms + If property is not found, channel will use 15us. + + qcom,avg-samples: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Number of samples to be used for measurement. + Averaging provides the option to obtain a single measurement + from the ADC that is an average of multiple samples. The value + selected is 2^(value). + - For compatible property "qcom,spmi-vadc", valid values + are: 1, 2, 4, 8, 16, 32, 64, 128, 256, 512 + If property is not found, 1 sample will be used. + + required: + - reg + +allOf: + - if: + properties: + compatible: + contains: + const: qcom,spmi-vadc + + then: + patternProperties: + "^.*@[0-9a-fx]+$": + minItems: 4 + properties: + qcom,decimation: + items: + enum: [ 512, 1024, 2048, 4096 ] + default: 512 + + qcom,hw-settle-time: + items: + enum: [ 0, 100, 200, 300, 400, 500, 600, 700, 800, 900, 1, 2, + 4, 6, 8, 10 ] + default: 0 + + qcom,avg-samples: + items: + enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512 ] + default: 1 + + - if: + properties: + compatible: + contains: + const: qcom,spmi-adc-rev2 + + then: + patternProperties: + "^.*@[0-9a-fx]+$": + properties: + qcom,decimation: + items: + enum: [ 256, 512, 1024 ] + default: 1024 + + qcom,hw-settle-time: + items: + enum: [ 0, 100, 200, 300, 400, 500, 600, 700, 800, 900, 1, 2, + 4, 6, 8, 10 ] + default: 0 + + qcom,avg-samples: + items: + enum: [ 1, 2, 4, 8, 16 ] + default: 1 + + - if: + properties: + compatible: + contains: + const: qcom,spmi-adc5 + + then: + patternProperties: + "^.*@[0-9a-fx]+$": + properties: + qcom,decimation: + items: + enum: [ 250, 420, 840 ] + default: 840 + + qcom,hw-settle-time: + items: + enum: [ 15, 100, 200, 300, 400, 500, 600, 700, 800, 900, 1, 2, + 4, 6, 8, 10, 16, 32, 64, 128 ] + default: 15 + + qcom,avg-samples: + items: + enum: [ 1, 2, 4, 8, 16 ] + default: 1 + +examples: + - | + spmi_bus { + #address-cells = <1>; + #size-cells = <0>; + /* VADC node */ + pmic_vadc: adc@3100 { + compatible = "qcom,spmi-vadc"; + reg = <0x3100>; + interrupts = <0x0 0x31 0x0 0x1>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + io-channel-ranges; + + /* Channel node */ + adc-chan@0x39 { + reg = <0x39>; + qcom,decimation = <512>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,avg-samples = <1>; + qcom,pre-scaling = <1 3>; + }; + + adc-chan@0x9 { + reg = <0x9>; + }; + + adc-chan@0xa { + reg = <0xa>; + }; + + adc-chan@0xe { + reg = <0xe>; + }; + + adc-chan@0xf { + reg = <0xf>; + }; + }; + }; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH V2 1/3] iio: adc: Convert the QCOM SPMI ADC bindings to .yaml format 2020-04-15 9:17 ` [PATCH V2 1/3] iio: adc: Convert the QCOM SPMI ADC bindings to .yaml format Jishnu Prakash @ 2020-04-16 20:42 ` Rob Herring 2020-04-27 12:53 ` Jishnu Prakash 2020-04-18 16:22 ` Jonathan Cameron 1 sibling, 1 reply; 15+ messages in thread From: Rob Herring @ 2020-04-16 20:42 UTC (permalink / raw) To: Jishnu Prakash Cc: agross, bjorn.andersson, devicetree, linux-kernel, mka, linus.walleij, Jonathan.Cameron, smohanad, kgunda, aghayal, Jonathan Cameron, Hartmut Knaack, Lars-Peter Clausen, Peter Meerwald-Stadler, Mark Rutland, Jishnu Prakash, linux-iio, linux-arm-msm, linux-arm-msm-owner On Wed, 15 Apr 2020 14:47:44 +0530, Jishnu Prakash wrote: > Convert the adc bindings from .txt to .yaml format. > > Signed-off-by: Jishnu Prakash <jprakash@codeaurora.org> > --- > .../devicetree/bindings/iio/adc/qcom,spmi-vadc.txt | 173 ------------- > .../bindings/iio/adc/qcom,spmi-vadc.yaml | 288 +++++++++++++++++++++ > 2 files changed, 288 insertions(+), 173 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt > create mode 100644 Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml > My bot found errors running 'make dt_binding_check' on your patch: Documentation/devicetree/bindings/display/simple-framebuffer.example.dts:21.16-37.11: Warning (chosen_node_is_root): /example-0/chosen: chosen node must be at root node /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.example.dt.yaml: adc@3100: 'adc-chan@0x39', 'adc-chan@0x9', 'adc-chan@0xa', 'adc-chan@0xe', 'adc-chan@0xf' do not match any of the regexes: '.*-names$', '.*-supply$', '^#.*-cells$', '^#[a-zA-Z0-9,+\\-._]{0,63}$', '^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}$', '^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-fA-F]+(,[0-9a-fA-F]+)*$', '^__.*__$', 'pinctrl-[0-9]+' See https://patchwork.ozlabs.org/patch/1271025 If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure dt-schema is up to date: pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade Please check and re-submit. ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH V2 1/3] iio: adc: Convert the QCOM SPMI ADC bindings to .yaml format 2020-04-16 20:42 ` Rob Herring @ 2020-04-27 12:53 ` Jishnu Prakash 0 siblings, 0 replies; 15+ messages in thread From: Jishnu Prakash @ 2020-04-27 12:53 UTC (permalink / raw) To: Rob Herring Cc: agross, bjorn.andersson, devicetree, linux-kernel, mka, linus.walleij, Jonathan.Cameron, smohanad, kgunda, aghayal, Jonathan Cameron, Hartmut Knaack, Lars-Peter Clausen, Peter Meerwald-Stadler, Mark Rutland, linux-iio, linux-arm-msm, linux-arm-msm-owner Hi Rob I can see the first error: "....chosen node must be at root node" from 'make dt_binding_check' even without my patch applied, so it does not seem related. I will fix the second error in the next post. On 4/17/2020 2:12 AM, Rob Herring wrote: > On Wed, 15 Apr 2020 14:47:44 +0530, Jishnu Prakash wrote: >> Convert the adc bindings from .txt to .yaml format. >> >> Signed-off-by: Jishnu Prakash <jprakash@codeaurora.org> >> --- >> .../devicetree/bindings/iio/adc/qcom,spmi-vadc.txt | 173 ------------- >> .../bindings/iio/adc/qcom,spmi-vadc.yaml | 288 +++++++++++++++++++++ >> 2 files changed, 288 insertions(+), 173 deletions(-) >> delete mode 100644 Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt >> create mode 100644 Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml >> > My bot found errors running 'make dt_binding_check' on your patch: > > Documentation/devicetree/bindings/display/simple-framebuffer.example.dts:21.16-37.11: Warning (chosen_node_is_root): /example-0/chosen: chosen node must be at root node > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.example.dt.yaml: adc@3100: 'adc-chan@0x39', 'adc-chan@0x9', 'adc-chan@0xa', 'adc-chan@0xe', 'adc-chan@0xf' do not match any of the regexes: '.*-names$', '.*-supply$', '^#.*-cells$', '^#[a-zA-Z0-9,+\\-._]{0,63}$', '^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}$', '^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-fA-F]+(,[0-9a-fA-F]+)*$', '^__.*__$', 'pinctrl-[0-9]+' > > See https://patchwork.ozlabs.org/patch/1271025 > > If you already ran 'make dt_binding_check' and didn't see the above > error(s), then make sure dt-schema is up to date: > > pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade > > Please check and re-submit. ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH V2 1/3] iio: adc: Convert the QCOM SPMI ADC bindings to .yaml format 2020-04-15 9:17 ` [PATCH V2 1/3] iio: adc: Convert the QCOM SPMI ADC bindings to .yaml format Jishnu Prakash 2020-04-16 20:42 ` Rob Herring @ 2020-04-18 16:22 ` Jonathan Cameron 2020-04-27 12:53 ` Jishnu Prakash 1 sibling, 1 reply; 15+ messages in thread From: Jonathan Cameron @ 2020-04-18 16:22 UTC (permalink / raw) To: Jishnu Prakash Cc: agross, bjorn.andersson, devicetree, linux-kernel, mka, linus.walleij, Jonathan.Cameron, smohanad, kgunda, aghayal, Hartmut Knaack, Lars-Peter Clausen, Peter Meerwald-Stadler, Rob Herring, Mark Rutland, linux-iio, linux-arm-msm, linux-arm-msm-owner On Wed, 15 Apr 2020 14:47:44 +0530 Jishnu Prakash <jprakash@codeaurora.org> wrote: > Convert the adc bindings from .txt to .yaml format. > I read patch 2 before this one for some reason but same question applies here Given we are now enforcing a lot of the values explicitly are we better off dropping the text description of that. It looks to me like a potential place to get out of sync given the information is a bit further down. > Signed-off-by: Jishnu Prakash <jprakash@codeaurora.org> > --- > .../devicetree/bindings/iio/adc/qcom,spmi-vadc.txt | 173 ------------- > .../bindings/iio/adc/qcom,spmi-vadc.yaml | 288 +++++++++++++++++++++ > 2 files changed, 288 insertions(+), 173 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt > create mode 100644 Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml > > diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt > deleted file mode 100644 > index c878768..0000000 > --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt > +++ /dev/null > @@ -1,173 +0,0 @@ > -Qualcomm's SPMI PMIC ADC > - > -- SPMI PMIC voltage ADC (VADC) provides interface to clients to read > - voltage. The VADC is a 15-bit sigma-delta ADC. > -- SPMI PMIC5 voltage ADC (ADC) provides interface to clients to read > - voltage. The VADC is a 16-bit sigma-delta ADC. > - > -VADC node: > - > -- compatible: > - Usage: required > - Value type: <string> > - Definition: Should contain "qcom,spmi-vadc". > - Should contain "qcom,spmi-adc5" for PMIC5 ADC driver. > - Should contain "qcom,spmi-adc-rev2" for PMIC rev2 ADC driver. > - Should contain "qcom,pms405-adc" for PMS405 PMIC > - > -- reg: > - Usage: required > - Value type: <prop-encoded-array> > - Definition: VADC base address in the SPMI PMIC register map. > - > -- #address-cells: > - Usage: required > - Value type: <u32> > - Definition: Must be one. Child node 'reg' property should define ADC > - channel number. > - > -- #size-cells: > - Usage: required > - Value type: <u32> > - Definition: Must be zero. > - > -- #io-channel-cells: > - Usage: required > - Value type: <u32> > - Definition: Must be one. For details about IIO bindings see: > - Documentation/devicetree/bindings/iio/iio-bindings.txt > - > -- interrupts: > - Usage: optional > - Value type: <prop-encoded-array> > - Definition: End of conversion interrupt. > - > -Channel node properties: > - > -- reg: > - Usage: required > - Value type: <u32> > - Definition: ADC channel number. > - See include/dt-bindings/iio/qcom,spmi-vadc.h > - > -- label: > - Usage: required for "qcom,spmi-adc5" and "qcom,spmi-adc-rev2" > - Value type: <empty> > - Definition: ADC input of the platform as seen in the schematics. > - For thermistor inputs connected to generic AMUX or GPIO inputs > - these can vary across platform for the same pins. Hence select > - the platform schematics name for this channel. > - > -- qcom,decimation: > - Usage: optional > - Value type: <u32> > - Definition: This parameter is used to decrease ADC sampling rate. > - Quicker measurements can be made by reducing decimation ratio. > - - For compatible property "qcom,spmi-vadc", valid values are > - 512, 1024, 2048, 4096. If property is not found, default value > - of 512 will be used. > - - For compatible property "qcom,spmi-adc5", valid values are 250, 420 > - and 840. If property is not found, default value of 840 is used. > - - For compatible property "qcom,spmi-adc-rev2", valid values are 256, > - 512 and 1024. If property is not present, default value is 1024. > - > -- qcom,pre-scaling: > - Usage: optional > - Value type: <u32 array> > - Definition: Used for scaling the channel input signal before the signal is > - fed to VADC. The configuration for this node is to know the > - pre-determined ratio and use it for post scaling. Select one from > - the following options. > - <1 1>, <1 3>, <1 4>, <1 6>, <1 20>, <1 8>, <10 81>, <1 10> > - If property is not found default value depending on chip will be used. > - > -- qcom,ratiometric: > - Usage: optional > - Value type: <empty> > - Definition: Channel calibration type. > - - For compatible property "qcom,spmi-vadc", if this property is > - specified VADC will use the VDD reference (1.8V) and GND for > - channel calibration. If property is not found, channel will be > - calibrated with 0.625V and 1.25V reference channels, also > - known as absolute calibration. > - - For compatible property "qcom,spmi-adc5" and "qcom,spmi-adc-rev2", > - if this property is specified VADC will use the VDD reference > - (1.875V) and GND for channel calibration. If property is not found, > - channel will be calibrated with 0V and 1.25V reference channels, > - also known as absolute calibration. > - > -- qcom,hw-settle-time: > - Usage: optional > - Value type: <u32> > - Definition: Time between AMUX getting configured and the ADC starting > - conversion. The 'hw_settle_time' is an index used from valid values > - and programmed in hardware to achieve the hardware settling delay. > - - For compatible property "qcom,spmi-vadc" and "qcom,spmi-adc-rev2", > - Delay = 100us * (hw_settle_time) for hw_settle_time < 11, > - and 2ms * (hw_settle_time - 10) otherwise. > - Valid values are: 0, 100, 200, 300, 400, 500, 600, 700, 800, > - 900 us and 1, 2, 4, 6, 8, 10 ms. > - If property is not found, channel will use 0us. > - - For compatible property "qcom,spmi-adc5", delay = 15us for > - value 0, 100us * (value) for values < 11, > - and 2ms * (value - 10) otherwise. > - Valid values are: 15, 100, 200, 300, 400, 500, 600, 700, 800, > - 900 us and 1, 2, 4, 6, 8, 10 ms > - Certain controller digital versions have valid values of > - 15, 100, 200, 300, 400, 500, 600, 700, 1, 2, 4, 8, 16, 32, 64, 128 ms > - If property is not found, channel will use 15us. > - > -- qcom,avg-samples: > - Usage: optional > - Value type: <u32> > - Definition: Number of samples to be used for measurement. > - Averaging provides the option to obtain a single measurement > - from the ADC that is an average of multiple samples. The value > - selected is 2^(value). > - - For compatible property "qcom,spmi-vadc", valid values > - are: 1, 2, 4, 8, 16, 32, 64, 128, 256, 512 > - If property is not found, 1 sample will be used. > - - For compatible property "qcom,spmi-adc5" and "qcom,spmi-adc-rev2", > - valid values are: 1, 2, 4, 8, 16 > - If property is not found, 1 sample will be used. > - > -NOTE: > - > -For compatible property "qcom,spmi-vadc" following channels, also known as > -reference point channels, are used for result calibration and their channel > -configuration nodes should be defined: > -VADC_REF_625MV and/or VADC_SPARE1(based on PMIC version) VADC_REF_1250MV, > -VADC_GND_REF and VADC_VDD_VADC. > - > -Example: > - > -#include <dt-bindings/iio/qcom,spmi-vadc.h> > -#include <linux/irq.h> > -/* ... */ > - > - /* VADC node */ > - pmic_vadc: vadc@3100 { > - compatible = "qcom,spmi-vadc"; > - reg = <0x3100>; > - interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; > - #address-cells = <1>; > - #size-cells = <0>; > - #io-channel-cells = <1>; > - io-channel-ranges; > - > - /* Channel node */ > - adc-chan@VADC_LR_MUX10_USB_ID { > - reg = <VADC_LR_MUX10_USB_ID>; > - qcom,decimation = <512>; > - qcom,ratiometric; > - qcom,hw-settle-time = <200>; > - qcom,avg-samples = <1>; > - qcom,pre-scaling = <1 3>; > - }; > - }; > - > - /* IIO client node */ > - usb { > - io-channels = <&pmic_vadc VADC_LR_MUX10_USB_ID>; > - io-channel-names = "vadc"; > - }; > diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml > new file mode 100644 > index 0000000..8273981 > --- /dev/null > +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml > @@ -0,0 +1,288 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/iio/adc/qcom,spmi-vadc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm's SPMI PMIC ADC > + > +maintainers: > + - Andy Gross <agross@kernel.org> > + - Bjorn Andersson <bjorn.andersson@linaro.org> > + > +description: | > + SPMI PMIC voltage ADC (VADC) provides interface to clients to read > + voltage. The VADC is a 15-bit sigma-delta ADC. > + SPMI PMIC5 voltage ADC (ADC) provides interface to clients to read > + voltage. The VADC is a 16-bit sigma-delta ADC. > + > +properties: > + compatible: > + oneOf: > + - items: > + - const: qcom,pms405-adc > + - const: qcom,spmi-adc-rev2 > + > + - items: > + - enum: > + - qcom,spmi-vadc > + - qcom,spmi-adc5 > + - qcom,spmi-adc-rev2 > + > + reg: > + description: VADC base address in the SPMI PMIC register map > + maxItems: 1 > + > + '#address-cells': > + const: 1 > + > + '#size-cells': > + const: 0 > + > + '#io-channel-cells': > + const: 1 > + > + interrupts: > + maxItems: 1 > + description: > + End of conversion interrupt. > + > +required: > + - compatible > + - reg > + - '#address-cells' > + - '#size-cells' > + - '#io-channel-cells' > + > +patternProperties: > + "^.*@[0-9a-fx]+$": > + type: object > + description: | > + Represents the external channels which are connected to the ADC. > + For compatible property "qcom,spmi-vadc" following channels, also known as > + reference point channels, are used for result calibration and their channel > + configuration nodes should be defined: > + VADC_REF_625MV and/or VADC_SPARE1(based on PMIC version) VADC_REF_1250MV, > + VADC_GND_REF and VADC_VDD_VADC. > + > + properties: > + reg: > + description: | > + ADC channel number. > + See include/dt-bindings/iio/qcom,spmi-vadc.h > + > + label: > + $ref: /schemas/types.yaml#/definitions/string > + description: | > + ADC input of the platform as seen in the schematics. > + For thermistor inputs connected to generic AMUX or GPIO inputs > + these can vary across platform for the same pins. Hence select > + the platform schematics name for this channel. > + > + qcom,decimation: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: | > + This parameter is used to decrease ADC sampling rate. > + Quicker measurements can be made by reducing decimation ratio. > + - For compatible property "qcom,spmi-vadc", valid values are > + 512, 1024, 2048, 4096. If property is not found, default value > + of 512 will be used. > + - For compatible property "qcom,spmi-adc5", valid values are 250, 420 > + and 840. If property is not found, default value of 840 is used. > + - For compatible property "qcom,spmi-adc-rev2", valid values are 256, > + 512 and 1024. If property is not present, default value is 1024. > + > + qcom,pre-scaling: > + description: | > + Used for scaling the channel input signal before the signal is > + fed to VADC. The configuration for this node is to know the > + pre-determined ratio and use it for post scaling. It is a pair of > + integers, denoting the numerator and denominator of the fraction by which > + input signal is multiplied. For example, <1 3> indicates the signal is scaled > + down to 1/3 of its value before ADC measurement. Select one from > + the following options. > + <1 1>, <1 3>, <1 4>, <1 6>, <1 20>, <1 8>, <10 81>, <1 10> > + If property is not found default value depending on chip will be used. > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint32-array > + oneOf: > + - items: > + - const: 1 > + - enum: [ 1, 3, 4, 6, 20, 8, 10 ] > + > + - items: > + - const: 10 > + - const: 81 > + > + qcom,ratiometric: > + description: | > + Channel calibration type. > + - For compatible property "qcom,spmi-vadc", if this property is > + specified VADC will use the VDD reference (1.8V) and GND for > + channel calibration. If property is not found, channel will be > + calibrated with 0.625V and 1.25V reference channels, also > + known as absolute calibration. > + - For compatible property "qcom,spmi-adc5" and "qcom,spmi-adc-rev2", > + if this property is specified VADC will use the VDD reference (1.875V) > + and GND for channel calibration. If property is not found, channel > + will be calibrated with 0V and 1.25V reference channels, also known > + as absolute calibration. > + type: boolean > + > + qcom,hw-settle-time: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: | > + Time between AMUX getting configured and the ADC starting > + conversion. The 'hw_settle_time' is an index used from valid values > + and programmed in hardware to achieve the hardware settling delay. > + - For compatible property "qcom,spmi-vadc" and "qcom,spmi-adc-rev2", > + Delay = 100us * (hw_settle_time) for hw_settle_time < 11, > + and 2ms * (hw_settle_time - 10) otherwise. > + Valid values are: 0, 100, 200, 300, 400, 500, 600, 700, 800, > + 900 us and 1, 2, 4, 6, 8, 10 ms. > + If property is not found, channel will use 0us. > + - For compatible property "qcom,spmi-adc5", delay = 15us for > + value 0, 100us * (value) for values < 11, > + and 2ms * (value - 10) otherwise. > + Valid values are: 15, 100, 200, 300, 400, 500, 600, 700, 800, > + 900 us and 1, 2, 4, 6, 8, 10 ms > + Certain controller digital versions have valid values of > + 15, 100, 200, 300, 400, 500, 600, 700, 1, 2, 4, 8, 16, 32, 64, 128 ms > + If property is not found, channel will use 15us. > + > + qcom,avg-samples: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: | > + Number of samples to be used for measurement. > + Averaging provides the option to obtain a single measurement > + from the ADC that is an average of multiple samples. The value > + selected is 2^(value). > + - For compatible property "qcom,spmi-vadc", valid values > + are: 1, 2, 4, 8, 16, 32, 64, 128, 256, 512 > + If property is not found, 1 sample will be used. > + > + required: > + - reg > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + const: qcom,spmi-vadc > + > + then: > + patternProperties: > + "^.*@[0-9a-fx]+$": > + minItems: 4 > + properties: > + qcom,decimation: > + items: > + enum: [ 512, 1024, 2048, 4096 ] > + default: 512 > + > + qcom,hw-settle-time: > + items: > + enum: [ 0, 100, 200, 300, 400, 500, 600, 700, 800, 900, 1, 2, > + 4, 6, 8, 10 ] > + default: 0 > + > + qcom,avg-samples: > + items: > + enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512 ] > + default: 1 > + > + - if: > + properties: > + compatible: > + contains: > + const: qcom,spmi-adc-rev2 > + > + then: > + patternProperties: > + "^.*@[0-9a-fx]+$": > + properties: > + qcom,decimation: > + items: > + enum: [ 256, 512, 1024 ] > + default: 1024 > + > + qcom,hw-settle-time: > + items: > + enum: [ 0, 100, 200, 300, 400, 500, 600, 700, 800, 900, 1, 2, > + 4, 6, 8, 10 ] > + default: 0 > + > + qcom,avg-samples: > + items: > + enum: [ 1, 2, 4, 8, 16 ] > + default: 1 > + > + - if: > + properties: > + compatible: > + contains: > + const: qcom,spmi-adc5 > + > + then: > + patternProperties: > + "^.*@[0-9a-fx]+$": > + properties: > + qcom,decimation: > + items: > + enum: [ 250, 420, 840 ] > + default: 840 > + > + qcom,hw-settle-time: > + items: > + enum: [ 15, 100, 200, 300, 400, 500, 600, 700, 800, 900, 1, 2, > + 4, 6, 8, 10, 16, 32, 64, 128 ] > + default: 15 > + > + qcom,avg-samples: > + items: > + enum: [ 1, 2, 4, 8, 16 ] > + default: 1 > + > +examples: > + - | > + spmi_bus { > + #address-cells = <1>; > + #size-cells = <0>; > + /* VADC node */ > + pmic_vadc: adc@3100 { > + compatible = "qcom,spmi-vadc"; > + reg = <0x3100>; > + interrupts = <0x0 0x31 0x0 0x1>; > + #address-cells = <1>; > + #size-cells = <0>; > + #io-channel-cells = <1>; > + io-channel-ranges; > + > + /* Channel node */ > + adc-chan@0x39 { > + reg = <0x39>; > + qcom,decimation = <512>; > + qcom,ratiometric; > + qcom,hw-settle-time = <200>; > + qcom,avg-samples = <1>; > + qcom,pre-scaling = <1 3>; > + }; > + > + adc-chan@0x9 { > + reg = <0x9>; > + }; > + > + adc-chan@0xa { > + reg = <0xa>; > + }; > + > + adc-chan@0xe { > + reg = <0xe>; > + }; > + > + adc-chan@0xf { > + reg = <0xf>; > + }; > + }; > + }; ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH V2 1/3] iio: adc: Convert the QCOM SPMI ADC bindings to .yaml format 2020-04-18 16:22 ` Jonathan Cameron @ 2020-04-27 12:53 ` Jishnu Prakash 0 siblings, 0 replies; 15+ messages in thread From: Jishnu Prakash @ 2020-04-27 12:53 UTC (permalink / raw) To: Jonathan Cameron Cc: agross, bjorn.andersson, devicetree, linux-kernel, mka, linus.walleij, Jonathan.Cameron, smohanad, kgunda, aghayal, Hartmut Knaack, Lars-Peter Clausen, Peter Meerwald-Stadler, Rob Herring, Mark Rutland, linux-iio, linux-arm-msm, linux-arm-msm-owner Hi Jonathan On 4/18/2020 9:52 PM, Jonathan Cameron wrote: > On Wed, 15 Apr 2020 14:47:44 +0530 > Jishnu Prakash <jprakash@codeaurora.org> wrote: > >> Convert the adc bindings from .txt to .yaml format. >> > I read patch 2 before this one for some reason but same question applies here > Given we are now enforcing a lot of the values explicitly are we better > off dropping the text description of that. It looks to me like a potential > place to get out of sync given the information is a bit further down. I'll remove the redundant parts of the descriptions in the next post. ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH V2 2/3] iio: adc: Add PMIC7 ADC bindings 2020-04-15 9:17 [PATCH V2 0/3] iio: adc: Add support for QCOM SPMI PMIC7 ADC Jishnu Prakash 2020-04-15 9:17 ` [PATCH V2 1/3] iio: adc: Convert the QCOM SPMI ADC bindings to .yaml format Jishnu Prakash @ 2020-04-15 9:17 ` Jishnu Prakash 2020-04-18 16:18 ` Jonathan Cameron 2020-04-20 22:02 ` Rob Herring 2020-04-15 9:17 ` [PATCH V2 3/3] iio: adc: Add support for PMIC7 ADC Jishnu Prakash 2 siblings, 2 replies; 15+ messages in thread From: Jishnu Prakash @ 2020-04-15 9:17 UTC (permalink / raw) To: agross, bjorn.andersson, devicetree, linux-kernel, mka, linus.walleij, Jonathan.Cameron, smohanad, kgunda, aghayal, Jonathan Cameron, Hartmut Knaack, Lars-Peter Clausen, Peter Meerwald-Stadler, Rob Herring, Mark Rutland, Jishnu Prakash, linux-iio, linux-arm-msm Cc: linux-arm-msm-owner Add documentation for PMIC7 ADC peripheral. For the PMIC7-type PMICs, ADC peripheral is present in HW for the following PMICs: PMK8350, PM8350, PM8350b, PMR735a and PMR735b. Of these, only the ADC peripheral on PMK8350 is exposed directly to SW. If SW needs to communicate with ADCs on other PMICs, it specifies the PMIC to PMK8350 through the newly added SID register and communication between PMK8350 ADC and other PMIC ADCs is carried out through PBS(Programmable Boot Sequence) at the firmware level. In addition, add definitions for ADC channels and virtual channel definitions (combination of ADC channel number and PMIC SID number) per PMIC, to be used by ADC clients for PMIC7. Signed-off-by: Jishnu Prakash <jprakash@codeaurora.org> --- .../bindings/iio/adc/qcom,spmi-vadc.yaml | 52 +++++++++++-- include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h | 67 ++++++++++++++++ include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h | 88 ++++++++++++++++++++++ include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h | 46 +++++++++++ include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h | 28 +++++++ include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h | 28 +++++++ include/dt-bindings/iio/qcom,spmi-vadc.h | 78 ++++++++++++++++++- 7 files changed, 380 insertions(+), 7 deletions(-) create mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h create mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h create mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h create mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h create mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml index 8273981..62aa311 100644 --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml @@ -13,7 +13,7 @@ maintainers: description: | SPMI PMIC voltage ADC (VADC) provides interface to clients to read voltage. The VADC is a 15-bit sigma-delta ADC. - SPMI PMIC5 voltage ADC (ADC) provides interface to clients to read + SPMI PMIC5/PMIC7 voltage ADC (ADC) provides interface to clients to read voltage. The VADC is a 16-bit sigma-delta ADC. properties: @@ -28,6 +28,7 @@ properties: - qcom,spmi-vadc - qcom,spmi-adc5 - qcom,spmi-adc-rev2 + - qcom,spmi-adc7 reg: description: VADC base address in the SPMI PMIC register map @@ -70,6 +71,8 @@ patternProperties: description: | ADC channel number. See include/dt-bindings/iio/qcom,spmi-vadc.h + For PMIC7 ADC, the channel numbers are specified separately per PMIC + in the PMIC-specific files in include/dt-bindings/iio/. label: $ref: /schemas/types.yaml#/definitions/string @@ -89,6 +92,8 @@ patternProperties: of 512 will be used. - For compatible property "qcom,spmi-adc5", valid values are 250, 420 and 840. If property is not found, default value of 840 is used. + - For compatible property "qcom,spmi-adc7", valid values are 85, 340 + and 1360. If property is not found, default value of 1360 is used. - For compatible property "qcom,spmi-adc-rev2", valid values are 256, 512 and 1024. If property is not present, default value is 1024. @@ -122,11 +127,11 @@ patternProperties: channel calibration. If property is not found, channel will be calibrated with 0.625V and 1.25V reference channels, also known as absolute calibration. - - For compatible property "qcom,spmi-adc5" and "qcom,spmi-adc-rev2", - if this property is specified VADC will use the VDD reference (1.875V) - and GND for channel calibration. If property is not found, channel - will be calibrated with 0V and 1.25V reference channels, also known - as absolute calibration. + - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc7" and + "qcom,spmi-adc-rev2", if this property is specified VADC will use + the VDD reference (1.875V) and GND for channel calibration. If + property is not found, channel will be calibrated with 0V and 1.25V + reference channels, also known as absolute calibration. type: boolean qcom,hw-settle-time: @@ -149,6 +154,12 @@ patternProperties: Certain controller digital versions have valid values of 15, 100, 200, 300, 400, 500, 600, 700, 1, 2, 4, 8, 16, 32, 64, 128 ms If property is not found, channel will use 15us. + - For compatible property "qcom,spmi-adc7", delay = 15us for + value 0, 100us * (value) for values < 8, 1ms for value 8 + and 2ms * (value - 8) otherwise. + Valid values are: 15, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, + 4000, 8000, 16000, 32000, 64000, 128000 us. + If property is not found, channel will use 15us. qcom,avg-samples: $ref: /schemas/types.yaml#/definitions/uint32 @@ -160,6 +171,9 @@ patternProperties: - For compatible property "qcom,spmi-vadc", valid values are: 1, 2, 4, 8, 16, 32, 64, 128, 256, 512 If property is not found, 1 sample will be used. + - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc7" + and "qcom,spmi-adc-rev2", valid values are: 1, 2, 4, 8, 16. + If property is not found, 1 sample will be used. required: - reg @@ -244,6 +258,32 @@ allOf: enum: [ 1, 2, 4, 8, 16 ] default: 1 + - if: + properties: + compatible: + contains: + const: qcom,spmi-adc7 + + then: + patternProperties: + "^.*@[0-9a-fx]+$": + properties: + qcom,decimation: + items: + enum: [ 85, 340, 1360 ] + default: 1360 + + qcom,hw-settle-time: + items: + enum: [ 15, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, 4000, + 8000, 16000, 32000, 64000, 128000 ] + default: 15 + + qcom,avg-samples: + items: + enum: [ 1, 2, 4, 8, 16 ] + default: 1 + examples: - | spmi_bus { diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h b/include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h new file mode 100644 index 0000000..9426f27 --- /dev/null +++ b/include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H + +#ifndef PM8350_SID +#define PM8350_SID 1 +#endif + +/* ADC channels for PM8350_ADC for PMIC7 */ +#define PM8350_ADC7_REF_GND (PM8350_SID << 8 | 0x0) +#define PM8350_ADC7_1P25VREF (PM8350_SID << 8 | 0x01) +#define PM8350_ADC7_VREF_VADC (PM8350_SID << 8 | 0x02) +#define PM8350_ADC7_DIE_TEMP (PM8350_SID << 8 | 0x03) + +#define PM8350_ADC7_AMUX_THM1 (PM8350_SID << 8 | 0x04) +#define PM8350_ADC7_AMUX_THM2 (PM8350_SID << 8 | 0x05) +#define PM8350_ADC7_AMUX_THM3 (PM8350_SID << 8 | 0x06) +#define PM8350_ADC7_AMUX_THM4 (PM8350_SID << 8 | 0x07) +#define PM8350_ADC7_AMUX_THM5 (PM8350_SID << 8 | 0x08) +#define PM8350_ADC7_GPIO1 (PM8350_SID << 8 | 0x0a) +#define PM8350_ADC7_GPIO2 (PM8350_SID << 8 | 0x0b) +#define PM8350_ADC7_GPIO3 (PM8350_SID << 8 | 0x0c) +#define PM8350_ADC7_GPIO4 (PM8350_SID << 8 | 0x0d) + +/* 30k pull-up1 */ +#define PM8350_ADC7_AMUX_THM1_30K_PU (PM8350_SID << 8 | 0x24) +#define PM8350_ADC7_AMUX_THM2_30K_PU (PM8350_SID << 8 | 0x25) +#define PM8350_ADC7_AMUX_THM3_30K_PU (PM8350_SID << 8 | 0x26) +#define PM8350_ADC7_AMUX_THM4_30K_PU (PM8350_SID << 8 | 0x27) +#define PM8350_ADC7_AMUX_THM5_30K_PU (PM8350_SID << 8 | 0x28) +#define PM8350_ADC7_GPIO1_30K_PU (PM8350_SID << 8 | 0x2a) +#define PM8350_ADC7_GPIO2_30K_PU (PM8350_SID << 8 | 0x2b) +#define PM8350_ADC7_GPIO3_30K_PU (PM8350_SID << 8 | 0x2c) +#define PM8350_ADC7_GPIO4_30K_PU (PM8350_SID << 8 | 0x2d) + +/* 100k pull-up2 */ +#define PM8350_ADC7_AMUX_THM1_100K_PU (PM8350_SID << 8 | 0x44) +#define PM8350_ADC7_AMUX_THM2_100K_PU (PM8350_SID << 8 | 0x45) +#define PM8350_ADC7_AMUX_THM3_100K_PU (PM8350_SID << 8 | 0x46) +#define PM8350_ADC7_AMUX_THM4_100K_PU (PM8350_SID << 8 | 0x47) +#define PM8350_ADC7_AMUX_THM5_100K_PU (PM8350_SID << 8 | 0x48) +#define PM8350_ADC7_GPIO1_100K_PU (PM8350_SID << 8 | 0x4a) +#define PM8350_ADC7_GPIO2_100K_PU (PM8350_SID << 8 | 0x4b) +#define PM8350_ADC7_GPIO3_100K_PU (PM8350_SID << 8 | 0x4c) +#define PM8350_ADC7_GPIO4_100K_PU (PM8350_SID << 8 | 0x4d) + +/* 400k pull-up3 */ +#define PM8350_ADC7_AMUX_THM1_400K_PU (PM8350_SID << 8 | 0x64) +#define PM8350_ADC7_AMUX_THM2_400K_PU (PM8350_SID << 8 | 0x65) +#define PM8350_ADC7_AMUX_THM3_400K_PU (PM8350_SID << 8 | 0x66) +#define PM8350_ADC7_AMUX_THM4_400K_PU (PM8350_SID << 8 | 0x67) +#define PM8350_ADC7_AMUX_THM5_400K_PU (PM8350_SID << 8 | 0x68) +#define PM8350_ADC7_GPIO1_400K_PU (PM8350_SID << 8 | 0x6a) +#define PM8350_ADC7_GPIO2_400K_PU (PM8350_SID << 8 | 0x6b) +#define PM8350_ADC7_GPIO3_400K_PU (PM8350_SID << 8 | 0x6c) +#define PM8350_ADC7_GPIO4_400K_PU (PM8350_SID << 8 | 0x6d) + +/* 1/3 Divider */ +#define PM8350_ADC7_GPIO4_DIV3 (PM8350_SID << 8 | 0x8d) + +#define PM8350_ADC7_VPH_PWR (PM8350_SID << 8 | 0x8e) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h b/include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h new file mode 100644 index 0000000..dc2497c --- /dev/null +++ b/include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H + +#ifndef PM8350B_SID +#define PM8350B_SID 3 +#endif + +/* ADC channels for PM8350B_ADC for PMIC7 */ +#define PM8350B_ADC7_REF_GND (PM8350B_SID << 8 | 0x0) +#define PM8350B_ADC7_1P25VREF (PM8350B_SID << 8 | 0x01) +#define PM8350B_ADC7_VREF_VADC (PM8350B_SID << 8 | 0x02) +#define PM8350B_ADC7_DIE_TEMP (PM8350B_SID << 8 | 0x03) + +#define PM8350B_ADC7_AMUX_THM1 (PM8350B_SID << 8 | 0x04) +#define PM8350B_ADC7_AMUX_THM2 (PM8350B_SID << 8 | 0x05) +#define PM8350B_ADC7_AMUX_THM3 (PM8350B_SID << 8 | 0x06) +#define PM8350B_ADC7_AMUX_THM4 (PM8350B_SID << 8 | 0x07) +#define PM8350B_ADC7_AMUX_THM5 (PM8350B_SID << 8 | 0x08) +#define PM8350B_ADC7_AMUX_THM6 (PM8350B_SID << 8 | 0x09) +#define PM8350B_ADC7_GPIO1 (PM8350B_SID << 8 | 0x0a) +#define PM8350B_ADC7_GPIO2 (PM8350B_SID << 8 | 0x0b) +#define PM8350B_ADC7_GPIO3 (PM8350B_SID << 8 | 0x0c) +#define PM8350B_ADC7_GPIO4 (PM8350B_SID << 8 | 0x0d) + +#define PM8350B_ADC7_CHG_TEMP (PM8350B_SID << 8 | 0x10) +#define PM8350B_ADC7_USB_IN_V_16 (PM8350B_SID << 8 | 0x11) +#define PM8350B_ADC7_VDC_16 (PM8350B_SID << 8 | 0x12) +#define PM8350B_ADC7_CC1_ID (PM8350B_SID << 8 | 0x13) +#define PM8350B_ADC7_VREF_BAT_THERM (PM8350B_SID << 8 | 0x15) +#define PM8350B_ADC7_IIN_FB (PM8350B_SID << 8 | 0x17) + +/* 30k pull-up1 */ +#define PM8350B_ADC7_AMUX_THM1_30K_PU (PM8350B_SID << 8 | 0x24) +#define PM8350B_ADC7_AMUX_THM2_30K_PU (PM8350B_SID << 8 | 0x25) +#define PM8350B_ADC7_AMUX_THM3_30K_PU (PM8350B_SID << 8 | 0x26) +#define PM8350B_ADC7_AMUX_THM4_30K_PU (PM8350B_SID << 8 | 0x27) +#define PM8350B_ADC7_AMUX_THM5_30K_PU (PM8350B_SID << 8 | 0x28) +#define PM8350B_ADC7_AMUX_THM6_30K_PU (PM8350B_SID << 8 | 0x29) +#define PM8350B_ADC7_GPIO1_30K_PU (PM8350B_SID << 8 | 0x2a) +#define PM8350B_ADC7_GPIO2_30K_PU (PM8350B_SID << 8 | 0x2b) +#define PM8350B_ADC7_GPIO3_30K_PU (PM8350B_SID << 8 | 0x2c) +#define PM8350B_ADC7_GPIO4_30K_PU (PM8350B_SID << 8 | 0x2d) +#define PM8350B_ADC7_CC1_ID_30K_PU (PM8350B_SID << 8 | 0x33) + +/* 100k pull-up2 */ +#define PM8350B_ADC7_AMUX_THM1_100K_PU (PM8350B_SID << 8 | 0x44) +#define PM8350B_ADC7_AMUX_THM2_100K_PU (PM8350B_SID << 8 | 0x45) +#define PM8350B_ADC7_AMUX_THM3_100K_PU (PM8350B_SID << 8 | 0x46) +#define PM8350B_ADC7_AMUX_THM4_100K_PU (PM8350B_SID << 8 | 0x47) +#define PM8350B_ADC7_AMUX_THM5_100K_PU (PM8350B_SID << 8 | 0x48) +#define PM8350B_ADC7_AMUX_THM6_100K_PU (PM8350B_SID << 8 | 0x49) +#define PM8350B_ADC7_GPIO1_100K_PU (PM8350B_SID << 8 | 0x4a) +#define PM8350B_ADC7_GPIO2_100K_PU (PM8350B_SID << 8 | 0x4b) +#define PM8350B_ADC7_GPIO3_100K_PU (PM8350B_SID << 8 | 0x4c) +#define PM8350B_ADC7_GPIO4_100K_PU (PM8350B_SID << 8 | 0x4d) +#define PM8350B_ADC7_CC1_ID_100K_PU (PM8350B_SID << 8 | 0x53) + +/* 400k pull-up3 */ +#define PM8350B_ADC7_AMUX_THM1_400K_PU (PM8350B_SID << 8 | 0x64) +#define PM8350B_ADC7_AMUX_THM2_400K_PU (PM8350B_SID << 8 | 0x65) +#define PM8350B_ADC7_AMUX_THM3_400K_PU (PM8350B_SID << 8 | 0x66) +#define PM8350B_ADC7_AMUX_THM4_400K_PU (PM8350B_SID << 8 | 0x67) +#define PM8350B_ADC7_AMUX_THM5_400K_PU (PM8350B_SID << 8 | 0x68) +#define PM8350B_ADC7_AMUX_THM6_400K_PU (PM8350B_SID << 8 | 0x69) +#define PM8350B_ADC7_GPIO1_400K_PU (PM8350B_SID << 8 | 0x6a) +#define PM8350B_ADC7_GPIO2_400K_PU (PM8350B_SID << 8 | 0x6b) +#define PM8350B_ADC7_GPIO3_400K_PU (PM8350B_SID << 8 | 0x6c) +#define PM8350B_ADC7_GPIO4_400K_PU (PM8350B_SID << 8 | 0x6d) +#define PM8350B_ADC7_CC1_ID_400K_PU (PM8350B_SID << 8 | 0x73) + +/* 1/3 Divider */ +#define PM8350B_ADC7_GPIO1_DIV3 (PM8350B_SID << 8 | 0x8a) +#define PM8350B_ADC7_GPIO2_DIV3 (PM8350B_SID << 8 | 0x8b) +#define PM8350B_ADC7_GPIO3_DIV3 (PM8350B_SID << 8 | 0x8c) +#define PM8350B_ADC7_GPIO4_DIV3 (PM8350B_SID << 8 | 0x8d) + +#define PM8350B_ADC7_VPH_PWR (PM8350B_SID << 8 | 0x8e) +#define PM8350B_ADC7_VBAT_SNS (PM8350B_SID << 8 | 0x8f) + +#define PM8350B_ADC7_SBUx (PM8350B_SID << 8 | 0x94) +#define PM8350B_ADC7_VBAT_2S_MID (PM8350B_SID << 8 | 0x96) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h b/include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h new file mode 100644 index 0000000..6c29687 --- /dev/null +++ b/include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H + +#ifndef PMK8350_SID +#define PMK8350_SID 0 +#endif + +/* ADC channels for PMK8350_ADC for PMIC7 */ +#define PMK8350_ADC7_REF_GND (PMK8350_SID << 8 | 0x0) +#define PMK8350_ADC7_1P25VREF (PMK8350_SID << 8 | 0x01) +#define PMK8350_ADC7_VREF_VADC (PMK8350_SID << 8 | 0x02) +#define PMK8350_ADC7_DIE_TEMP (PMK8350_SID << 8 | 0x03) + +#define PMK8350_ADC7_AMUX_THM1 (PMK8350_SID << 8 | 0x04) +#define PMK8350_ADC7_AMUX_THM2 (PMK8350_SID << 8 | 0x05) +#define PMK8350_ADC7_AMUX_THM3 (PMK8350_SID << 8 | 0x06) +#define PMK8350_ADC7_AMUX_THM4 (PMK8350_SID << 8 | 0x07) +#define PMK8350_ADC7_AMUX_THM5 (PMK8350_SID << 8 | 0x08) + +/* 30k pull-up1 */ +#define PMK8350_ADC7_AMUX_THM1_30K_PU (PMK8350_SID << 8 | 0x24) +#define PMK8350_ADC7_AMUX_THM2_30K_PU (PMK8350_SID << 8 | 0x25) +#define PMK8350_ADC7_AMUX_THM3_30K_PU (PMK8350_SID << 8 | 0x26) +#define PMK8350_ADC7_AMUX_THM4_30K_PU (PMK8350_SID << 8 | 0x27) +#define PMK8350_ADC7_AMUX_THM5_30K_PU (PMK8350_SID << 8 | 0x28) + +/* 100k pull-up2 */ +#define PMK8350_ADC7_AMUX_THM1_100K_PU (PMK8350_SID << 8 | 0x44) +#define PMK8350_ADC7_AMUX_THM2_100K_PU (PMK8350_SID << 8 | 0x45) +#define PMK8350_ADC7_AMUX_THM3_100K_PU (PMK8350_SID << 8 | 0x46) +#define PMK8350_ADC7_AMUX_THM4_100K_PU (PMK8350_SID << 8 | 0x47) +#define PMK8350_ADC7_AMUX_THM5_100K_PU (PMK8350_SID << 8 | 0x48) + +/* 400k pull-up3 */ +#define PMK8350_ADC7_AMUX_THM1_400K_PU (PMK8350_SID << 8 | 0x64) +#define PMK8350_ADC7_AMUX_THM2_400K_PU (PMK8350_SID << 8 | 0x65) +#define PMK8350_ADC7_AMUX_THM3_400K_PU (PMK8350_SID << 8 | 0x66) +#define PMK8350_ADC7_AMUX_THM4_400K_PU (PMK8350_SID << 8 | 0x67) +#define PMK8350_ADC7_AMUX_THM5_400K_PU (PMK8350_SID << 8 | 0x68) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h b/include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h new file mode 100644 index 0000000..d6df1b1 --- /dev/null +++ b/include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H + +#ifndef PMR735A_SID +#define PMR735A_SID 4 +#endif + +/* ADC channels for PMR735A_ADC for PMIC7 */ +#define PMR735A_ADC7_REF_GND (PMR735A_SID << 8 | 0x0) +#define PMR735A_ADC7_1P25VREF (PMR735A_SID << 8 | 0x01) +#define PMR735A_ADC7_VREF_VADC (PMR735A_SID << 8 | 0x02) +#define PMR735A_ADC7_DIE_TEMP (PMR735A_SID << 8 | 0x03) + +#define PMR735A_ADC7_GPIO1 (PMR735A_SID << 8 | 0x0a) +#define PMR735A_ADC7_GPIO2 (PMR735A_SID << 8 | 0x0b) +#define PMR735A_ADC7_GPIO3 (PMR735A_SID << 8 | 0x0c) + +/* 100k pull-up2 */ +#define PMR735A_ADC7_GPIO1_100K_PU (PMR735A_SID << 8 | 0x4a) +#define PMR735A_ADC7_GPIO2_100K_PU (PMR735A_SID << 8 | 0x4b) +#define PMR735A_ADC7_GPIO3_100K_PU (PMR735A_SID << 8 | 0x4c) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h b/include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h new file mode 100644 index 0000000..8da0e7d --- /dev/null +++ b/include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H + +#ifndef PMR735B_SID +#define PMR735B_SID 5 +#endif + +/* ADC channels for PMR735B_ADC for PMIC7 */ +#define PMR735B_ADC7_REF_GND (PMR735B_SID << 8 | 0x0) +#define PMR735B_ADC7_1P25VREF (PMR735B_SID << 8 | 0x01) +#define PMR735B_ADC7_VREF_VADC (PMR735B_SID << 8 | 0x02) +#define PMR735B_ADC7_DIE_TEMP (PMR735B_SID << 8 | 0x03) + +#define PMR735B_ADC7_GPIO1 (PMR735B_SID << 8 | 0x0a) +#define PMR735B_ADC7_GPIO2 (PMR735B_SID << 8 | 0x0b) +#define PMR735B_ADC7_GPIO3 (PMR735B_SID << 8 | 0x0c) + +/* 100k pull-up2 */ +#define PMR735B_ADC7_GPIO1_100K_PU (PMR735B_SID << 8 | 0x4a) +#define PMR735B_ADC7_GPIO2_100K_PU (PMR735B_SID << 8 | 0x4b) +#define PMR735B_ADC7_GPIO3_100K_PU (PMR735B_SID << 8 | 0x4c) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-vadc.h b/include/dt-bindings/iio/qcom,spmi-vadc.h index 61d556d..08adfe2 100644 --- a/include/dt-bindings/iio/qcom,spmi-vadc.h +++ b/include/dt-bindings/iio/qcom,spmi-vadc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2012-2014,2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved. */ #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H @@ -221,4 +221,80 @@ #define ADC5_MAX_CHANNEL 0xc0 +/* ADC channels for ADC for PMIC7 */ + +#define ADC7_REF_GND 0x00 +#define ADC7_1P25VREF 0x01 +#define ADC7_VREF_VADC 0x02 +#define ADC7_DIE_TEMP 0x03 + +#define ADC7_AMUX_THM1 0x04 +#define ADC7_AMUX_THM2 0x05 +#define ADC7_AMUX_THM3 0x06 +#define ADC7_AMUX_THM4 0x07 +#define ADC7_AMUX_THM5 0x08 +#define ADC7_AMUX_THM6 0x09 +#define ADC7_GPIO1 0x0a +#define ADC7_GPIO2 0x0b +#define ADC7_GPIO3 0x0c +#define ADC7_GPIO4 0x0d + +#define ADC7_CHG_TEMP 0x10 +#define ADC7_USB_IN_V_16 0x11 +#define ADC7_VDC_16 0x12 +#define ADC7_CC1_ID 0x13 +#define ADC7_VREF_BAT_THERM 0x15 +#define ADC7_IIN_FB 0x17 + +/* 30k pull-up1 */ +#define ADC7_AMUX_THM1_30K_PU 0x24 +#define ADC7_AMUX_THM2_30K_PU 0x25 +#define ADC7_AMUX_THM3_30K_PU 0x26 +#define ADC7_AMUX_THM4_30K_PU 0x27 +#define ADC7_AMUX_THM5_30K_PU 0x28 +#define ADC7_AMUX_THM6_30K_PU 0x29 +#define ADC7_GPIO1_30K_PU 0x2a +#define ADC7_GPIO2_30K_PU 0x2b +#define ADC7_GPIO3_30K_PU 0x2c +#define ADC7_GPIO4_30K_PU 0x2d +#define ADC7_CC1_ID_30K_PU 0x33 + +/* 100k pull-up2 */ +#define ADC7_AMUX_THM1_100K_PU 0x44 +#define ADC7_AMUX_THM2_100K_PU 0x45 +#define ADC7_AMUX_THM3_100K_PU 0x46 +#define ADC7_AMUX_THM4_100K_PU 0x47 +#define ADC7_AMUX_THM5_100K_PU 0x48 +#define ADC7_AMUX_THM6_100K_PU 0x49 +#define ADC7_GPIO1_100K_PU 0x4a +#define ADC7_GPIO2_100K_PU 0x4b +#define ADC7_GPIO3_100K_PU 0x4c +#define ADC7_GPIO4_100K_PU 0x4d +#define ADC7_CC1_ID_100K_PU 0x53 + +/* 400k pull-up3 */ +#define ADC7_AMUX_THM1_400K_PU 0x64 +#define ADC7_AMUX_THM2_400K_PU 0x65 +#define ADC7_AMUX_THM3_400K_PU 0x66 +#define ADC7_AMUX_THM4_400K_PU 0x67 +#define ADC7_AMUX_THM5_400K_PU 0x68 +#define ADC7_AMUX_THM6_400K_PU 0x69 +#define ADC7_GPIO1_400K_PU 0x6a +#define ADC7_GPIO2_400K_PU 0x6b +#define ADC7_GPIO3_400K_PU 0x6c +#define ADC7_GPIO4_400K_PU 0x6d +#define ADC7_CC1_ID_400K_PU 0x73 + +/* 1/3 Divider */ +#define ADC7_GPIO1_DIV3 0x8a +#define ADC7_GPIO2_DIV3 0x8b +#define ADC7_GPIO3_DIV3 0x8c +#define ADC7_GPIO4_DIV3 0x8d + +#define ADC7_VPH_PWR 0x8e +#define ADC7_VBAT_SNS 0x8f + +#define ADC7_SBUx 0x94 +#define ADC7_VBAT_2S_MID 0x96 + #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */ -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH V2 2/3] iio: adc: Add PMIC7 ADC bindings 2020-04-15 9:17 ` [PATCH V2 2/3] iio: adc: Add PMIC7 ADC bindings Jishnu Prakash @ 2020-04-18 16:18 ` Jonathan Cameron 2020-04-27 12:55 ` Jishnu Prakash 2020-04-20 22:02 ` Rob Herring 1 sibling, 1 reply; 15+ messages in thread From: Jonathan Cameron @ 2020-04-18 16:18 UTC (permalink / raw) To: Jishnu Prakash Cc: agross, bjorn.andersson, devicetree, linux-kernel, mka, linus.walleij, Jonathan.Cameron, smohanad, kgunda, aghayal, Hartmut Knaack, Lars-Peter Clausen, Peter Meerwald-Stadler, Rob Herring, Mark Rutland, linux-iio, linux-arm-msm, linux-arm-msm-owner On Wed, 15 Apr 2020 14:47:45 +0530 Jishnu Prakash <jprakash@codeaurora.org> wrote: > Add documentation for PMIC7 ADC peripheral. > For the PMIC7-type PMICs, ADC peripheral is present in HW for the > following PMICs: PMK8350, PM8350, PM8350b, PMR735a and PMR735b. > Of these, only the ADC peripheral on PMK8350 is exposed directly to SW. > If SW needs to communicate with ADCs on other PMICs, it specifies the > PMIC to PMK8350 through the newly added SID register and communication > between PMK8350 ADC and other PMIC ADCs is carried out through > PBS(Programmable Boot Sequence) at the firmware level. > > In addition, add definitions for ADC channels and virtual channel > definitions (combination of ADC channel number and PMIC SID number) > per PMIC, to be used by ADC clients for PMIC7. > > Signed-off-by: Jishnu Prakash <jprakash@codeaurora.org> > --- > .../bindings/iio/adc/qcom,spmi-vadc.yaml | 52 +++++++++++-- > include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h | 67 ++++++++++++++++ > include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h | 88 ++++++++++++++++++++++ > include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h | 46 +++++++++++ > include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h | 28 +++++++ > include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h | 28 +++++++ > include/dt-bindings/iio/qcom,spmi-vadc.h | 78 ++++++++++++++++++- > 7 files changed, 380 insertions(+), 7 deletions(-) > create mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h > create mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h > create mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h > create mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h > create mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h > > diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml > index 8273981..62aa311 100644 > --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml > +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml > @@ -13,7 +13,7 @@ maintainers: > description: | > SPMI PMIC voltage ADC (VADC) provides interface to clients to read > voltage. The VADC is a 15-bit sigma-delta ADC. > - SPMI PMIC5 voltage ADC (ADC) provides interface to clients to read > + SPMI PMIC5/PMIC7 voltage ADC (ADC) provides interface to clients to read > voltage. The VADC is a 16-bit sigma-delta ADC. > > properties: > @@ -28,6 +28,7 @@ properties: > - qcom,spmi-vadc > - qcom,spmi-adc5 > - qcom,spmi-adc-rev2 > + - qcom,spmi-adc7 > > reg: > description: VADC base address in the SPMI PMIC register map > @@ -70,6 +71,8 @@ patternProperties: > description: | > ADC channel number. > See include/dt-bindings/iio/qcom,spmi-vadc.h > + For PMIC7 ADC, the channel numbers are specified separately per PMIC > + in the PMIC-specific files in include/dt-bindings/iio/. > > label: > $ref: /schemas/types.yaml#/definitions/string > @@ -89,6 +92,8 @@ patternProperties: > of 512 will be used. > - For compatible property "qcom,spmi-adc5", valid values are 250, 420 > and 840. If property is not found, default value of 840 is used. > + - For compatible property "qcom,spmi-adc7", valid values are 85, 340 > + and 1360. If property is not found, default value of 1360 is used. > - For compatible property "qcom,spmi-adc-rev2", valid values are 256, > 512 and 1024. If property is not present, default value is 1024. > > @@ -122,11 +127,11 @@ patternProperties: > channel calibration. If property is not found, channel will be > calibrated with 0.625V and 1.25V reference channels, also > known as absolute calibration. > - - For compatible property "qcom,spmi-adc5" and "qcom,spmi-adc-rev2", > - if this property is specified VADC will use the VDD reference (1.875V) > - and GND for channel calibration. If property is not found, channel > - will be calibrated with 0V and 1.25V reference channels, also known > - as absolute calibration. > + - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc7" and > + "qcom,spmi-adc-rev2", if this property is specified VADC will use > + the VDD reference (1.875V) and GND for channel calibration. If > + property is not found, channel will be calibrated with 0V and 1.25V > + reference channels, also known as absolute calibration. > type: boolean > > qcom,hw-settle-time: > @@ -149,6 +154,12 @@ patternProperties: > Certain controller digital versions have valid values of > 15, 100, 200, 300, 400, 500, 600, 700, 1, 2, 4, 8, 16, 32, 64, 128 ms > If property is not found, channel will use 15us. > + - For compatible property "qcom,spmi-adc7", delay = 15us for > + value 0, 100us * (value) for values < 8, 1ms for value 8 > + and 2ms * (value - 8) otherwise. > + Valid values are: 15, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, > + 4000, 8000, 16000, 32000, 64000, 128000 us. We are enforcing them in the binding. Does it make sense to put them here as well? Just seems like something that will get out of sync to me. > + If property is not found, channel will use 15us. > > qcom,avg-samples: > $ref: /schemas/types.yaml#/definitions/uint32 > @@ -160,6 +171,9 @@ patternProperties: > - For compatible property "qcom,spmi-vadc", valid values > are: 1, 2, 4, 8, 16, 32, 64, 128, 256, 512 > If property is not found, 1 sample will be used. > + - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc7" > + and "qcom,spmi-adc-rev2", valid values are: 1, 2, 4, 8, 16. > + If property is not found, 1 sample will be used. > > required: > - reg > @@ -244,6 +258,32 @@ allOf: > enum: [ 1, 2, 4, 8, 16 ] > default: 1 > > + - if: > + properties: > + compatible: > + contains: > + const: qcom,spmi-adc7 > + > + then: > + patternProperties: > + "^.*@[0-9a-fx]+$": > + properties: > + qcom,decimation: > + items: > + enum: [ 85, 340, 1360 ] > + default: 1360 > + > + qcom,hw-settle-time: > + items: > + enum: [ 15, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, 4000, > + 8000, 16000, 32000, 64000, 128000 ] > + default: 15 > + > + qcom,avg-samples: > + items: > + enum: [ 1, 2, 4, 8, 16 ] > + default: 1 > + > examples: > - | > spmi_bus { > diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h b/include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h > new file mode 100644 > index 0000000..9426f27 > --- /dev/null > +++ b/include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h > @@ -0,0 +1,67 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2020, The Linux Foundation. All rights reserved. > + */ > + > +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H > +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H > + > +#ifndef PM8350_SID > +#define PM8350_SID 1 > +#endif > + > +/* ADC channels for PM8350_ADC for PMIC7 */ > +#define PM8350_ADC7_REF_GND (PM8350_SID << 8 | 0x0) > +#define PM8350_ADC7_1P25VREF (PM8350_SID << 8 | 0x01) > +#define PM8350_ADC7_VREF_VADC (PM8350_SID << 8 | 0x02) > +#define PM8350_ADC7_DIE_TEMP (PM8350_SID << 8 | 0x03) > + > +#define PM8350_ADC7_AMUX_THM1 (PM8350_SID << 8 | 0x04) > +#define PM8350_ADC7_AMUX_THM2 (PM8350_SID << 8 | 0x05) > +#define PM8350_ADC7_AMUX_THM3 (PM8350_SID << 8 | 0x06) > +#define PM8350_ADC7_AMUX_THM4 (PM8350_SID << 8 | 0x07) > +#define PM8350_ADC7_AMUX_THM5 (PM8350_SID << 8 | 0x08) > +#define PM8350_ADC7_GPIO1 (PM8350_SID << 8 | 0x0a) > +#define PM8350_ADC7_GPIO2 (PM8350_SID << 8 | 0x0b) > +#define PM8350_ADC7_GPIO3 (PM8350_SID << 8 | 0x0c) > +#define PM8350_ADC7_GPIO4 (PM8350_SID << 8 | 0x0d) > + > +/* 30k pull-up1 */ > +#define PM8350_ADC7_AMUX_THM1_30K_PU (PM8350_SID << 8 | 0x24) > +#define PM8350_ADC7_AMUX_THM2_30K_PU (PM8350_SID << 8 | 0x25) > +#define PM8350_ADC7_AMUX_THM3_30K_PU (PM8350_SID << 8 | 0x26) > +#define PM8350_ADC7_AMUX_THM4_30K_PU (PM8350_SID << 8 | 0x27) > +#define PM8350_ADC7_AMUX_THM5_30K_PU (PM8350_SID << 8 | 0x28) > +#define PM8350_ADC7_GPIO1_30K_PU (PM8350_SID << 8 | 0x2a) > +#define PM8350_ADC7_GPIO2_30K_PU (PM8350_SID << 8 | 0x2b) > +#define PM8350_ADC7_GPIO3_30K_PU (PM8350_SID << 8 | 0x2c) > +#define PM8350_ADC7_GPIO4_30K_PU (PM8350_SID << 8 | 0x2d) > + > +/* 100k pull-up2 */ > +#define PM8350_ADC7_AMUX_THM1_100K_PU (PM8350_SID << 8 | 0x44) > +#define PM8350_ADC7_AMUX_THM2_100K_PU (PM8350_SID << 8 | 0x45) > +#define PM8350_ADC7_AMUX_THM3_100K_PU (PM8350_SID << 8 | 0x46) > +#define PM8350_ADC7_AMUX_THM4_100K_PU (PM8350_SID << 8 | 0x47) > +#define PM8350_ADC7_AMUX_THM5_100K_PU (PM8350_SID << 8 | 0x48) > +#define PM8350_ADC7_GPIO1_100K_PU (PM8350_SID << 8 | 0x4a) > +#define PM8350_ADC7_GPIO2_100K_PU (PM8350_SID << 8 | 0x4b) > +#define PM8350_ADC7_GPIO3_100K_PU (PM8350_SID << 8 | 0x4c) > +#define PM8350_ADC7_GPIO4_100K_PU (PM8350_SID << 8 | 0x4d) > + > +/* 400k pull-up3 */ > +#define PM8350_ADC7_AMUX_THM1_400K_PU (PM8350_SID << 8 | 0x64) > +#define PM8350_ADC7_AMUX_THM2_400K_PU (PM8350_SID << 8 | 0x65) > +#define PM8350_ADC7_AMUX_THM3_400K_PU (PM8350_SID << 8 | 0x66) > +#define PM8350_ADC7_AMUX_THM4_400K_PU (PM8350_SID << 8 | 0x67) > +#define PM8350_ADC7_AMUX_THM5_400K_PU (PM8350_SID << 8 | 0x68) > +#define PM8350_ADC7_GPIO1_400K_PU (PM8350_SID << 8 | 0x6a) > +#define PM8350_ADC7_GPIO2_400K_PU (PM8350_SID << 8 | 0x6b) > +#define PM8350_ADC7_GPIO3_400K_PU (PM8350_SID << 8 | 0x6c) > +#define PM8350_ADC7_GPIO4_400K_PU (PM8350_SID << 8 | 0x6d) > + > +/* 1/3 Divider */ > +#define PM8350_ADC7_GPIO4_DIV3 (PM8350_SID << 8 | 0x8d) > + > +#define PM8350_ADC7_VPH_PWR (PM8350_SID << 8 | 0x8e) > + > +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H */ > diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h b/include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h > new file mode 100644 > index 0000000..dc2497c > --- /dev/null > +++ b/include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h > @@ -0,0 +1,88 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2020 The Linux Foundation. All rights reserved. > + */ > + > +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H > +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H > + > +#ifndef PM8350B_SID > +#define PM8350B_SID 3 > +#endif > + > +/* ADC channels for PM8350B_ADC for PMIC7 */ > +#define PM8350B_ADC7_REF_GND (PM8350B_SID << 8 | 0x0) > +#define PM8350B_ADC7_1P25VREF (PM8350B_SID << 8 | 0x01) > +#define PM8350B_ADC7_VREF_VADC (PM8350B_SID << 8 | 0x02) > +#define PM8350B_ADC7_DIE_TEMP (PM8350B_SID << 8 | 0x03) > + > +#define PM8350B_ADC7_AMUX_THM1 (PM8350B_SID << 8 | 0x04) > +#define PM8350B_ADC7_AMUX_THM2 (PM8350B_SID << 8 | 0x05) > +#define PM8350B_ADC7_AMUX_THM3 (PM8350B_SID << 8 | 0x06) > +#define PM8350B_ADC7_AMUX_THM4 (PM8350B_SID << 8 | 0x07) > +#define PM8350B_ADC7_AMUX_THM5 (PM8350B_SID << 8 | 0x08) > +#define PM8350B_ADC7_AMUX_THM6 (PM8350B_SID << 8 | 0x09) > +#define PM8350B_ADC7_GPIO1 (PM8350B_SID << 8 | 0x0a) > +#define PM8350B_ADC7_GPIO2 (PM8350B_SID << 8 | 0x0b) > +#define PM8350B_ADC7_GPIO3 (PM8350B_SID << 8 | 0x0c) > +#define PM8350B_ADC7_GPIO4 (PM8350B_SID << 8 | 0x0d) > + > +#define PM8350B_ADC7_CHG_TEMP (PM8350B_SID << 8 | 0x10) > +#define PM8350B_ADC7_USB_IN_V_16 (PM8350B_SID << 8 | 0x11) > +#define PM8350B_ADC7_VDC_16 (PM8350B_SID << 8 | 0x12) > +#define PM8350B_ADC7_CC1_ID (PM8350B_SID << 8 | 0x13) > +#define PM8350B_ADC7_VREF_BAT_THERM (PM8350B_SID << 8 | 0x15) > +#define PM8350B_ADC7_IIN_FB (PM8350B_SID << 8 | 0x17) > + > +/* 30k pull-up1 */ > +#define PM8350B_ADC7_AMUX_THM1_30K_PU (PM8350B_SID << 8 | 0x24) > +#define PM8350B_ADC7_AMUX_THM2_30K_PU (PM8350B_SID << 8 | 0x25) > +#define PM8350B_ADC7_AMUX_THM3_30K_PU (PM8350B_SID << 8 | 0x26) > +#define PM8350B_ADC7_AMUX_THM4_30K_PU (PM8350B_SID << 8 | 0x27) > +#define PM8350B_ADC7_AMUX_THM5_30K_PU (PM8350B_SID << 8 | 0x28) > +#define PM8350B_ADC7_AMUX_THM6_30K_PU (PM8350B_SID << 8 | 0x29) > +#define PM8350B_ADC7_GPIO1_30K_PU (PM8350B_SID << 8 | 0x2a) > +#define PM8350B_ADC7_GPIO2_30K_PU (PM8350B_SID << 8 | 0x2b) > +#define PM8350B_ADC7_GPIO3_30K_PU (PM8350B_SID << 8 | 0x2c) > +#define PM8350B_ADC7_GPIO4_30K_PU (PM8350B_SID << 8 | 0x2d) > +#define PM8350B_ADC7_CC1_ID_30K_PU (PM8350B_SID << 8 | 0x33) > + > +/* 100k pull-up2 */ > +#define PM8350B_ADC7_AMUX_THM1_100K_PU (PM8350B_SID << 8 | 0x44) > +#define PM8350B_ADC7_AMUX_THM2_100K_PU (PM8350B_SID << 8 | 0x45) > +#define PM8350B_ADC7_AMUX_THM3_100K_PU (PM8350B_SID << 8 | 0x46) > +#define PM8350B_ADC7_AMUX_THM4_100K_PU (PM8350B_SID << 8 | 0x47) > +#define PM8350B_ADC7_AMUX_THM5_100K_PU (PM8350B_SID << 8 | 0x48) > +#define PM8350B_ADC7_AMUX_THM6_100K_PU (PM8350B_SID << 8 | 0x49) > +#define PM8350B_ADC7_GPIO1_100K_PU (PM8350B_SID << 8 | 0x4a) > +#define PM8350B_ADC7_GPIO2_100K_PU (PM8350B_SID << 8 | 0x4b) > +#define PM8350B_ADC7_GPIO3_100K_PU (PM8350B_SID << 8 | 0x4c) > +#define PM8350B_ADC7_GPIO4_100K_PU (PM8350B_SID << 8 | 0x4d) > +#define PM8350B_ADC7_CC1_ID_100K_PU (PM8350B_SID << 8 | 0x53) > + > +/* 400k pull-up3 */ > +#define PM8350B_ADC7_AMUX_THM1_400K_PU (PM8350B_SID << 8 | 0x64) > +#define PM8350B_ADC7_AMUX_THM2_400K_PU (PM8350B_SID << 8 | 0x65) > +#define PM8350B_ADC7_AMUX_THM3_400K_PU (PM8350B_SID << 8 | 0x66) > +#define PM8350B_ADC7_AMUX_THM4_400K_PU (PM8350B_SID << 8 | 0x67) > +#define PM8350B_ADC7_AMUX_THM5_400K_PU (PM8350B_SID << 8 | 0x68) > +#define PM8350B_ADC7_AMUX_THM6_400K_PU (PM8350B_SID << 8 | 0x69) > +#define PM8350B_ADC7_GPIO1_400K_PU (PM8350B_SID << 8 | 0x6a) > +#define PM8350B_ADC7_GPIO2_400K_PU (PM8350B_SID << 8 | 0x6b) > +#define PM8350B_ADC7_GPIO3_400K_PU (PM8350B_SID << 8 | 0x6c) > +#define PM8350B_ADC7_GPIO4_400K_PU (PM8350B_SID << 8 | 0x6d) > +#define PM8350B_ADC7_CC1_ID_400K_PU (PM8350B_SID << 8 | 0x73) > + > +/* 1/3 Divider */ > +#define PM8350B_ADC7_GPIO1_DIV3 (PM8350B_SID << 8 | 0x8a) > +#define PM8350B_ADC7_GPIO2_DIV3 (PM8350B_SID << 8 | 0x8b) > +#define PM8350B_ADC7_GPIO3_DIV3 (PM8350B_SID << 8 | 0x8c) > +#define PM8350B_ADC7_GPIO4_DIV3 (PM8350B_SID << 8 | 0x8d) > + > +#define PM8350B_ADC7_VPH_PWR (PM8350B_SID << 8 | 0x8e) > +#define PM8350B_ADC7_VBAT_SNS (PM8350B_SID << 8 | 0x8f) > + > +#define PM8350B_ADC7_SBUx (PM8350B_SID << 8 | 0x94) > +#define PM8350B_ADC7_VBAT_2S_MID (PM8350B_SID << 8 | 0x96) > + > +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H */ > diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h b/include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h > new file mode 100644 > index 0000000..6c29687 > --- /dev/null > +++ b/include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h > @@ -0,0 +1,46 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2020 The Linux Foundation. All rights reserved. > + */ > + > +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H > +#define _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H > + > +#ifndef PMK8350_SID > +#define PMK8350_SID 0 > +#endif > + > +/* ADC channels for PMK8350_ADC for PMIC7 */ > +#define PMK8350_ADC7_REF_GND (PMK8350_SID << 8 | 0x0) > +#define PMK8350_ADC7_1P25VREF (PMK8350_SID << 8 | 0x01) > +#define PMK8350_ADC7_VREF_VADC (PMK8350_SID << 8 | 0x02) > +#define PMK8350_ADC7_DIE_TEMP (PMK8350_SID << 8 | 0x03) > + > +#define PMK8350_ADC7_AMUX_THM1 (PMK8350_SID << 8 | 0x04) > +#define PMK8350_ADC7_AMUX_THM2 (PMK8350_SID << 8 | 0x05) > +#define PMK8350_ADC7_AMUX_THM3 (PMK8350_SID << 8 | 0x06) > +#define PMK8350_ADC7_AMUX_THM4 (PMK8350_SID << 8 | 0x07) > +#define PMK8350_ADC7_AMUX_THM5 (PMK8350_SID << 8 | 0x08) > + > +/* 30k pull-up1 */ > +#define PMK8350_ADC7_AMUX_THM1_30K_PU (PMK8350_SID << 8 | 0x24) > +#define PMK8350_ADC7_AMUX_THM2_30K_PU (PMK8350_SID << 8 | 0x25) > +#define PMK8350_ADC7_AMUX_THM3_30K_PU (PMK8350_SID << 8 | 0x26) > +#define PMK8350_ADC7_AMUX_THM4_30K_PU (PMK8350_SID << 8 | 0x27) > +#define PMK8350_ADC7_AMUX_THM5_30K_PU (PMK8350_SID << 8 | 0x28) > + > +/* 100k pull-up2 */ > +#define PMK8350_ADC7_AMUX_THM1_100K_PU (PMK8350_SID << 8 | 0x44) > +#define PMK8350_ADC7_AMUX_THM2_100K_PU (PMK8350_SID << 8 | 0x45) > +#define PMK8350_ADC7_AMUX_THM3_100K_PU (PMK8350_SID << 8 | 0x46) > +#define PMK8350_ADC7_AMUX_THM4_100K_PU (PMK8350_SID << 8 | 0x47) > +#define PMK8350_ADC7_AMUX_THM5_100K_PU (PMK8350_SID << 8 | 0x48) > + > +/* 400k pull-up3 */ > +#define PMK8350_ADC7_AMUX_THM1_400K_PU (PMK8350_SID << 8 | 0x64) > +#define PMK8350_ADC7_AMUX_THM2_400K_PU (PMK8350_SID << 8 | 0x65) > +#define PMK8350_ADC7_AMUX_THM3_400K_PU (PMK8350_SID << 8 | 0x66) > +#define PMK8350_ADC7_AMUX_THM4_400K_PU (PMK8350_SID << 8 | 0x67) > +#define PMK8350_ADC7_AMUX_THM5_400K_PU (PMK8350_SID << 8 | 0x68) > + > +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H */ > diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h b/include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h > new file mode 100644 > index 0000000..d6df1b1 > --- /dev/null > +++ b/include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h > @@ -0,0 +1,28 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2020 The Linux Foundation. All rights reserved. > + */ > + > +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H > +#define _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H > + > +#ifndef PMR735A_SID > +#define PMR735A_SID 4 > +#endif > + > +/* ADC channels for PMR735A_ADC for PMIC7 */ > +#define PMR735A_ADC7_REF_GND (PMR735A_SID << 8 | 0x0) > +#define PMR735A_ADC7_1P25VREF (PMR735A_SID << 8 | 0x01) > +#define PMR735A_ADC7_VREF_VADC (PMR735A_SID << 8 | 0x02) > +#define PMR735A_ADC7_DIE_TEMP (PMR735A_SID << 8 | 0x03) > + > +#define PMR735A_ADC7_GPIO1 (PMR735A_SID << 8 | 0x0a) > +#define PMR735A_ADC7_GPIO2 (PMR735A_SID << 8 | 0x0b) > +#define PMR735A_ADC7_GPIO3 (PMR735A_SID << 8 | 0x0c) > + > +/* 100k pull-up2 */ > +#define PMR735A_ADC7_GPIO1_100K_PU (PMR735A_SID << 8 | 0x4a) > +#define PMR735A_ADC7_GPIO2_100K_PU (PMR735A_SID << 8 | 0x4b) > +#define PMR735A_ADC7_GPIO3_100K_PU (PMR735A_SID << 8 | 0x4c) > + > +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H */ > diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h b/include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h > new file mode 100644 > index 0000000..8da0e7d > --- /dev/null > +++ b/include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h > @@ -0,0 +1,28 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2020 The Linux Foundation. All rights reserved. > + */ > + > +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H > +#define _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H > + > +#ifndef PMR735B_SID > +#define PMR735B_SID 5 > +#endif > + > +/* ADC channels for PMR735B_ADC for PMIC7 */ > +#define PMR735B_ADC7_REF_GND (PMR735B_SID << 8 | 0x0) > +#define PMR735B_ADC7_1P25VREF (PMR735B_SID << 8 | 0x01) > +#define PMR735B_ADC7_VREF_VADC (PMR735B_SID << 8 | 0x02) > +#define PMR735B_ADC7_DIE_TEMP (PMR735B_SID << 8 | 0x03) > + > +#define PMR735B_ADC7_GPIO1 (PMR735B_SID << 8 | 0x0a) > +#define PMR735B_ADC7_GPIO2 (PMR735B_SID << 8 | 0x0b) > +#define PMR735B_ADC7_GPIO3 (PMR735B_SID << 8 | 0x0c) > + > +/* 100k pull-up2 */ > +#define PMR735B_ADC7_GPIO1_100K_PU (PMR735B_SID << 8 | 0x4a) > +#define PMR735B_ADC7_GPIO2_100K_PU (PMR735B_SID << 8 | 0x4b) > +#define PMR735B_ADC7_GPIO3_100K_PU (PMR735B_SID << 8 | 0x4c) > + > +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H */ > diff --git a/include/dt-bindings/iio/qcom,spmi-vadc.h b/include/dt-bindings/iio/qcom,spmi-vadc.h > index 61d556d..08adfe2 100644 > --- a/include/dt-bindings/iio/qcom,spmi-vadc.h > +++ b/include/dt-bindings/iio/qcom,spmi-vadc.h > @@ -1,6 +1,6 @@ > /* SPDX-License-Identifier: GPL-2.0 */ > /* > - * Copyright (c) 2012-2014,2018 The Linux Foundation. All rights reserved. > + * Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved. > */ > > #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H > @@ -221,4 +221,80 @@ > > #define ADC5_MAX_CHANNEL 0xc0 > > +/* ADC channels for ADC for PMIC7 */ > + > +#define ADC7_REF_GND 0x00 > +#define ADC7_1P25VREF 0x01 > +#define ADC7_VREF_VADC 0x02 > +#define ADC7_DIE_TEMP 0x03 > + > +#define ADC7_AMUX_THM1 0x04 > +#define ADC7_AMUX_THM2 0x05 > +#define ADC7_AMUX_THM3 0x06 > +#define ADC7_AMUX_THM4 0x07 > +#define ADC7_AMUX_THM5 0x08 > +#define ADC7_AMUX_THM6 0x09 > +#define ADC7_GPIO1 0x0a > +#define ADC7_GPIO2 0x0b > +#define ADC7_GPIO3 0x0c > +#define ADC7_GPIO4 0x0d > + > +#define ADC7_CHG_TEMP 0x10 > +#define ADC7_USB_IN_V_16 0x11 > +#define ADC7_VDC_16 0x12 > +#define ADC7_CC1_ID 0x13 > +#define ADC7_VREF_BAT_THERM 0x15 > +#define ADC7_IIN_FB 0x17 > + > +/* 30k pull-up1 */ > +#define ADC7_AMUX_THM1_30K_PU 0x24 > +#define ADC7_AMUX_THM2_30K_PU 0x25 > +#define ADC7_AMUX_THM3_30K_PU 0x26 > +#define ADC7_AMUX_THM4_30K_PU 0x27 > +#define ADC7_AMUX_THM5_30K_PU 0x28 > +#define ADC7_AMUX_THM6_30K_PU 0x29 > +#define ADC7_GPIO1_30K_PU 0x2a > +#define ADC7_GPIO2_30K_PU 0x2b > +#define ADC7_GPIO3_30K_PU 0x2c > +#define ADC7_GPIO4_30K_PU 0x2d > +#define ADC7_CC1_ID_30K_PU 0x33 > + > +/* 100k pull-up2 */ > +#define ADC7_AMUX_THM1_100K_PU 0x44 > +#define ADC7_AMUX_THM2_100K_PU 0x45 > +#define ADC7_AMUX_THM3_100K_PU 0x46 > +#define ADC7_AMUX_THM4_100K_PU 0x47 > +#define ADC7_AMUX_THM5_100K_PU 0x48 > +#define ADC7_AMUX_THM6_100K_PU 0x49 > +#define ADC7_GPIO1_100K_PU 0x4a > +#define ADC7_GPIO2_100K_PU 0x4b > +#define ADC7_GPIO3_100K_PU 0x4c > +#define ADC7_GPIO4_100K_PU 0x4d > +#define ADC7_CC1_ID_100K_PU 0x53 > + > +/* 400k pull-up3 */ > +#define ADC7_AMUX_THM1_400K_PU 0x64 > +#define ADC7_AMUX_THM2_400K_PU 0x65 > +#define ADC7_AMUX_THM3_400K_PU 0x66 > +#define ADC7_AMUX_THM4_400K_PU 0x67 > +#define ADC7_AMUX_THM5_400K_PU 0x68 > +#define ADC7_AMUX_THM6_400K_PU 0x69 > +#define ADC7_GPIO1_400K_PU 0x6a > +#define ADC7_GPIO2_400K_PU 0x6b > +#define ADC7_GPIO3_400K_PU 0x6c > +#define ADC7_GPIO4_400K_PU 0x6d > +#define ADC7_CC1_ID_400K_PU 0x73 > + > +/* 1/3 Divider */ > +#define ADC7_GPIO1_DIV3 0x8a > +#define ADC7_GPIO2_DIV3 0x8b > +#define ADC7_GPIO3_DIV3 0x8c > +#define ADC7_GPIO4_DIV3 0x8d > + > +#define ADC7_VPH_PWR 0x8e > +#define ADC7_VBAT_SNS 0x8f > + > +#define ADC7_SBUx 0x94 > +#define ADC7_VBAT_2S_MID 0x96 > + > #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */ ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH V2 2/3] iio: adc: Add PMIC7 ADC bindings 2020-04-18 16:18 ` Jonathan Cameron @ 2020-04-27 12:55 ` Jishnu Prakash 0 siblings, 0 replies; 15+ messages in thread From: Jishnu Prakash @ 2020-04-27 12:55 UTC (permalink / raw) To: Jonathan Cameron Cc: agross, bjorn.andersson, devicetree, linux-kernel, mka, linus.walleij, Jonathan.Cameron, smohanad, kgunda, aghayal, Hartmut Knaack, Lars-Peter Clausen, Peter Meerwald-Stadler, Rob Herring, Mark Rutland, linux-iio, linux-arm-msm, linux-arm-msm-owner Hi Jonathan, On 4/18/2020 9:48 PM, Jonathan Cameron wrote: > On Wed, 15 Apr 2020 14:47:45 +0530 > Jishnu Prakash <jprakash@codeaurora.org> wrote: > > We are enforcing them in the binding. Does it make sense to put them here as well? > Just seems like something that will get out of sync to me. I'll remove the redundant parts of the descriptions in the next post. > ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH V2 2/3] iio: adc: Add PMIC7 ADC bindings 2020-04-15 9:17 ` [PATCH V2 2/3] iio: adc: Add PMIC7 ADC bindings Jishnu Prakash 2020-04-18 16:18 ` Jonathan Cameron @ 2020-04-20 22:02 ` Rob Herring 2020-04-27 12:54 ` Jishnu Prakash 1 sibling, 1 reply; 15+ messages in thread From: Rob Herring @ 2020-04-20 22:02 UTC (permalink / raw) To: Jishnu Prakash Cc: agross, bjorn.andersson, devicetree, linux-kernel, mka, linus.walleij, Jonathan.Cameron, smohanad, kgunda, aghayal, Jonathan Cameron, Hartmut Knaack, Lars-Peter Clausen, Peter Meerwald-Stadler, Mark Rutland, linux-iio, linux-arm-msm, linux-arm-msm-owner On Wed, Apr 15, 2020 at 02:47:45PM +0530, Jishnu Prakash wrote: > Add documentation for PMIC7 ADC peripheral. > For the PMIC7-type PMICs, ADC peripheral is present in HW for the > following PMICs: PMK8350, PM8350, PM8350b, PMR735a and PMR735b. > Of these, only the ADC peripheral on PMK8350 is exposed directly to SW. > If SW needs to communicate with ADCs on other PMICs, it specifies the > PMIC to PMK8350 through the newly added SID register and communication > between PMK8350 ADC and other PMIC ADCs is carried out through > PBS(Programmable Boot Sequence) at the firmware level. > > In addition, add definitions for ADC channels and virtual channel > definitions (combination of ADC channel number and PMIC SID number) > per PMIC, to be used by ADC clients for PMIC7. > > Signed-off-by: Jishnu Prakash <jprakash@codeaurora.org> > --- > .../bindings/iio/adc/qcom,spmi-vadc.yaml | 52 +++++++++++-- > include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h | 67 ++++++++++++++++ > include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h | 88 ++++++++++++++++++++++ > include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h | 46 +++++++++++ > include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h | 28 +++++++ > include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h | 28 +++++++ > include/dt-bindings/iio/qcom,spmi-vadc.h | 78 ++++++++++++++++++- > 7 files changed, 380 insertions(+), 7 deletions(-) > create mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h > create mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h > create mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h > create mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h > create mode 100644 include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h > > diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml > index 8273981..62aa311 100644 > --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml > +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml > @@ -13,7 +13,7 @@ maintainers: > description: | > SPMI PMIC voltage ADC (VADC) provides interface to clients to read > voltage. The VADC is a 15-bit sigma-delta ADC. > - SPMI PMIC5 voltage ADC (ADC) provides interface to clients to read > + SPMI PMIC5/PMIC7 voltage ADC (ADC) provides interface to clients to read > voltage. The VADC is a 16-bit sigma-delta ADC. > > properties: > @@ -28,6 +28,7 @@ properties: > - qcom,spmi-vadc > - qcom,spmi-adc5 > - qcom,spmi-adc-rev2 > + - qcom,spmi-adc7 > > reg: > description: VADC base address in the SPMI PMIC register map > @@ -70,6 +71,8 @@ patternProperties: > description: | > ADC channel number. > See include/dt-bindings/iio/qcom,spmi-vadc.h > + For PMIC7 ADC, the channel numbers are specified separately per PMIC > + in the PMIC-specific files in include/dt-bindings/iio/. > > label: > $ref: /schemas/types.yaml#/definitions/string > @@ -89,6 +92,8 @@ patternProperties: > of 512 will be used. > - For compatible property "qcom,spmi-adc5", valid values are 250, 420 > and 840. If property is not found, default value of 840 is used. > + - For compatible property "qcom,spmi-adc7", valid values are 85, 340 > + and 1360. If property is not found, default value of 1360 is used. We express constraints in schema now, don't duplicate with free form text. > - For compatible property "qcom,spmi-adc-rev2", valid values are 256, > 512 and 1024. If property is not present, default value is 1024. > > @@ -122,11 +127,11 @@ patternProperties: > channel calibration. If property is not found, channel will be > calibrated with 0.625V and 1.25V reference channels, also > known as absolute calibration. > - - For compatible property "qcom,spmi-adc5" and "qcom,spmi-adc-rev2", > - if this property is specified VADC will use the VDD reference (1.875V) > - and GND for channel calibration. If property is not found, channel > - will be calibrated with 0V and 1.25V reference channels, also known > - as absolute calibration. > + - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc7" and > + "qcom,spmi-adc-rev2", if this property is specified VADC will use > + the VDD reference (1.875V) and GND for channel calibration. If > + property is not found, channel will be calibrated with 0V and 1.25V > + reference channels, also known as absolute calibration. > type: boolean > > qcom,hw-settle-time: > @@ -149,6 +154,12 @@ patternProperties: > Certain controller digital versions have valid values of > 15, 100, 200, 300, 400, 500, 600, 700, 1, 2, 4, 8, 16, 32, 64, 128 ms > If property is not found, channel will use 15us. > + - For compatible property "qcom,spmi-adc7", delay = 15us for > + value 0, 100us * (value) for values < 8, 1ms for value 8 > + and 2ms * (value - 8) otherwise. > + Valid values are: 15, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, > + 4000, 8000, 16000, 32000, 64000, 128000 us. > + If property is not found, channel will use 15us. > > qcom,avg-samples: > $ref: /schemas/types.yaml#/definitions/uint32 > @@ -160,6 +171,9 @@ patternProperties: > - For compatible property "qcom,spmi-vadc", valid values > are: 1, 2, 4, 8, 16, 32, 64, 128, 256, 512 > If property is not found, 1 sample will be used. > + - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc7" > + and "qcom,spmi-adc-rev2", valid values are: 1, 2, 4, 8, 16. > + If property is not found, 1 sample will be used. > > required: > - reg > @@ -244,6 +258,32 @@ allOf: > enum: [ 1, 2, 4, 8, 16 ] > default: 1 > > + - if: > + properties: > + compatible: > + contains: > + const: qcom,spmi-adc7 > + > + then: > + patternProperties: > + "^.*@[0-9a-fx]+$": 'x' should not be in unit-addresses. > + properties: > + qcom,decimation: > + items: Not an array, so 'items' doesn't make sense here. > + enum: [ 85, 340, 1360 ] > + default: 1360 > + > + qcom,hw-settle-time: > + items: > + enum: [ 15, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, 4000, > + 8000, 16000, 32000, 64000, 128000 ] > + default: 15 > + > + qcom,avg-samples: > + items: > + enum: [ 1, 2, 4, 8, 16 ] > + default: 1 > + > examples: > - | > spmi_bus { ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH V2 2/3] iio: adc: Add PMIC7 ADC bindings 2020-04-20 22:02 ` Rob Herring @ 2020-04-27 12:54 ` Jishnu Prakash 0 siblings, 0 replies; 15+ messages in thread From: Jishnu Prakash @ 2020-04-27 12:54 UTC (permalink / raw) To: Rob Herring Cc: agross, bjorn.andersson, devicetree, linux-kernel, mka, linus.walleij, Jonathan.Cameron, smohanad, kgunda, aghayal, Jonathan Cameron, Hartmut Knaack, Lars-Peter Clausen, Peter Meerwald-Stadler, Mark Rutland, linux-iio, linux-arm-msm, linux-arm-msm-owner Hi Rob, On 4/21/2020 3:32 AM, Rob Herring wrote: > On Wed, Apr 15, 2020 at 02:47:45PM +0530, Jishnu Prakash wrote: >> of 512 will be used. >> - For compatible property "qcom,spmi-adc5", valid values are 250, 420 >> and 840. If property is not found, default value of 840 is used. >> + - For compatible property "qcom,spmi-adc7", valid values are 85, 340 >> + and 1360. If property is not found, default value of 1360 is used. > We express constraints in schema now, don't duplicate with free form > text. I'll remove the redundant parts of the descriptions in the next post. > >> - For compatible property "qcom,spmi-adc-rev2", valid values are 256, >> 512 and 1024. If property is not present, default value is 1024. >> + then: >> + patternProperties: >> + "^.*@[0-9a-fx]+$": > 'x' should not be in unit-addresses. I'll remove it in the next post. > >> + properties: >> + qcom,decimation: >> + items: > Not an array, so 'items' doesn't make sense here. I'll remove it in the next post. > >> + enum: [ 85, 340, 1360 ] >> + default: 1360 >> + >> ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH V2 3/3] iio: adc: Add support for PMIC7 ADC 2020-04-15 9:17 [PATCH V2 0/3] iio: adc: Add support for QCOM SPMI PMIC7 ADC Jishnu Prakash 2020-04-15 9:17 ` [PATCH V2 1/3] iio: adc: Convert the QCOM SPMI ADC bindings to .yaml format Jishnu Prakash 2020-04-15 9:17 ` [PATCH V2 2/3] iio: adc: Add PMIC7 ADC bindings Jishnu Prakash @ 2020-04-15 9:17 ` Jishnu Prakash 2020-04-17 10:21 ` Andy Shevchenko 2 siblings, 1 reply; 15+ messages in thread From: Jishnu Prakash @ 2020-04-15 9:17 UTC (permalink / raw) To: agross, bjorn.andersson, devicetree, linux-kernel, mka, linus.walleij, Jonathan.Cameron, smohanad, kgunda, aghayal, Jonathan Cameron, Hartmut Knaack, Lars-Peter Clausen, Peter Meerwald-Stadler, linux-arm-msm, linux-iio Cc: linux-arm-msm-owner, Jishnu Prakash The ADC architecture on PMIC7 is changed as compared to PMIC5. The major change from PMIC5 is that all SW communication to ADC goes through PMK8350, which communicates with other PMICs through PBS when the ADC on PMK8350 works in master mode. The SID register is used to identify the PMICs with which the PBS needs to communicate. Add support for the same. Signed-off-by: Jishnu Prakash <jprakash@codeaurora.org> --- drivers/iio/adc/qcom-spmi-adc5.c | 257 ++++++++++++++++++++++++++++++++++-- drivers/iio/adc/qcom-vadc-common.c | 258 +++++++++++++++++++++++++++++++++++++ drivers/iio/adc/qcom-vadc-common.h | 15 +++ 3 files changed, 517 insertions(+), 13 deletions(-) diff --git a/drivers/iio/adc/qcom-spmi-adc5.c b/drivers/iio/adc/qcom-spmi-adc5.c index 21fdcde..8d86ed0 100644 --- a/drivers/iio/adc/qcom-spmi-adc5.c +++ b/drivers/iio/adc/qcom-spmi-adc5.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved. */ #include <linux/bitops.h> @@ -23,6 +23,7 @@ #define ADC5_USR_REVISION1 0x0 #define ADC5_USR_STATUS1 0x8 +#define ADC5_USR_STATUS1_CONV_FAULT BIT(7) #define ADC5_USR_STATUS1_REQ_STS BIT(1) #define ADC5_USR_STATUS1_EOC BIT(0) #define ADC5_USR_STATUS1_REQ_STS_EOC_MASK 0x3 @@ -65,6 +66,9 @@ #define ADC5_USR_IBAT_DATA1 0x53 +#define ADC_CHANNEL_OFFSET 0x8 +#define ADC_CHANNEL_MASK GENMASK(7, 0) + /* * Conversion time varies based on the decimation, clock rate, fast average * samples and measurements queued across different VADC peripherals. @@ -79,6 +83,11 @@ #define ADC5_HW_SETTLE_DIFF_MINOR 3 #define ADC5_HW_SETTLE_DIFF_MAJOR 5 +/* For PMIC7 */ +#define ADC_APP_SID 0x40 +#define ADC_APP_SID_MASK GENMASK(3, 0) +#define ADC7_CONV_TIMEOUT msecs_to_jiffies(10) + enum adc5_cal_method { ADC5_NO_CAL = 0, ADC5_RATIOMETRIC_CAL, @@ -96,6 +105,7 @@ enum adc5_cal_val { * @cal_method: calibration method. * @cal_val: calibration value * @decimation: sampling rate supported for the channel. + * @sid: slave id of PMIC owning the channel, for PMIC7. * @prescale: channel scaling performed on the input signal. * @hw_settle_time: the time between AMUX being configured and the * start of conversion. @@ -110,6 +120,7 @@ struct adc5_channel_prop { enum adc5_cal_method cal_method; enum adc5_cal_val cal_val; unsigned int decimation; + unsigned int sid; unsigned int prescale; unsigned int hw_settle_time; unsigned int avg_samples; @@ -140,6 +151,7 @@ struct adc5_chip { bool poll_eoc; struct completion complete; struct mutex lock; + int irq_eoc; const struct adc5_data *data; }; @@ -155,6 +167,8 @@ static const struct vadc_prescale_ratio adc5_prescale_ratios[] = { {.num = 1, .den = 16} }; +static const struct adc5_data adc7_data_pmic; + static int adc5_read(struct adc5_chip *adc, u16 offset, u8 *data, int len) { return regmap_bulk_read(adc->regmap, adc->base + offset, data, len); @@ -165,6 +179,11 @@ static int adc5_write(struct adc5_chip *adc, u16 offset, u8 *data, int len) return regmap_bulk_write(adc->regmap, adc->base + offset, data, len); } +static int adc5_masked_write(struct adc5_chip *adc, u16 offset, u8 mask, u8 val) +{ + return regmap_update_bits(adc->regmap, adc->base + offset, mask, val); +} + static int adc5_prescaling_from_dt(u32 num, u32 den) { unsigned int pre; @@ -230,11 +249,11 @@ static int adc5_read_voltage_data(struct adc5_chip *adc, u16 *data) *data = (rslt_msb << 8) | rslt_lsb; if (*data == ADC5_USR_DATA_CHECK) { - pr_err("Invalid data:0x%x\n", *data); + dev_err(adc->dev, "Invalid data:0x%x\n", *data); return -EINVAL; } - pr_debug("voltage raw code:0x%x\n", *data); + dev_dbg(adc->dev, "voltage raw code:0x%x\n", *data); return 0; } @@ -314,6 +333,47 @@ static int adc5_configure(struct adc5_chip *adc, return adc5_write(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf)); } +static int adc7_configure(struct adc5_chip *adc, + struct adc5_channel_prop *prop) +{ + int ret; + u8 conv_req = 0, buf[4]; + + ret = adc5_masked_write(adc, ADC_APP_SID, ADC_APP_SID_MASK, prop->sid); + if (ret) + return ret; + + ret = adc5_read(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf)); + if (ret < 0) + return ret; + + /* Digital param selection */ + adc5_update_dig_param(adc, prop, &buf[0]); + + /* Update fast average sample value */ + buf[1] &= 0xff & ~ADC5_USR_FAST_AVG_CTL_SAMPLES_MASK; + buf[1] |= prop->avg_samples; + + /* Select ADC channel */ + buf[2] = prop->channel; + + /* Select HW settle delay for channel */ + buf[3] &= 0xff & ~ADC5_USR_HW_SETTLE_DELAY_MASK; + buf[3] |= prop->hw_settle_time; + + /* Select CONV request */ + conv_req = ADC5_USR_CONV_REQ_REQ; + + if (!adc->poll_eoc) + reinit_completion(&adc->complete); + + ret = adc5_write(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf)); + if (ret) + return ret; + + return adc5_write(adc, ADC5_USR_CONV_REQ, &conv_req, 1); +} + static int adc5_do_conversion(struct adc5_chip *adc, struct adc5_channel_prop *prop, struct iio_chan_spec const *chan, @@ -325,24 +385,24 @@ static int adc5_do_conversion(struct adc5_chip *adc, ret = adc5_configure(adc, prop); if (ret) { - pr_err("ADC configure failed with %d\n", ret); + dev_err(adc->dev, "ADC configure failed with %d\n", ret); goto unlock; } if (adc->poll_eoc) { ret = adc5_poll_wait_eoc(adc); if (ret < 0) { - pr_err("EOC bit not set\n"); + dev_err(adc->dev, "EOC bit not set\n"); goto unlock; } } else { ret = wait_for_completion_timeout(&adc->complete, ADC5_CONV_TIMEOUT); if (!ret) { - pr_debug("Did not get completion timeout.\n"); + dev_dbg(adc->dev, "Did not get completion timeout.\n"); ret = adc5_poll_wait_eoc(adc); if (ret < 0) { - pr_err("EOC bit not set\n"); + dev_err(adc->dev, "EOC bit not set\n"); goto unlock; } } @@ -355,6 +415,43 @@ static int adc5_do_conversion(struct adc5_chip *adc, return ret; } +static int adc7_do_conversion(struct adc5_chip *adc, + struct adc5_channel_prop *prop, + struct iio_chan_spec const *chan, + u16 *data_volt, u16 *data_cur) +{ + int ret; + u8 status = 0; + + mutex_lock(&adc->lock); + + ret = adc7_configure(adc, prop); + if (ret) { + dev_err(adc->dev, "ADC configure failed with %d\n", ret); + goto unlock; + } + + /* No support for polling mode at present*/ + wait_for_completion_timeout(&adc->complete, ADC7_CONV_TIMEOUT); + + ret = adc5_read(adc, ADC5_USR_STATUS1, &status, 1); + if (ret < 0) + goto unlock; + + if (status & ADC5_USR_STATUS1_CONV_FAULT) { + dev_err(adc->dev, "Unexpected conversion fault\n"); + ret = -EIO; + goto unlock; + } + + ret = adc5_read_voltage_data(adc, data_volt); + +unlock: + mutex_unlock(&adc->lock); + + return ret; +} + static irqreturn_t adc5_isr(int irq, void *dev_id) { struct adc5_chip *adc = dev_id; @@ -377,6 +474,56 @@ static int adc5_of_xlate(struct iio_dev *indio_dev, return -EINVAL; } +static int adc7_of_xlate(struct iio_dev *indio_dev, + const struct of_phandle_args *iiospec) +{ + struct adc5_chip *adc = iio_priv(indio_dev); + int i, v_channel; + + for (i = 0; i < adc->nchannels; i++) { + v_channel = (adc->chan_props[i].sid << ADC_CHANNEL_OFFSET | + adc->chan_props[i].channel); + if (v_channel == iiospec->args[0]) + return i; + } + + return -EINVAL; +} + +static int adc7_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val, int *val2, + long mask) +{ + struct adc5_chip *adc = iio_priv(indio_dev); + struct adc5_channel_prop *prop; + u16 adc_code_volt, adc_code_cur; + int ret; + + prop = &adc->chan_props[chan->address]; + + switch (mask) { + case IIO_CHAN_INFO_PROCESSED: + ret = adc7_do_conversion(adc, prop, chan, + &adc_code_volt, &adc_code_cur); + if (ret) + return ret; + + ret = qcom_adc5_hw_scale(prop->scale_fn_type, + &adc5_prescale_ratios[prop->prescale], + adc->data, + adc_code_volt, val); + + if (ret) + return ret; + + return IIO_VAL_INT; + default: + return -EINVAL; + } + + return 0; +} + static int adc5_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) @@ -415,6 +562,11 @@ static const struct iio_info adc5_info = { .of_xlate = adc5_of_xlate, }; +static const struct iio_info adc7_info = { + .read_raw = adc7_read_raw, + .of_xlate = adc7_of_xlate, +}; + struct adc5_channels { const char *datasheet_name; unsigned int prescale_index; @@ -477,6 +629,39 @@ static const struct adc5_channels adc5_chans_pmic[ADC5_MAX_CHANNEL] = { SCALE_HW_CALIB_PM5_SMB_TEMP) }; +static const struct adc5_channels adc7_chans_pmic[ADC5_MAX_CHANNEL] = { + [ADC7_REF_GND] = ADC5_CHAN_VOLT("ref_gnd", 0, + SCALE_HW_CALIB_DEFAULT) + [ADC7_1P25VREF] = ADC5_CHAN_VOLT("vref_1p25", 0, + SCALE_HW_CALIB_DEFAULT) + [ADC7_VPH_PWR] = ADC5_CHAN_VOLT("vph_pwr", 1, + SCALE_HW_CALIB_DEFAULT) + [ADC7_VBAT_SNS] = ADC5_CHAN_VOLT("vbat_sns", 3, + SCALE_HW_CALIB_DEFAULT) + [ADC7_DIE_TEMP] = ADC5_CHAN_TEMP("die_temp", 0, + SCALE_HW_CALIB_PMIC_THERM_PM7) + [ADC7_AMUX_THM1_100K_PU] = ADC5_CHAN_TEMP("amux_thm1_pu2", 0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC7_AMUX_THM2_100K_PU] = ADC5_CHAN_TEMP("amux_thm2_pu2", 0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC7_AMUX_THM3_100K_PU] = ADC5_CHAN_TEMP("amux_thm3_pu2", 0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC7_AMUX_THM4_100K_PU] = ADC5_CHAN_TEMP("amux_thm4_pu2", 0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC7_AMUX_THM5_100K_PU] = ADC5_CHAN_TEMP("amux_thm5_pu2", 0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC7_AMUX_THM6_100K_PU] = ADC5_CHAN_TEMP("amux_thm6_pu2", 0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC7_GPIO1_100K_PU] = ADC5_CHAN_TEMP("gpio1_pu2", 0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC7_GPIO2_100K_PU] = ADC5_CHAN_TEMP("gpio2_pu2", 0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC7_GPIO3_100K_PU] = ADC5_CHAN_TEMP("gpio3_pu2", 0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC7_GPIO4_100K_PU] = ADC5_CHAN_TEMP("gpio4_pu2", 0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) +}; + static const struct adc5_channels adc5_chans_rev2[ADC5_MAX_CHANNEL] = { [ADC5_REF_GND] = ADC5_CHAN_VOLT("ref_gnd", 0, SCALE_HW_CALIB_DEFAULT) @@ -511,6 +696,7 @@ static int adc5_get_dt_channel_data(struct adc5_chip *adc, { const char *name = node->name, *channel_name; u32 chan, value, varr[2]; + u32 sid = 0; int ret; struct device *dev = adc->dev; @@ -520,6 +706,15 @@ static int adc5_get_dt_channel_data(struct adc5_chip *adc, return ret; } + /* + * Value read from "reg" is virtual channel number + * virtual channel number = (sid << 8 | channel number). + */ + if (adc->data == &adc7_data_pmic) { + sid = chan >> ADC_CHANNEL_OFFSET; + chan = chan & ADC_CHANNEL_MASK; + } + if (chan > ADC5_PARALLEL_ISENSE_VBAT_IDATA || !data->adc_chans[chan].datasheet_name) { dev_err(dev, "%s invalid channel number %d\n", name, chan); @@ -528,11 +723,12 @@ static int adc5_get_dt_channel_data(struct adc5_chip *adc, /* the channel has DT description */ prop->channel = chan; + prop->sid = sid; channel_name = of_get_property(node, "label", NULL) ? : node->name; if (!channel_name) { - pr_err("Invalid channel name\n"); + dev_err(dev,"Invalid channel name\n"); return -EINVAL; } prop->datasheet_name = channel_name; @@ -575,11 +771,12 @@ static int adc5_get_dt_channel_data(struct adc5_chip *adc, return ret; } - pr_debug("dig_ver:minor:%d, major:%d\n", dig_version[0], + dev_dbg(adc->dev, "dig_ver:minor:%d, major:%d\n", dig_version[0], dig_version[1]); /* Digital controller >= 5.3 have hw_settle_2 option */ - if (dig_version[0] >= ADC5_HW_SETTLE_DIFF_MINOR && - dig_version[1] >= ADC5_HW_SETTLE_DIFF_MAJOR) + if ((dig_version[0] >= ADC5_HW_SETTLE_DIFF_MINOR && + dig_version[1] >= ADC5_HW_SETTLE_DIFF_MAJOR) || + adc->data == &adc7_data_pmic) ret = adc5_hw_settle_time_from_dt(value, data->hw_settle_2); else @@ -629,6 +826,7 @@ static const struct adc5_data adc5_data_pmic = { .full_scale_code_volt = 0x70e4, .full_scale_code_cur = 0x2710, .adc_chans = adc5_chans_pmic, + .info = &adc5_info, .decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX]) {250, 420, 840}, .hw_settle_1 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX]) @@ -639,10 +837,23 @@ static const struct adc5_data adc5_data_pmic = { 1, 2, 4, 8, 16, 32, 64, 128}, }; +static const struct adc5_data adc7_data_pmic = { + .full_scale_code_volt = 0x70e4, + .adc_chans = adc7_chans_pmic, + .info = &adc7_info, + .decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX]) + {85, 340, 1360}, + .hw_settle_2 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX]) + {15, 100, 200, 300, 400, 500, 600, 700, + 1000, 2000, 4000, 8000, 16000, 32000, + 64000, 128000}, +}; + static const struct adc5_data adc5_data_pmic_rev2 = { .full_scale_code_volt = 0x4000, .full_scale_code_cur = 0x1800, .adc_chans = adc5_chans_rev2, + .info = &adc5_info, .decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX]) {256, 512, 1024}, .hw_settle_1 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX]) @@ -659,6 +870,10 @@ static const struct of_device_id adc5_match_table[] = { .data = &adc5_data_pmic, }, { + .compatible = "qcom,spmi-adc7", + .data = &adc7_data_pmic, + }, + { .compatible = "qcom,spmi-adc-rev2", .data = &adc5_data_pmic_rev2, }, @@ -752,15 +967,20 @@ static int adc5_probe(struct platform_device *pdev) adc->regmap = regmap; adc->dev = dev; adc->base = reg; + + platform_set_drvdata(pdev, adc); + init_completion(&adc->complete); mutex_init(&adc->lock); ret = adc5_get_dt_data(adc, node); if (ret) { - pr_err("adc get dt data failed\n"); + dev_err(dev, "adc get dt data failed\n"); return ret; } + indio_dev->info = adc->data->info; + irq_eoc = platform_get_irq(pdev, 0); if (irq_eoc < 0) { if (irq_eoc == -EPROBE_DEFER || irq_eoc == -EINVAL) @@ -773,23 +993,34 @@ static int adc5_probe(struct platform_device *pdev) return ret; } + adc->irq_eoc = irq_eoc; + indio_dev->dev.parent = dev; indio_dev->dev.of_node = node; indio_dev->name = pdev->name; indio_dev->modes = INDIO_DIRECT_MODE; - indio_dev->info = &adc5_info; indio_dev->channels = adc->iio_chans; indio_dev->num_channels = adc->nchannels; return devm_iio_device_register(dev, indio_dev); } +static int adc5_exit(struct platform_device *pdev) +{ + struct adc5_chip *adc = platform_get_drvdata(pdev); + + if (adc->irq_eoc >= 0) + disable_irq(adc->irq_eoc); + return 0; +} + static struct platform_driver adc5_driver = { .driver = { .name = "qcom-spmi-adc5.c", .of_match_table = adc5_match_table, }, .probe = adc5_probe, + .remove = adc5_exit, }; module_platform_driver(adc5_driver); diff --git a/drivers/iio/adc/qcom-vadc-common.c b/drivers/iio/adc/qcom-vadc-common.c index 2bb78d1..2194029 100644 --- a/drivers/iio/adc/qcom-vadc-common.c +++ b/drivers/iio/adc/qcom-vadc-common.c @@ -89,6 +89,195 @@ static const struct vadc_map_pt adcmap_100k_104ef_104fb_1875_vref[] = { { 46, 125000 }, }; +static const struct vadc_map_pt adcmap7_die_temp[] = { + { 433700, 1967}, + { 473100, 1964}, + { 512400, 1957}, + { 551500, 1949}, + { 590500, 1940}, + { 629300, 1930}, + { 667900, 1921}, + { 706400, 1910}, + { 744600, 1896}, + { 782500, 1878}, + { 820100, 1859}, + { 857300, 0}, +}; + +/* + * Resistance to temperature table for 100k pull up for NTCG104EF104. + */ +static const struct vadc_map_pt adcmap7_100k[] = { + { 4250657, -40960 }, + { 3962085, -39936 }, + { 3694875, -38912 }, + { 3447322, -37888 }, + { 3217867, -36864 }, + { 3005082, -35840 }, + { 2807660, -34816 }, + { 2624405, -33792 }, + { 2454218, -32768 }, + { 2296094, -31744 }, + { 2149108, -30720 }, + { 2012414, -29696 }, + { 1885232, -28672 }, + { 1766846, -27648 }, + { 1656598, -26624 }, + { 1553884, -25600 }, + { 1458147, -24576 }, + { 1368873, -23552 }, + { 1285590, -22528 }, + { 1207863, -21504 }, + { 1135290, -20480 }, + { 1067501, -19456 }, + { 1004155, -18432 }, + { 944935, -17408 }, + { 889550, -16384 }, + { 837731, -15360 }, + { 789229, -14336 }, + { 743813, -13312 }, + { 701271, -12288 }, + { 661405, -11264 }, + { 624032, -10240 }, + { 588982, -9216 }, + { 556100, -8192 }, + { 525239, -7168 }, + { 496264, -6144 }, + { 469050, -5120 }, + { 443480, -4096 }, + { 419448, -3072 }, + { 396851, -2048 }, + { 375597, -1024 }, + { 355598, 0 }, + { 336775, 1024 }, + { 319052, 2048 }, + { 302359, 3072 }, + { 286630, 4096 }, + { 271806, 5120 }, + { 257829, 6144 }, + { 244646, 7168 }, + { 232209, 8192 }, + { 220471, 9216 }, + { 209390, 10240 }, + { 198926, 11264 }, + { 189040, 12288 }, + { 179698, 13312 }, + { 170868, 14336 }, + { 162519, 15360 }, + { 154622, 16384 }, + { 147150, 17408 }, + { 140079, 18432 }, + { 133385, 19456 }, + { 127046, 20480 }, + { 121042, 21504 }, + { 115352, 22528 }, + { 109960, 23552 }, + { 104848, 24576 }, + { 100000, 25600 }, + { 95402, 26624 }, + { 91038, 27648 }, + { 86897, 28672 }, + { 82965, 29696 }, + { 79232, 30720 }, + { 75686, 31744 }, + { 72316, 32768 }, + { 69114, 33792 }, + { 66070, 34816 }, + { 63176, 35840 }, + { 60423, 36864 }, + { 57804, 37888 }, + { 55312, 38912 }, + { 52940, 39936 }, + { 50681, 40960 }, + { 48531, 41984 }, + { 46482, 43008 }, + { 44530, 44032 }, + { 42670, 45056 }, + { 40897, 46080 }, + { 39207, 47104 }, + { 37595, 48128 }, + { 36057, 49152 }, + { 34590, 50176 }, + { 33190, 51200 }, + { 31853, 52224 }, + { 30577, 53248 }, + { 29358, 54272 }, + { 28194, 55296 }, + { 27082, 56320 }, + { 26020, 57344 }, + { 25004, 58368 }, + { 24033, 59392 }, + { 23104, 60416 }, + { 22216, 61440 }, + { 21367, 62464 }, + { 20554, 63488 }, + { 19776, 64512 }, + { 19031, 65536 }, + { 18318, 66560 }, + { 17636, 67584 }, + { 16982, 68608 }, + { 16355, 69632 }, + { 15755, 70656 }, + { 15180, 71680 }, + { 14628, 72704 }, + { 14099, 73728 }, + { 13592, 74752 }, + { 13106, 75776 }, + { 12640, 76800 }, + { 12192, 77824 }, + { 11762, 78848 }, + { 11350, 79872 }, + { 10954, 80896 }, + { 10574, 81920 }, + { 10209, 82944 }, + { 9858, 83968 }, + { 9521, 84992 }, + { 9197, 86016 }, + { 8886, 87040 }, + { 8587, 88064 }, + { 8299, 89088 }, + { 8023, 90112 }, + { 7757, 91136 }, + { 7501, 92160 }, + { 7254, 93184 }, + { 7017, 94208 }, + { 6789, 95232 }, + { 6570, 96256 }, + { 6358, 97280 }, + { 6155, 98304 }, + { 5959, 99328 }, + { 5770, 100352 }, + { 5588, 101376 }, + { 5412, 102400 }, + { 5243, 103424 }, + { 5080, 104448 }, + { 4923, 105472 }, + { 4771, 106496 }, + { 4625, 107520 }, + { 4484, 108544 }, + { 4348, 109568 }, + { 4217, 110592 }, + { 4090, 111616 }, + { 3968, 112640 }, + { 3850, 113664 }, + { 3736, 114688 }, + { 3626, 115712 }, + { 3519, 116736 }, + { 3417, 117760 }, + { 3317, 118784 }, + { 3221, 119808 }, + { 3129, 120832 }, + { 3039, 121856 }, + { 2952, 122880 }, + { 2868, 123904 }, + { 2787, 124928 }, + { 2709, 125952 }, + { 2633, 126976 }, + { 2560, 128000 }, + { 2489, 129024 }, + { 2420, 130048 } +}; + static int qcom_vadc_scale_hw_calib_volt( const struct vadc_prescale_ratio *prescale, const struct adc5_data *data, @@ -97,6 +286,10 @@ static int qcom_vadc_scale_hw_calib_therm( const struct vadc_prescale_ratio *prescale, const struct adc5_data *data, u16 adc_code, int *result_mdec); +static int qcom_vadc7_scale_hw_calib_therm( + const struct vadc_prescale_ratio *prescale, + const struct adc5_data *data, + u16 adc_code, int *result_mdec); static int qcom_vadc_scale_hw_smb_temp( const struct vadc_prescale_ratio *prescale, const struct adc5_data *data, @@ -109,12 +302,20 @@ static int qcom_vadc_scale_hw_calib_die_temp( const struct vadc_prescale_ratio *prescale, const struct adc5_data *data, u16 adc_code, int *result_mdec); +static int qcom_vadc7_scale_hw_calib_die_temp( + const struct vadc_prescale_ratio *prescale, + const struct adc5_data *data, + u16 adc_code, int *result_mdec); static struct qcom_adc5_scale_type scale_adc5_fn[] = { [SCALE_HW_CALIB_DEFAULT] = {qcom_vadc_scale_hw_calib_volt}, [SCALE_HW_CALIB_THERM_100K_PULLUP] = {qcom_vadc_scale_hw_calib_therm}, [SCALE_HW_CALIB_XOTHERM] = {qcom_vadc_scale_hw_calib_therm}, + [SCALE_HW_CALIB_THERM_100K_PU_PM7] = { + qcom_vadc7_scale_hw_calib_therm}, [SCALE_HW_CALIB_PMIC_THERM] = {qcom_vadc_scale_hw_calib_die_temp}, + [SCALE_HW_CALIB_PMIC_THERM_PM7] = { + qcom_vadc7_scale_hw_calib_die_temp}, [SCALE_HW_CALIB_PM5_CHG_TEMP] = {qcom_vadc_scale_hw_chg5_temp}, [SCALE_HW_CALIB_PM5_SMB_TEMP] = {qcom_vadc_scale_hw_smb_temp}, }; @@ -291,6 +492,32 @@ static int qcom_vadc_scale_code_voltage_factor(u16 adc_code, return (int) voltage; } +static int qcom_vadc7_scale_hw_calib_therm( + const struct vadc_prescale_ratio *prescale, + const struct adc5_data *data, + u16 adc_code, int *result_mdec) +{ + s64 resistance = adc_code; + int ret, result = 0; + + if (adc_code >= RATIO_MAX_ADC7) + return -EINVAL; + + /* (ADC code * R_PULLUP (100Kohm)) / (full_scale_code - ADC code)*/ + resistance *= R_PU_100K; + resistance = div64_s64(resistance, RATIO_MAX_ADC7 - adc_code); + + ret = qcom_vadc_map_voltage_temp(adcmap7_100k, + ARRAY_SIZE(adcmap7_100k), + resistance, &result); + if (ret) + return ret; + + *result_mdec = result; + + return 0; +} + static int qcom_vadc_scale_hw_calib_volt( const struct vadc_prescale_ratio *prescale, const struct adc5_data *data, @@ -330,6 +557,37 @@ static int qcom_vadc_scale_hw_calib_die_temp( return 0; } +static int qcom_vadc7_scale_hw_calib_die_temp( + const struct vadc_prescale_ratio *prescale, + const struct adc5_data *data, + u16 adc_code, int *result_mdec) +{ + + int voltage, vtemp0, temp, i; + + voltage = qcom_vadc_scale_code_voltage_factor(adc_code, + prescale, data, 1); + + for (i = 0; i < ARRAY_SIZE(adcmap7_die_temp); i++) + if (adcmap7_die_temp[i].x > voltage) + break; + + if (i == 0) { + *result_mdec = DIE_TEMP_ADC7_SCALE_1; + } else if (i == ARRAY_SIZE(adcmap7_die_temp)) { + *result_mdec = DIE_TEMP_ADC7_MAX; + } else { + vtemp0 = adcmap7_die_temp[i - 1].x; + voltage = voltage - vtemp0; + temp = div64_s64(voltage * DIE_TEMP_ADC7_SCALE_FACTOR, + adcmap7_die_temp[i - 1].y); + temp += DIE_TEMP_ADC7_SCALE_1 + (DIE_TEMP_ADC7_SCALE_2 * (i - 1)); + *result_mdec = temp; + } + + return 0; +} + static int qcom_vadc_scale_hw_smb_temp( const struct vadc_prescale_ratio *prescale, const struct adc5_data *data, diff --git a/drivers/iio/adc/qcom-vadc-common.h b/drivers/iio/adc/qcom-vadc-common.h index e074902a..d195e83 100644 --- a/drivers/iio/adc/qcom-vadc-common.h +++ b/drivers/iio/adc/qcom-vadc-common.h @@ -49,6 +49,14 @@ #define ADC5_FULL_SCALE_CODE 0x70e4 #define ADC5_USR_DATA_CHECK 0x8000 +#define R_PU_100K 100000 +#define RATIO_MAX_ADC7 0x4000 + +#define DIE_TEMP_ADC7_SCALE_1 -60000 +#define DIE_TEMP_ADC7_SCALE_2 20000 +#define DIE_TEMP_ADC7_SCALE_FACTOR 1000 +#define DIE_TEMP_ADC7_MAX 160000 + /** * struct vadc_map_pt - Map the graph representation for ADC channel * @x: Represent the ADC digitized code. @@ -110,8 +118,12 @@ struct vadc_prescale_ratio { * lookup table. The hardware applies offset/slope to adc code. * SCALE_HW_CALIB_XOTHERM: Returns XO thermistor voltage in millidegC using * 100k pullup. The hardware applies offset/slope to adc code. + * SCALE_HW_CALIB_THERM_100K_PU_PM7: Returns temperature in millidegC using + * lookup table for PMIC7. The hardware applies offset/slope to adc code. * SCALE_HW_CALIB_PMIC_THERM: Returns result in milli degree's Centigrade. * The hardware applies offset/slope to adc code. + * SCALE_HW_CALIB_PMIC_THERM: Returns result in milli degree's Centigrade. + * The hardware applies offset/slope to adc code. This is for PMIC7. * SCALE_HW_CALIB_PM5_CHG_TEMP: Returns result in millidegrees for PMIC5 * charger temperature. * SCALE_HW_CALIB_PM5_SMB_TEMP: Returns result in millidegrees for PMIC5 @@ -126,7 +138,9 @@ enum vadc_scale_fn_type { SCALE_HW_CALIB_DEFAULT, SCALE_HW_CALIB_THERM_100K_PULLUP, SCALE_HW_CALIB_XOTHERM, + SCALE_HW_CALIB_THERM_100K_PU_PM7, SCALE_HW_CALIB_PMIC_THERM, + SCALE_HW_CALIB_PMIC_THERM_PM7, SCALE_HW_CALIB_PM5_CHG_TEMP, SCALE_HW_CALIB_PM5_SMB_TEMP, SCALE_HW_CALIB_INVALID, @@ -136,6 +150,7 @@ struct adc5_data { const u32 full_scale_code_volt; const u32 full_scale_code_cur; const struct adc5_channels *adc_chans; + const struct iio_info *info; unsigned int *decimation; unsigned int *hw_settle_1; unsigned int *hw_settle_2; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH V2 3/3] iio: adc: Add support for PMIC7 ADC 2020-04-15 9:17 ` [PATCH V2 3/3] iio: adc: Add support for PMIC7 ADC Jishnu Prakash @ 2020-04-17 10:21 ` Andy Shevchenko [not found] ` <68d9c770-b190-dd13-0869-fdae9fb1f16f@codeaurora.org> 0 siblings, 1 reply; 15+ messages in thread From: Andy Shevchenko @ 2020-04-17 10:21 UTC (permalink / raw) To: Jishnu Prakash Cc: agross, Bjorn Andersson, devicetree, Linux Kernel Mailing List, Matthias Kaehlcke, Linus Walleij, Jonathan Cameron, smohanad, kgunda, aghayal, Jonathan Cameron, Hartmut Knaack, Lars-Peter Clausen, Peter Meerwald-Stadler, linux-arm-msm, linux-iio, linux-arm-msm-owner On Thu, Apr 16, 2020 at 1:48 AM Jishnu Prakash <jprakash@codeaurora.org> wrote: > > The ADC architecture on PMIC7 is changed as compared to PMIC5. The > major change from PMIC5 is that all SW communication to ADC goes through > PMK8350, which communicates with other PMICs through PBS when the ADC > on PMK8350 works in master mode. The SID register is used to identify the > PMICs with which the PBS needs to communicate. Add support for the same. Please, split pr_*() -> dev_*() to separate patch. Also think about other logical pieces you may split out. ... > +static const struct adc5_data adc7_data_pmic; Global variable? Hmm... ... > + int ret; > + u8 conv_req = 0, buf[4]; > + > + ret = adc5_masked_write(adc, ADC_APP_SID, ADC_APP_SID_MASK, prop->sid); > + if (ret) > + return ret; > + > + ret = adc5_read(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf)); > + if (ret < 0) Does > 0 have a meaning? > + return ret; > + > + /* Digital param selection */ > + adc5_update_dig_param(adc, prop, &buf[0]); > + > + /* Update fast average sample value */ > + buf[1] &= 0xff & ~ADC5_USR_FAST_AVG_CTL_SAMPLES_MASK; What the point of 0xff & part? > + buf[1] |= prop->avg_samples; > + > + /* Select ADC channel */ > + buf[2] = prop->channel; > + > + /* Select HW settle delay for channel */ > + buf[3] &= 0xff & ~ADC5_USR_HW_SETTLE_DELAY_MASK; Ditto. > + buf[3] |= prop->hw_settle_time; ... > +static int adc7_do_conversion(struct adc5_chip *adc, > + struct adc5_channel_prop *prop, > + struct iio_chan_spec const *chan, > + u16 *data_volt, u16 *data_cur) > +{ > + int ret; > + u8 status = 0; Redundant assignment. > + mutex_lock(&adc->lock); > + > + ret = adc7_configure(adc, prop); > + if (ret) { > + dev_err(adc->dev, "ADC configure failed with %d\n", ret); > + goto unlock; > + } > + > + /* No support for polling mode at present*/ Missed space > + wait_for_completion_timeout(&adc->complete, ADC7_CONV_TIMEOUT); > + > + ret = adc5_read(adc, ADC5_USR_STATUS1, &status, 1); > + if (ret < 0) Remove all ' < 0' where it is not needed. > + goto unlock; > + > + if (status & ADC5_USR_STATUS1_CONV_FAULT) { > + dev_err(adc->dev, "Unexpected conversion fault\n"); > + ret = -EIO; > + goto unlock; > + } > + > + ret = adc5_read_voltage_data(adc, data_volt); > + > +unlock: > + mutex_unlock(&adc->lock); ... > + for (i = 0; i < adc->nchannels; i++) { > + v_channel = (adc->chan_props[i].sid << ADC_CHANNEL_OFFSET | > + adc->chan_props[i].channel); Too many parentheses or they are in a wrong position. I don't remember operator precedence by heart. > + if (v_channel == iiospec->args[0]) > + return i; > + } ... > + /* > + * Value read from "reg" is virtual channel number > + * virtual channel number = (sid << 8 | channel number). Too many parentheses. And perhaps formulas better to have on a separate line. > + */ ... > +static const struct vadc_map_pt adcmap7_100k[] = { > + { 4250657, -40960 }, > + { 3962085, -39936 }, > + { 419448, -3072 }, > + { 396851, -2048 }, > + { 375597, -1024 }, > + { 355598, 0 }, > + { 336775, 1024 }, > + { 319052, 2048 }, > + { 302359, 3072 }, > + { 2560, 128000 }, > + { 2489, 129024 }, > + { 2420, 130048 } > +}; I'm wondering why you have second column here? Can't you derive it from index? Seems to me pretty easy calculus. ... > + int ret, result = 0; Redundant assignment. > + if (adc_code >= RATIO_MAX_ADC7) > + return -EINVAL; > + > + /* (ADC code * R_PULLUP (100Kohm)) / (full_scale_code - ADC code)*/ > + resistance *= R_PU_100K; > + resistance = div64_s64(resistance, RATIO_MAX_ADC7 - adc_code); > + > + ret = qcom_vadc_map_voltage_temp(adcmap7_100k, > + ARRAY_SIZE(adcmap7_100k), > + resistance, &result); > + if (ret) > + return ret; > + > + *result_mdec = result; ... > + for (i = 0; i < ARRAY_SIZE(adcmap7_die_temp); i++) > + if (adcmap7_die_temp[i].x > voltage) > + break; > + > + if (i == 0) { > + *result_mdec = DIE_TEMP_ADC7_SCALE_1; > + } else if (i == ARRAY_SIZE(adcmap7_die_temp)) { > + *result_mdec = DIE_TEMP_ADC7_MAX; I think you can done these checks before loop, and return immediately. > + } else { > + vtemp0 = adcmap7_die_temp[i - 1].x; > + voltage = voltage - vtemp0; > + temp = div64_s64(voltage * DIE_TEMP_ADC7_SCALE_FACTOR, > + adcmap7_die_temp[i - 1].y); > + temp += DIE_TEMP_ADC7_SCALE_1 + (DIE_TEMP_ADC7_SCALE_2 * (i - 1)); > + *result_mdec = temp; > + } -- With Best Regards, Andy Shevchenko ^ permalink raw reply [flat|nested] 15+ messages in thread
[parent not found: <68d9c770-b190-dd13-0869-fdae9fb1f16f@codeaurora.org>]
* Re: [PATCH V2 3/3] iio: adc: Add support for PMIC7 ADC [not found] ` <68d9c770-b190-dd13-0869-fdae9fb1f16f@codeaurora.org> @ 2020-04-27 13:28 ` Andy Shevchenko 2020-05-13 9:20 ` Jishnu Prakash 0 siblings, 1 reply; 15+ messages in thread From: Andy Shevchenko @ 2020-04-27 13:28 UTC (permalink / raw) To: Jishnu Prakash Cc: agross, Bjorn Andersson, devicetree, Linux Kernel Mailing List, Matthias Kaehlcke, Linus Walleij, Jonathan Cameron, smohanad, kgunda, aghayal, Jonathan Cameron, Hartmut Knaack, Lars-Peter Clausen, Peter Meerwald-Stadler, linux-arm-msm, linux-iio, linux-arm-msm-owner On Mon, Apr 27, 2020 at 3:56 PM Jishnu Prakash <jprakash@codeaurora.org> wrote: > On 4/17/2020 3:51 PM, Andy Shevchenko wrote: > On Thu, Apr 16, 2020 at 1:48 AM Jishnu Prakash <jprakash@codeaurora.org> wrote: Stop using HTML. It breaks badly the reply and discussion. ... > +static const struct adc5_data adc7_data_pmic; > > Global variable? Hmm... > > adc7_data_pmic is referenced twice before its actual definition (which was added along with corresponding adc5_data struct for PMIC5 ADC), so I have given the initial declaration here. Maybe you can realize how to avoid global variable at all? ... > + buf[1] &= 0xff & ~ADC5_USR_FAST_AVG_CTL_SAMPLES_MASK; > > What the point of 0xff & part? > > This was something you suggested in my first post: > > > + buf[1] &= (u8) ~ADC5_USR_FAST_AVG_CTL_SAMPLES_MASK; > > Use '0xFF ^ _MASK' instead of casting. > > ... > > > + buf[3] &= (u8) ~ADC5_USR_HW_SETTLE_DELAY_MASK; > > Ditto. > > I think "0xff &" works as intended here in place of casting to (u8)... Does it work without casting? (Note, I suggested slightly different expression) I.o.w. what the problem casting solves? > + buf[1] |= prop->avg_samples; > + > + /* Select ADC channel */ > + buf[2] = prop->channel; > + > + /* Select HW settle delay for channel */ > + buf[3] &= 0xff & ~ADC5_USR_HW_SETTLE_DELAY_MASK; > > Ditto. > > + buf[3] |= prop->hw_settle_time; -- With Best Regards, Andy Shevchenko ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH V2 3/3] iio: adc: Add support for PMIC7 ADC 2020-04-27 13:28 ` Andy Shevchenko @ 2020-05-13 9:20 ` Jishnu Prakash 0 siblings, 0 replies; 15+ messages in thread From: Jishnu Prakash @ 2020-05-13 9:20 UTC (permalink / raw) To: Andy Shevchenko Cc: agross, Bjorn Andersson, devicetree, Linux Kernel Mailing List, Matthias Kaehlcke, Linus Walleij, Jonathan Cameron, smohanad, kgunda, aghayal, Jonathan Cameron, Hartmut Knaack, Lars-Peter Clausen, Peter Meerwald-Stadler, linux-arm-msm, linux-iio, linux-arm-msm-owner Hi Andy, On 4/27/2020 6:58 PM, Andy Shevchenko wrote: > On Mon, Apr 27, 2020 at 3:56 PM Jishnu Prakash <jprakash@codeaurora.org> wrote: >> On 4/17/2020 3:51 PM, Andy Shevchenko wrote: >> On Thu, Apr 16, 2020 at 1:48 AM Jishnu Prakash <jprakash@codeaurora.org> wrote: > Stop using HTML. It breaks badly the reply and discussion. > > ... > >> +static const struct adc5_data adc7_data_pmic; >> >> Global variable? Hmm... >> >> adc7_data_pmic is referenced twice before its actual definition (which was added along with corresponding adc5_data struct for PMIC5 ADC), so I have given the initial declaration here. > Maybe you can realize how to avoid global variable at all? There is a way to remove this, I'll make this change with some other changes in the fifth patch of my latest post. > > ... > >> + buf[1] &= 0xff & ~ADC5_USR_FAST_AVG_CTL_SAMPLES_MASK; >> >> What the point of 0xff & part? >> >> This was something you suggested in my first post: >> >>> + buf[1] &= (u8) ~ADC5_USR_FAST_AVG_CTL_SAMPLES_MASK; >> Use '0xFF ^ _MASK' instead of casting. >> >> ... >> >>> + buf[3] &= (u8) ~ADC5_USR_HW_SETTLE_DELAY_MASK; >> Ditto. >> >> I think "0xff &" works as intended here in place of casting to (u8)... > Does it work without casting? (Note, I suggested slightly different expression) > I.o.w. what the problem casting solves? I checked this part again. It looks like casting is not strictly required here, I'll remove it in my latest post. > >> + buf[1] |= prop->avg_samples; >> + >> + /* Select ADC channel */ >> + buf[2] = prop->channel; >> + >> + /* Select HW settle delay for channel */ >> + buf[3] &= 0xff & ~ADC5_USR_HW_SETTLE_DELAY_MASK; >> >> Ditto. >> >> + buf[3] |= prop->hw_settle_time; > ^ permalink raw reply [flat|nested] 15+ messages in thread
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2020-04-15 9:17 [PATCH V2 0/3] iio: adc: Add support for QCOM SPMI PMIC7 ADC Jishnu Prakash
2020-04-15 9:17 ` [PATCH V2 1/3] iio: adc: Convert the QCOM SPMI ADC bindings to .yaml format Jishnu Prakash
2020-04-16 20:42 ` Rob Herring
2020-04-27 12:53 ` Jishnu Prakash
2020-04-18 16:22 ` Jonathan Cameron
2020-04-27 12:53 ` Jishnu Prakash
2020-04-15 9:17 ` [PATCH V2 2/3] iio: adc: Add PMIC7 ADC bindings Jishnu Prakash
2020-04-18 16:18 ` Jonathan Cameron
2020-04-27 12:55 ` Jishnu Prakash
2020-04-20 22:02 ` Rob Herring
2020-04-27 12:54 ` Jishnu Prakash
2020-04-15 9:17 ` [PATCH V2 3/3] iio: adc: Add support for PMIC7 ADC Jishnu Prakash
2020-04-17 10:21 ` Andy Shevchenko
[not found] ` <68d9c770-b190-dd13-0869-fdae9fb1f16f@codeaurora.org>
2020-04-27 13:28 ` Andy Shevchenko
2020-05-13 9:20 ` Jishnu Prakash
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