[PATCH v4 0/4] Enable stmpe811 touch screen on stm32f429-disco board

[PATCH v4 0/4] Enable stmpe811 touch screen on stm32f429-disco board

[dillon.minfei]

From: dillon min <dillon.minfei@gmail.com>

This patchset is intend to enable stmpe811 touch screen on stm32f429-disco
board with three dts and one i2c driver changes.

has been validated by ts_print tool

Changes log:
V4: indroduce 'IIC_LAST_BYTE_POS' to compatible with xipkernel boot

V3: just add change log in [PATCH V3 3/4] below ---

V2: remove id, blocks, irq-trigger from stmpe811 dts

V1:
ARM: dts: stm32: add I2C3 support on STM32F429 SoC
ARM: dts: stm32: Add pin map for I2C3 controller on stm32f4
ARM: dts: stm32: enable stmpe811 on stm32429-disco board
i2c: stm32f4: Fix stmpe811 get xyz data timeout issue

dillon min (4):
  ARM: dts: stm32: add I2C3 support on STM32F429 SoC
  ARM: dts: stm32: Add pin map for I2C3 controller on stm32f4
  ARM: dts: stm32: enable stmpe811 on stm32429-disco board
  i2c: stm32f4: Fix stmpe811 get xyz data timeout issue

 arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 12 +++++++++
 arch/arm/boot/dts/stm32f429-disco.dts  | 47 ++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/stm32f429.dtsi       | 12 +++++++++
 drivers/i2c/busses/i2c-stm32f4.c       | 12 ++++++---
 4 files changed, 80 insertions(+), 3 deletions(-)

-- 
2.7.4

[PATCH v4 1/4] ARM: dts: stm32: add I2C3 support on STM32F429 SoC

[dillon.minfei]

From: dillon min <dillon.minfei@gmail.com>

This patch adds I2C3 instances of the STM32F429 SoC

Signed-off-by: dillon min <dillon.minfei@gmail.com>
---
 arch/arm/boot/dts/stm32f429.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index d7770699feb5..257b8431dece 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -402,6 +402,18 @@
 			status = "disabled";
 		};
 
+		i2c3: i2c@40005c00 {
+			compatible = "st,stm32f4-i2c";
+			reg = <0x40005c00 0x400>;
+			interrupts = <72>,
+				     <73>;
+			resets = <&rcc STM32F4_APB1_RESET(I2C3)>;
+			clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C3)>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		dac: dac@40007400 {
 			compatible = "st,stm32f4-dac-core";
 			reg = <0x40007400 0x400>;
-- 
2.7.4

[PATCH v4 2/4] ARM: dts: stm32: Add pin map for I2C3 controller on stm32f4

[dillon.minfei]

From: dillon min <dillon.minfei@gmail.com>

This patch adds the pin configuration for I2C3 controller on
stm32f4.

Signed-off-by: dillon min <dillon.minfei@gmail.com>
---
 arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
index 392fa143ce07..051f33627e15 100644
--- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
@@ -316,6 +316,18 @@
 				};
 			};
 
+			i2c3_pins: i2c3-0 {
+				pins {
+					pinmux = <STM32_PINMUX('C', 9, AF4)>,
+						/* I2C3_SDA */
+						 <STM32_PINMUX('A', 8, AF4)>;
+						/* I2C3_SCL */
+					bias-disable;
+					drive-open-drain;
+					slew-rate = <3>;
+				};
+			};
+
 			dcmi_pins: dcmi-0 {
 				pins {
 					pinmux = <STM32_PINMUX('A', 4, AF13)>, /* DCMI_HSYNC */
-- 
2.7.4

[PATCH v4 3/4] ARM: dts: stm32: enable stmpe811 on stm32429-disco board

[dillon.minfei]

From: dillon min <dillon.minfei@gmail.com>

Enable the stmpe811 touch screen on stm32429-disco board.

Signed-off-by: dillon min <dillon.minfei@gmail.com>
---
 arch/arm/boot/dts/stm32f429-disco.dts | 47 +++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts
index 30c0f6717871..fad1ec10efb6 100644
--- a/arch/arm/boot/dts/stm32f429-disco.dts
+++ b/arch/arm/boot/dts/stm32f429-disco.dts
@@ -49,6 +49,8 @@
 #include "stm32f429.dtsi"
 #include "stm32f429-pinctrl.dtsi"
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	model = "STMicroelectronics STM32F429i-DISCO board";
@@ -127,3 +129,48 @@
 	pinctrl-names = "default";
 	status = "okay";
 };
+
+&i2c3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c3_pins>;
+	clock-frequency = <100000>;
+	status = "okay";
+
+	stmpe811@41 {
+		compatible = "st,stmpe811";
+		reg = <0x41>;
+		interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
+		interrupt-parent = <&gpioa>;
+		/* 3.25 MHz ADC clock speed */
+		st,adc-freq = <1>;
+		/* 12-bit ADC */
+		st,mod-12b = <1>;
+		/* internal ADC reference */
+		st,ref-sel = <0>;
+		/* ADC converstion time: 80 clocks */
+		st,sample-time = <4>;
+
+		stmpe_touchscreen {
+			compatible = "st,stmpe-ts";
+			/* 8 sample average control */
+			st,ave-ctrl = <3>;
+			/* 7 length fractional part in z */
+			st,fraction-z = <7>;
+			/*
+			 * 50 mA typical 80 mA max touchscreen drivers
+			 * current limit value
+			 */
+			st,i-drive = <1>;
+			/* 1 ms panel driver settling time */
+			st,settling = <3>;
+			/* 5 ms touch detect interrupt delay */
+			st,touch-det-delay = <5>;
+		};
+
+		stmpe_adc {
+			compatible = "st,stmpe-adc";
+			/* forbid to use ADC channels 3-0 (touch) */
+			st,norequest-mask = <0x0F>;
+		};
+	};
+};
-- 
2.7.4

[PATCH v4 4/4] i2c: stm32f4: Fix stmpe811 get xyz data timeout issue

[dillon.minfei]

From: dillon min <dillon.minfei@gmail.com>

as stm32f429's internal flash is 2Mbytes and compiled kernel
image bigger than 2Mbytes, so we have to load kernel image
to sdram on stm32f429-disco board which has 8Mbytes sdram space.

based on above context, as you knows kernel running on external
sdram is more slower than internal flash. besides, we need read 4
bytes to get touch screen xyz(x, y, pressure) coordinate data in
stmpe811 interrupt.

so, in stm32f4_i2c_handle_rx_done, as i2c read slower than running
in xip mode, have to adjust 'STOP/START bit set position' from last
two bytes to last one bytes. else, will get i2c timeout in reading
touch screen coordinate.

to not take side effect, introduce IIC_LAST_BYTE_POS to support xip
kernel or has mmu platform.

Signed-off-by: dillon min <dillon.minfei@gmail.com>
---

V4: indroduce 'IIC_LAST_BYTE_POS' to compatible with xipkernel boot

 drivers/i2c/busses/i2c-stm32f4.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/busses/i2c-stm32f4.c b/drivers/i2c/busses/i2c-stm32f4.c
index d6a69dfcac3f..97cf42ae7fa0 100644
--- a/drivers/i2c/busses/i2c-stm32f4.c
+++ b/drivers/i2c/busses/i2c-stm32f4.c
@@ -93,6 +93,12 @@
 #define STM32F4_I2C_MAX_FREQ		46U
 #define HZ_TO_MHZ			1000000
 
+#if !defined(CONFIG_MMU) && !defined(CONFIG_XIP_KERNEL)
+#define IIC_LAST_BYTE_POS 1
+#else
+#define IIC_LAST_BYTE_POS 2
+#endif
+
 /**
  * struct stm32f4_i2c_msg - client specific data
  * @addr: 8-bit slave addr, including r/w bit
@@ -439,7 +445,7 @@ static void stm32f4_i2c_handle_rx_done(struct stm32f4_i2c_dev *i2c_dev)
 	int i;
 
 	switch (msg->count) {
-	case 2:
+	case IIC_LAST_BYTE_POS:
 		/*
 		 * In order to correctly send the Stop or Repeated Start
 		 * condition on the I2C bus, the STOP/START bit has to be set
@@ -454,7 +460,7 @@ static void stm32f4_i2c_handle_rx_done(struct stm32f4_i2c_dev *i2c_dev)
 		else
 			stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START);
 
-		for (i = 2; i > 0; i--)
+		for (i = IIC_LAST_BYTE_POS; i > 0; i--)
 			stm32f4_i2c_read_msg(i2c_dev);
 
 		reg = i2c_dev->base + STM32F4_I2C_CR2;
@@ -463,7 +469,7 @@ static void stm32f4_i2c_handle_rx_done(struct stm32f4_i2c_dev *i2c_dev)
 
 		complete(&i2c_dev->complete);
 		break;
-	case 3:
+	case (IIC_LAST_BYTE_POS+1):
 		/*
 		 * In order to correctly generate the NACK pulse after the last
 		 * received data byte, we have to enable NACK before reading N-2
-- 
2.7.4

Re: [PATCH v4 0/4] Enable stmpe811 touch screen on stm32f429-disco board

[Alexandre Torgue]

Hi Dillon

On 6/9/20 3:26 PM, dillon.minfei@gmail.com wrote:
> From: dillon min <dillon.minfei@gmail.com>
> 
> This patchset is intend to enable stmpe811 touch screen on stm32f429-disco
> board with three dts and one i2c driver changes.
> 
> has been validated by ts_print tool
> 
> Changes log:
> V4: indroduce 'IIC_LAST_BYTE_POS' to compatible with xipkernel boot
> 
> V3: just add change log in [PATCH V3 3/4] below ---
> 
> V2: remove id, blocks, irq-trigger from stmpe811 dts
> 
> V1:
> ARM: dts: stm32: add I2C3 support on STM32F429 SoC
> ARM: dts: stm32: Add pin map for I2C3 controller on stm32f4
> ARM: dts: stm32: enable stmpe811 on stm32429-disco board
> i2c: stm32f4: Fix stmpe811 get xyz data timeout issue
> 
> dillon min (4):
>    ARM: dts: stm32: add I2C3 support on STM32F429 SoC
>    ARM: dts: stm32: Add pin map for I2C3 controller on stm32f4
>    ARM: dts: stm32: enable stmpe811 on stm32429-disco board
>    i2c: stm32f4: Fix stmpe811 get xyz data timeout issue
> 
>   arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 12 +++++++++
>   arch/arm/boot/dts/stm32f429-disco.dts  | 47 ++++++++++++++++++++++++++++++++++
>   arch/arm/boot/dts/stm32f429.dtsi       | 12 +++++++++
>   drivers/i2c/busses/i2c-stm32f4.c       | 12 ++++++---
>   4 files changed, 80 insertions(+), 3 deletions(-)
> 

DT patches applied on stm32-next. I changed node ordering in patch 3.

Thanks
Alex

Re: [PATCH v4 0/4] Enable stmpe811 touch screen on stm32f429-disco board

[dillon min]

On Mon, Jun 15, 2020 at 5:08 PM Alexandre Torgue
<alexandre.torgue@st.com> wrote:
>
> Hi Dillon
>
> On 6/9/20 3:26 PM, dillon.minfei@gmail.com wrote:
> > From: dillon min <dillon.minfei@gmail.com>
> >
> > This patchset is intend to enable stmpe811 touch screen on stm32f429-disco
> > board with three dts and one i2c driver changes.
> >
> > has been validated by ts_print tool
> >
> > Changes log:
> > V4: indroduce 'IIC_LAST_BYTE_POS' to compatible with xipkernel boot
> >
> > V3: just add change log in [PATCH V3 3/4] below ---
> >
> > V2: remove id, blocks, irq-trigger from stmpe811 dts
> >
> > V1:
> > ARM: dts: stm32: add I2C3 support on STM32F429 SoC
> > ARM: dts: stm32: Add pin map for I2C3 controller on stm32f4
> > ARM: dts: stm32: enable stmpe811 on stm32429-disco board
> > i2c: stm32f4: Fix stmpe811 get xyz data timeout issue
> >
> > dillon min (4):
> >    ARM: dts: stm32: add I2C3 support on STM32F429 SoC
> >    ARM: dts: stm32: Add pin map for I2C3 controller on stm32f4
> >    ARM: dts: stm32: enable stmpe811 on stm32429-disco board
> >    i2c: stm32f4: Fix stmpe811 get xyz data timeout issue
> >
> >   arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 12 +++++++++
> >   arch/arm/boot/dts/stm32f429-disco.dts  | 47 ++++++++++++++++++++++++++++++++++
> >   arch/arm/boot/dts/stm32f429.dtsi       | 12 +++++++++
> >   drivers/i2c/busses/i2c-stm32f4.c       | 12 ++++++---
> >   4 files changed, 80 insertions(+), 3 deletions(-)
> >
>
> DT patches applied on stm32-next. I changed node ordering in patch 3.
Okay, thanks.

Regards,
Dillon,
>
> Thanks
> Alex

Re: [PATCH v4 4/4] i2c: stm32f4: Fix stmpe811 get xyz data timeout issue

[dillon min]

Hi All,

Just a gentle ping.

Regards.

On Tue, Jun 9, 2020 at 9:27 PM <dillon.minfei@gmail.com> wrote:
>
> From: dillon min <dillon.minfei@gmail.com>
>
> as stm32f429's internal flash is 2Mbytes and compiled kernel
> image bigger than 2Mbytes, so we have to load kernel image
> to sdram on stm32f429-disco board which has 8Mbytes sdram space.
>
> based on above context, as you knows kernel running on external
> sdram is more slower than internal flash. besides, we need read 4
> bytes to get touch screen xyz(x, y, pressure) coordinate data in
> stmpe811 interrupt.
>
> so, in stm32f4_i2c_handle_rx_done, as i2c read slower than running
> in xip mode, have to adjust 'STOP/START bit set position' from last
> two bytes to last one bytes. else, will get i2c timeout in reading
> touch screen coordinate.
>
> to not take side effect, introduce IIC_LAST_BYTE_POS to support xip
> kernel or has mmu platform.
>
> Signed-off-by: dillon min <dillon.minfei@gmail.com>
> ---
>
> V4: indroduce 'IIC_LAST_BYTE_POS' to compatible with xipkernel boot
>
>  drivers/i2c/busses/i2c-stm32f4.c | 12 +++++++++---
>  1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-stm32f4.c b/drivers/i2c/busses/i2c-stm32f4.c
> index d6a69dfcac3f..97cf42ae7fa0 100644
> --- a/drivers/i2c/busses/i2c-stm32f4.c
> +++ b/drivers/i2c/busses/i2c-stm32f4.c
> @@ -93,6 +93,12 @@
>  #define STM32F4_I2C_MAX_FREQ           46U
>  #define HZ_TO_MHZ                      1000000
>
> +#if !defined(CONFIG_MMU) && !defined(CONFIG_XIP_KERNEL)
> +#define IIC_LAST_BYTE_POS 1
> +#else
> +#define IIC_LAST_BYTE_POS 2
> +#endif
> +
>  /**
>   * struct stm32f4_i2c_msg - client specific data
>   * @addr: 8-bit slave addr, including r/w bit
> @@ -439,7 +445,7 @@ static void stm32f4_i2c_handle_rx_done(struct stm32f4_i2c_dev *i2c_dev)
>         int i;
>
>         switch (msg->count) {
> -       case 2:
> +       case IIC_LAST_BYTE_POS:
>                 /*
>                  * In order to correctly send the Stop or Repeated Start
>                  * condition on the I2C bus, the STOP/START bit has to be set
> @@ -454,7 +460,7 @@ static void stm32f4_i2c_handle_rx_done(struct stm32f4_i2c_dev *i2c_dev)
>                 else
>                         stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START);
>
> -               for (i = 2; i > 0; i--)
> +               for (i = IIC_LAST_BYTE_POS; i > 0; i--)
>                         stm32f4_i2c_read_msg(i2c_dev);
>
>                 reg = i2c_dev->base + STM32F4_I2C_CR2;
> @@ -463,7 +469,7 @@ static void stm32f4_i2c_handle_rx_done(struct stm32f4_i2c_dev *i2c_dev)
>
>                 complete(&i2c_dev->complete);
>                 break;
> -       case 3:
> +       case (IIC_LAST_BYTE_POS+1):
>                 /*
>                  * In order to correctly generate the NACK pulse after the last
>                  * received data byte, we have to enable NACK before reading N-2
> --
> 2.7.4
>

Re: [PATCH v4 4/4] i2c: stm32f4: Fix stmpe811 get xyz data timeout issue

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 3264 bytes --]

On Mon, Mar 15, 2021 at 08:43:54PM +0800, dillon min wrote:
> Hi All,
> 
> Just a gentle ping.

Pierre-Yves?

> 
> Regards.
> 
> On Tue, Jun 9, 2020 at 9:27 PM <dillon.minfei@gmail.com> wrote:
> >
> > From: dillon min <dillon.minfei@gmail.com>
> >
> > as stm32f429's internal flash is 2Mbytes and compiled kernel
> > image bigger than 2Mbytes, so we have to load kernel image
> > to sdram on stm32f429-disco board which has 8Mbytes sdram space.
> >
> > based on above context, as you knows kernel running on external
> > sdram is more slower than internal flash. besides, we need read 4
> > bytes to get touch screen xyz(x, y, pressure) coordinate data in
> > stmpe811 interrupt.
> >
> > so, in stm32f4_i2c_handle_rx_done, as i2c read slower than running
> > in xip mode, have to adjust 'STOP/START bit set position' from last
> > two bytes to last one bytes. else, will get i2c timeout in reading
> > touch screen coordinate.
> >
> > to not take side effect, introduce IIC_LAST_BYTE_POS to support xip
> > kernel or has mmu platform.
> >
> > Signed-off-by: dillon min <dillon.minfei@gmail.com>
> > ---
> >
> > V4: indroduce 'IIC_LAST_BYTE_POS' to compatible with xipkernel boot
> >
> >  drivers/i2c/busses/i2c-stm32f4.c | 12 +++++++++---
> >  1 file changed, 9 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/i2c/busses/i2c-stm32f4.c b/drivers/i2c/busses/i2c-stm32f4.c
> > index d6a69dfcac3f..97cf42ae7fa0 100644
> > --- a/drivers/i2c/busses/i2c-stm32f4.c
> > +++ b/drivers/i2c/busses/i2c-stm32f4.c
> > @@ -93,6 +93,12 @@
> >  #define STM32F4_I2C_MAX_FREQ           46U
> >  #define HZ_TO_MHZ                      1000000
> >
> > +#if !defined(CONFIG_MMU) && !defined(CONFIG_XIP_KERNEL)
> > +#define IIC_LAST_BYTE_POS 1
> > +#else
> > +#define IIC_LAST_BYTE_POS 2
> > +#endif
> > +
> >  /**
> >   * struct stm32f4_i2c_msg - client specific data
> >   * @addr: 8-bit slave addr, including r/w bit
> > @@ -439,7 +445,7 @@ static void stm32f4_i2c_handle_rx_done(struct stm32f4_i2c_dev *i2c_dev)
> >         int i;
> >
> >         switch (msg->count) {
> > -       case 2:
> > +       case IIC_LAST_BYTE_POS:
> >                 /*
> >                  * In order to correctly send the Stop or Repeated Start
> >                  * condition on the I2C bus, the STOP/START bit has to be set
> > @@ -454,7 +460,7 @@ static void stm32f4_i2c_handle_rx_done(struct stm32f4_i2c_dev *i2c_dev)
> >                 else
> >                         stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START);
> >
> > -               for (i = 2; i > 0; i--)
> > +               for (i = IIC_LAST_BYTE_POS; i > 0; i--)
> >                         stm32f4_i2c_read_msg(i2c_dev);
> >
> >                 reg = i2c_dev->base + STM32F4_I2C_CR2;
> > @@ -463,7 +469,7 @@ static void stm32f4_i2c_handle_rx_done(struct stm32f4_i2c_dev *i2c_dev)
> >
> >                 complete(&i2c_dev->complete);
> >                 break;
> > -       case 3:
> > +       case (IIC_LAST_BYTE_POS+1):
> >                 /*
> >                  * In order to correctly generate the NACK pulse after the last
> >                  * received data byte, we have to enable NACK before reading N-2
> > --
> > 2.7.4
> >

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Re: [PATCH v4 4/4] i2c: stm32f4: Fix stmpe811 get xyz data timeout issue

[dillon min]

Hi Pierre-Yves, Alain

Could you help to take a look?
i really appreciate it.

Thanks,

Best Regards
Dillon

On Mon, Mar 15, 2021 at 9:00 PM Wolfram Sang <wsa@kernel.org> wrote:
>
> On Mon, Mar 15, 2021 at 08:43:54PM +0800, dillon min wrote:
> > Hi All,
> >
> > Just a gentle ping.
>
> Pierre-Yves?
>
> >
> > Regards.
> >
> > On Tue, Jun 9, 2020 at 9:27 PM <dillon.minfei@gmail.com> wrote:
> > >
> > > From: dillon min <dillon.minfei@gmail.com>
> > >
> > > as stm32f429's internal flash is 2Mbytes and compiled kernel
> > > image bigger than 2Mbytes, so we have to load kernel image
> > > to sdram on stm32f429-disco board which has 8Mbytes sdram space.
> > >
> > > based on above context, as you knows kernel running on external
> > > sdram is more slower than internal flash. besides, we need read 4
> > > bytes to get touch screen xyz(x, y, pressure) coordinate data in
> > > stmpe811 interrupt.
> > >
> > > so, in stm32f4_i2c_handle_rx_done, as i2c read slower than running
> > > in xip mode, have to adjust 'STOP/START bit set position' from last
> > > two bytes to last one bytes. else, will get i2c timeout in reading
> > > touch screen coordinate.
> > >
> > > to not take side effect, introduce IIC_LAST_BYTE_POS to support xip
> > > kernel or has mmu platform.
> > >
> > > Signed-off-by: dillon min <dillon.minfei@gmail.com>
> > > ---
> > >
> > > V4: indroduce 'IIC_LAST_BYTE_POS' to compatible with xipkernel boot
> > >
> > >  drivers/i2c/busses/i2c-stm32f4.c | 12 +++++++++---
> > >  1 file changed, 9 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/i2c/busses/i2c-stm32f4.c b/drivers/i2c/busses/i2c-stm32f4.c
> > > index d6a69dfcac3f..97cf42ae7fa0 100644
> > > --- a/drivers/i2c/busses/i2c-stm32f4.c
> > > +++ b/drivers/i2c/busses/i2c-stm32f4.c
> > > @@ -93,6 +93,12 @@
> > >  #define STM32F4_I2C_MAX_FREQ           46U
> > >  #define HZ_TO_MHZ                      1000000
> > >
> > > +#if !defined(CONFIG_MMU) && !defined(CONFIG_XIP_KERNEL)
> > > +#define IIC_LAST_BYTE_POS 1
> > > +#else
> > > +#define IIC_LAST_BYTE_POS 2
> > > +#endif
> > > +
> > >  /**
> > >   * struct stm32f4_i2c_msg - client specific data
> > >   * @addr: 8-bit slave addr, including r/w bit
> > > @@ -439,7 +445,7 @@ static void stm32f4_i2c_handle_rx_done(struct stm32f4_i2c_dev *i2c_dev)
> > >         int i;
> > >
> > >         switch (msg->count) {
> > > -       case 2:
> > > +       case IIC_LAST_BYTE_POS:
> > >                 /*
> > >                  * In order to correctly send the Stop or Repeated Start
> > >                  * condition on the I2C bus, the STOP/START bit has to be set
> > > @@ -454,7 +460,7 @@ static void stm32f4_i2c_handle_rx_done(struct stm32f4_i2c_dev *i2c_dev)
> > >                 else
> > >                         stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START);
> > >
> > > -               for (i = 2; i > 0; i--)
> > > +               for (i = IIC_LAST_BYTE_POS; i > 0; i--)
> > >                         stm32f4_i2c_read_msg(i2c_dev);
> > >
> > >                 reg = i2c_dev->base + STM32F4_I2C_CR2;
> > > @@ -463,7 +469,7 @@ static void stm32f4_i2c_handle_rx_done(struct stm32f4_i2c_dev *i2c_dev)
> > >
> > >                 complete(&i2c_dev->complete);
> > >                 break;
> > > -       case 3:
> > > +       case (IIC_LAST_BYTE_POS+1):
> > >                 /*
> > >                  * In order to correctly generate the NACK pulse after the last
> > >                  * received data byte, we have to enable NACK before reading N-2
> > > --
> > > 2.7.4
> > >

Re: [Linux-stm32] [PATCH v4 4/4] i2c: stm32f4: Fix stmpe811 get xyz data timeout issue

[Patrice CHOTARD]

Hi Dillon

In order to test this patch, it's tricky to make a recent kernel running 
on stm32f429-disco as this board embeds only 8MB of SDRAM and 2MB of flash.

Can you indicates us which kernel version you are using and also the kernel config please ?

Thanks

Patrice

On 5/7/21 4:54 AM, dillon min wrote:
> Hi Pierre-Yves, Alain
> 
> Could you help to take a look?
> i really appreciate it.
> 
> Thanks,
> 
> Best Regards
> Dillon
> 
> On Mon, Mar 15, 2021 at 9:00 PM Wolfram Sang <wsa@kernel.org> wrote:
>>
>> On Mon, Mar 15, 2021 at 08:43:54PM +0800, dillon min wrote:
>>> Hi All,
>>>
>>> Just a gentle ping.
>>
>> Pierre-Yves?
>>
>>>
>>> Regards.
>>>
>>> On Tue, Jun 9, 2020 at 9:27 PM <dillon.minfei@gmail.com> wrote:
>>>>
>>>> From: dillon min <dillon.minfei@gmail.com>
>>>>
>>>> as stm32f429's internal flash is 2Mbytes and compiled kernel
>>>> image bigger than 2Mbytes, so we have to load kernel image
>>>> to sdram on stm32f429-disco board which has 8Mbytes sdram space.
>>>>
>>>> based on above context, as you knows kernel running on external
>>>> sdram is more slower than internal flash. besides, we need read 4
>>>> bytes to get touch screen xyz(x, y, pressure) coordinate data in
>>>> stmpe811 interrupt.
>>>>
>>>> so, in stm32f4_i2c_handle_rx_done, as i2c read slower than running
>>>> in xip mode, have to adjust 'STOP/START bit set position' from last
>>>> two bytes to last one bytes. else, will get i2c timeout in reading
>>>> touch screen coordinate.
>>>>
>>>> to not take side effect, introduce IIC_LAST_BYTE_POS to support xip
>>>> kernel or has mmu platform.
>>>>
>>>> Signed-off-by: dillon min <dillon.minfei@gmail.com>
>>>> ---
>>>>
>>>> V4: indroduce 'IIC_LAST_BYTE_POS' to compatible with xipkernel boot
>>>>
>>>>  drivers/i2c/busses/i2c-stm32f4.c | 12 +++++++++---
>>>>  1 file changed, 9 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/drivers/i2c/busses/i2c-stm32f4.c b/drivers/i2c/busses/i2c-stm32f4.c
>>>> index d6a69dfcac3f..97cf42ae7fa0 100644
>>>> --- a/drivers/i2c/busses/i2c-stm32f4.c
>>>> +++ b/drivers/i2c/busses/i2c-stm32f4.c
>>>> @@ -93,6 +93,12 @@
>>>>  #define STM32F4_I2C_MAX_FREQ           46U
>>>>  #define HZ_TO_MHZ                      1000000
>>>>
>>>> +#if !defined(CONFIG_MMU) && !defined(CONFIG_XIP_KERNEL)
>>>> +#define IIC_LAST_BYTE_POS 1
>>>> +#else
>>>> +#define IIC_LAST_BYTE_POS 2
>>>> +#endif
>>>> +
>>>>  /**
>>>>   * struct stm32f4_i2c_msg - client specific data
>>>>   * @addr: 8-bit slave addr, including r/w bit
>>>> @@ -439,7 +445,7 @@ static void stm32f4_i2c_handle_rx_done(struct stm32f4_i2c_dev *i2c_dev)
>>>>         int i;
>>>>
>>>>         switch (msg->count) {
>>>> -       case 2:
>>>> +       case IIC_LAST_BYTE_POS:
>>>>                 /*
>>>>                  * In order to correctly send the Stop or Repeated Start
>>>>                  * condition on the I2C bus, the STOP/START bit has to be set
>>>> @@ -454,7 +460,7 @@ static void stm32f4_i2c_handle_rx_done(struct stm32f4_i2c_dev *i2c_dev)
>>>>                 else
>>>>                         stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START);
>>>>
>>>> -               for (i = 2; i > 0; i--)
>>>> +               for (i = IIC_LAST_BYTE_POS; i > 0; i--)
>>>>                         stm32f4_i2c_read_msg(i2c_dev);
>>>>
>>>>                 reg = i2c_dev->base + STM32F4_I2C_CR2;
>>>> @@ -463,7 +469,7 @@ static void stm32f4_i2c_handle_rx_done(struct stm32f4_i2c_dev *i2c_dev)
>>>>
>>>>                 complete(&i2c_dev->complete);
>>>>                 break;
>>>> -       case 3:
>>>> +       case (IIC_LAST_BYTE_POS+1):
>>>>                 /*
>>>>                  * In order to correctly generate the NACK pulse after the last
>>>>                  * received data byte, we have to enable NACK before reading N-2
>>>> --
>>>> 2.7.4
>>>>
> _______________________________________________
> Linux-stm32 mailing list
> Linux-stm32@st-md-mailman.stormreply.com
> https://st-md-mailman.stormreply.com/mailman/listinfo/linux-stm32
> 

Re: [Linux-stm32] [PATCH v4 4/4] i2c: stm32f4: Fix stmpe811 get xyz data timeout issue

[dillon min]

Hi Patrice

Thanks for the reply.

On Fri, May 7, 2021 at 8:29 PM Patrice CHOTARD
<patrice.chotard@foss.st.com> wrote:
>
> Hi Dillon
>
> In order to test this patch, it's tricky to make a recent kernel running
> on stm32f429-disco as this board embeds only 8MB of SDRAM and 2MB of flash.
>
> Can you indicates us which kernel version you are using and also the kernel config please ?

Since this patch was submitted in last year, might it be 5.0?  not for sure
Anyway, I will resubmit it in the recent kernel version with the kernel config
and a detailed test step for you.

Thanks for your time.

>
> Thanks
>
> Patrice
>
> On 5/7/21 4:54 AM, dillon min wrote:
> > Hi Pierre-Yves, Alain
> >
> > Could you help to take a look?
> > i really appreciate it.
> >
> > Thanks,
> >
> > Best Regards
> > Dillon
> >
> > On Mon, Mar 15, 2021 at 9:00 PM Wolfram Sang <wsa@kernel.org> wrote:
> >>
> >> On Mon, Mar 15, 2021 at 08:43:54PM +0800, dillon min wrote:
> >>> Hi All,
> >>>
> >>> Just a gentle ping.
> >>
> >> Pierre-Yves?
> >>
> >>>
> >>> Regards.
> >>>
> >>> On Tue, Jun 9, 2020 at 9:27 PM <dillon.minfei@gmail.com> wrote:
> >>>>
> >>>> From: dillon min <dillon.minfei@gmail.com>
> >>>>
> >>>> as stm32f429's internal flash is 2Mbytes and compiled kernel
> >>>> image bigger than 2Mbytes, so we have to load kernel image
> >>>> to sdram on stm32f429-disco board which has 8Mbytes sdram space.
> >>>>
> >>>> based on above context, as you knows kernel running on external
> >>>> sdram is more slower than internal flash. besides, we need read 4
> >>>> bytes to get touch screen xyz(x, y, pressure) coordinate data in
> >>>> stmpe811 interrupt.
> >>>>
> >>>> so, in stm32f4_i2c_handle_rx_done, as i2c read slower than running
> >>>> in xip mode, have to adjust 'STOP/START bit set position' from last
> >>>> two bytes to last one bytes. else, will get i2c timeout in reading
> >>>> touch screen coordinate.
> >>>>
> >>>> to not take side effect, introduce IIC_LAST_BYTE_POS to support xip
> >>>> kernel or has mmu platform.
> >>>>
> >>>> Signed-off-by: dillon min <dillon.minfei@gmail.com>
> >>>> ---
> >>>>
> >>>> V4: indroduce 'IIC_LAST_BYTE_POS' to compatible with xipkernel boot
> >>>>
> >>>>  drivers/i2c/busses/i2c-stm32f4.c | 12 +++++++++---
> >>>>  1 file changed, 9 insertions(+), 3 deletions(-)
> >>>>
> >>>> diff --git a/drivers/i2c/busses/i2c-stm32f4.c b/drivers/i2c/busses/i2c-stm32f4.c
> >>>> index d6a69dfcac3f..97cf42ae7fa0 100644
> >>>> --- a/drivers/i2c/busses/i2c-stm32f4.c
> >>>> +++ b/drivers/i2c/busses/i2c-stm32f4.c
> >>>> @@ -93,6 +93,12 @@
> >>>>  #define STM32F4_I2C_MAX_FREQ           46U
> >>>>  #define HZ_TO_MHZ                      1000000
> >>>>
> >>>> +#if !defined(CONFIG_MMU) && !defined(CONFIG_XIP_KERNEL)
> >>>> +#define IIC_LAST_BYTE_POS 1
> >>>> +#else
> >>>> +#define IIC_LAST_BYTE_POS 2
> >>>> +#endif
> >>>> +
> >>>>  /**
> >>>>   * struct stm32f4_i2c_msg - client specific data
> >>>>   * @addr: 8-bit slave addr, including r/w bit
> >>>> @@ -439,7 +445,7 @@ static void stm32f4_i2c_handle_rx_done(struct stm32f4_i2c_dev *i2c_dev)
> >>>>         int i;
> >>>>
> >>>>         switch (msg->count) {
> >>>> -       case 2:
> >>>> +       case IIC_LAST_BYTE_POS:
> >>>>                 /*
> >>>>                  * In order to correctly send the Stop or Repeated Start
> >>>>                  * condition on the I2C bus, the STOP/START bit has to be set
> >>>> @@ -454,7 +460,7 @@ static void stm32f4_i2c_handle_rx_done(struct stm32f4_i2c_dev *i2c_dev)
> >>>>                 else
> >>>>                         stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START);
> >>>>
> >>>> -               for (i = 2; i > 0; i--)
> >>>> +               for (i = IIC_LAST_BYTE_POS; i > 0; i--)
> >>>>                         stm32f4_i2c_read_msg(i2c_dev);
> >>>>
> >>>>                 reg = i2c_dev->base + STM32F4_I2C_CR2;
> >>>> @@ -463,7 +469,7 @@ static void stm32f4_i2c_handle_rx_done(struct stm32f4_i2c_dev *i2c_dev)
> >>>>
> >>>>                 complete(&i2c_dev->complete);
> >>>>                 break;
> >>>> -       case 3:
> >>>> +       case (IIC_LAST_BYTE_POS+1):
> >>>>                 /*
> >>>>                  * In order to correctly generate the NACK pulse after the last
> >>>>                  * received data byte, we have to enable NACK before reading N-2
> >>>> --
> >>>> 2.7.4
> >>>>
> > _______________________________________________
> > Linux-stm32 mailing list
> > Linux-stm32@st-md-mailman.stormreply.com
> > https://st-md-mailman.stormreply.com/mailman/listinfo/linux-stm32
> >

---
Best regards
Dillon,