* [PATCH V4 0/2] Fix issues related to register access in IPQ NAND @ 2020-06-12 7:58 Sivaprakash Murugesan 2020-06-12 7:58 ` [PATCH V4 1/2] mtd: rawnand: qcom: avoid write to unavailable register Sivaprakash Murugesan 2020-06-12 7:58 ` [PATCH V4 2/2] mtd: rawnand: qcom: set BAM mode only if not set already Sivaprakash Murugesan 0 siblings, 2 replies; 6+ messages in thread From: Sivaprakash Murugesan @ 2020-06-12 7:58 UTC (permalink / raw) To: miquel.raynal, richard, vigneshr, peter.ujfalusi, sivaprak, boris.brezillon, linux-mtd, linux-kernel Patch 1: avoids register write to unavailable SFLASHC_BURST_CFG register Patch 2: set BAM mode only if not set by bootloader [V4] * Addressed more review comments from Miquel * Removed architt@codeaurora.org from the senders list as it is bouncing [V3] * Addressed review comments from Miquel [V2] * As per review comments from Miquèl split the original patch into two addressing independent issues. Sivaprakash Murugesan (2): mtd: rawnand: qcom: remove write to unavailable register mtd: rawnand: qcom: set BAM mode only if not set already drivers/mtd/nand/raw/qcom_nandc.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) -- 2.7.4 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH V4 1/2] mtd: rawnand: qcom: avoid write to unavailable register 2020-06-12 7:58 [PATCH V4 0/2] Fix issues related to register access in IPQ NAND Sivaprakash Murugesan @ 2020-06-12 7:58 ` Sivaprakash Murugesan 2020-06-15 8:49 ` Miquel Raynal 2020-06-15 8:59 ` Miquel Raynal 2020-06-12 7:58 ` [PATCH V4 2/2] mtd: rawnand: qcom: set BAM mode only if not set already Sivaprakash Murugesan 1 sibling, 2 replies; 6+ messages in thread From: Sivaprakash Murugesan @ 2020-06-12 7:58 UTC (permalink / raw) To: miquel.raynal, richard, vigneshr, peter.ujfalusi, sivaprak, boris.brezillon, linux-mtd, linux-kernel Cc: stable SFLASHC_BURST_CFG is only available on older ipq nand platforms, this register has been removed when the NAND controller is moved as part of qpic controller. Avoid writing this register on devices which are based on qpic NAND controller. Fixes: dce84760 (mtd: nand: qcom: Support for IPQ8074 QPIC NAND controller) Cc: stable@vger.kernel.org Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> --- drivers/mtd/nand/raw/qcom_nandc.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index f1daf33..78b5f21 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -459,11 +459,13 @@ struct qcom_nand_host { * among different NAND controllers. * @ecc_modes - ecc mode for NAND * @is_bam - whether NAND controller is using BAM + * @is_qpic - whether NAND CTRL is part of qpic IP * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset */ struct qcom_nandc_props { u32 ecc_modes; bool is_bam; + bool is_qpic; u32 dev_cmd_reg_start; }; @@ -2774,7 +2776,8 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc) u32 nand_ctrl; /* kill onenand */ - nandc_write(nandc, SFLASHC_BURST_CFG, 0); + if (!nandc->props->is_qpic) + nandc_write(nandc, SFLASHC_BURST_CFG, 0); nandc_write(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD), NAND_DEV_CMD_VLD_VAL); @@ -3035,12 +3038,14 @@ static const struct qcom_nandc_props ipq806x_nandc_props = { static const struct qcom_nandc_props ipq4019_nandc_props = { .ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT), .is_bam = true, + .is_qpic = true, .dev_cmd_reg_start = 0x0, }; static const struct qcom_nandc_props ipq8074_nandc_props = { .ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT), .is_bam = true, + .is_qpic = true, .dev_cmd_reg_start = 0x7000, }; -- 2.7.4 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH V4 1/2] mtd: rawnand: qcom: avoid write to unavailable register 2020-06-12 7:58 ` [PATCH V4 1/2] mtd: rawnand: qcom: avoid write to unavailable register Sivaprakash Murugesan @ 2020-06-15 8:49 ` Miquel Raynal 2020-06-15 8:59 ` Miquel Raynal 1 sibling, 0 replies; 6+ messages in thread From: Miquel Raynal @ 2020-06-15 8:49 UTC (permalink / raw) To: Sivaprakash Murugesan Cc: richard, vigneshr, peter.ujfalusi, boris.brezillon, linux-mtd, linux-kernel, stable Hi Sivaprakash, Sivaprakash Murugesan <sivaprak@codeaurora.org> wrote on Fri, 12 Jun 2020 13:28:15 +0530: > SFLASHC_BURST_CFG is only available on older ipq nand platforms, this > register has been removed when the NAND controller is moved as part of qpic > controller. > > Avoid writing this register on devices which are based on qpic NAND > controller. > > Fixes: dce84760 (mtd: nand: qcom: Support for IPQ8074 QPIC NAND controller) The Fixes line is not properly formed: the number of digest digits must be 12 and the title should be enclosed with "". I will fix when applying. Thanks, Miquèl ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH V4 1/2] mtd: rawnand: qcom: avoid write to unavailable register 2020-06-12 7:58 ` [PATCH V4 1/2] mtd: rawnand: qcom: avoid write to unavailable register Sivaprakash Murugesan 2020-06-15 8:49 ` Miquel Raynal @ 2020-06-15 8:59 ` Miquel Raynal 1 sibling, 0 replies; 6+ messages in thread From: Miquel Raynal @ 2020-06-15 8:59 UTC (permalink / raw) To: Sivaprakash Murugesan, miquel.raynal, richard, vigneshr, peter.ujfalusi, boris.brezillon, linux-mtd, linux-kernel Cc: stable On Fri, 2020-06-12 at 07:58:15 UTC, Sivaprakash Murugesan wrote: > SFLASHC_BURST_CFG is only available on older ipq nand platforms, this > register has been removed when the NAND controller is moved as part of qpic > controller. > > Avoid writing this register on devices which are based on qpic NAND > controller. > > Fixes: dce84760 (mtd: nand: qcom: Support for IPQ8074 QPIC NAND controller) > Cc: stable@vger.kernel.org > Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next, thanks. Miquel ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH V4 2/2] mtd: rawnand: qcom: set BAM mode only if not set already 2020-06-12 7:58 [PATCH V4 0/2] Fix issues related to register access in IPQ NAND Sivaprakash Murugesan 2020-06-12 7:58 ` [PATCH V4 1/2] mtd: rawnand: qcom: avoid write to unavailable register Sivaprakash Murugesan @ 2020-06-12 7:58 ` Sivaprakash Murugesan 2020-06-15 8:59 ` Miquel Raynal 1 sibling, 1 reply; 6+ messages in thread From: Sivaprakash Murugesan @ 2020-06-12 7:58 UTC (permalink / raw) To: miquel.raynal, richard, vigneshr, peter.ujfalusi, sivaprak, boris.brezillon, linux-mtd, linux-kernel BAM is DMA controller on QCOM ipq platforms, BAM mode on NAND driver is set by writing BAM_MODE_EN bit on NAND_CTRL register. NAND_CTRL is an operational register and in BAM mode operational registers are read only. So, before enabling BAM mode by writing the NAND_CTRL register, check if BAM mode was already enabled by the bootloader, and enable BAM mode only if it is not enabled already. Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> --- drivers/mtd/nand/raw/qcom_nandc.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index 78b5f21..a3ef428 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -2784,7 +2784,14 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc) /* enable ADM or BAM DMA */ if (nandc->props->is_bam) { nand_ctrl = nandc_read(nandc, NAND_CTRL); - nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN); + /* NAND_CTRL is an operational registers, and CPU + * access to operational registers are read only + * in BAM mode. So update the NAND_CTRL register + * only if it is not in BAM mode. In most cases BAM + * mode will be enabled in bootloader + */ + if (!(nand_ctrl | BAM_MODE_EN)) + nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN); } else { nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN); } -- 2.7.4 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH V4 2/2] mtd: rawnand: qcom: set BAM mode only if not set already 2020-06-12 7:58 ` [PATCH V4 2/2] mtd: rawnand: qcom: set BAM mode only if not set already Sivaprakash Murugesan @ 2020-06-15 8:59 ` Miquel Raynal 0 siblings, 0 replies; 6+ messages in thread From: Miquel Raynal @ 2020-06-15 8:59 UTC (permalink / raw) To: Sivaprakash Murugesan, miquel.raynal, richard, vigneshr, peter.ujfalusi, boris.brezillon, linux-mtd, linux-kernel On Fri, 2020-06-12 at 07:58:16 UTC, Sivaprakash Murugesan wrote: > BAM is DMA controller on QCOM ipq platforms, BAM mode on NAND driver > is set by writing BAM_MODE_EN bit on NAND_CTRL register. > > NAND_CTRL is an operational register and in BAM mode operational > registers are read only. > > So, before enabling BAM mode by writing the NAND_CTRL register, check > if BAM mode was already enabled by the bootloader, and enable BAM mode > only if it is not enabled already. > > Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next, thanks. Miquel ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-06-15 9:00 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-06-12 7:58 [PATCH V4 0/2] Fix issues related to register access in IPQ NAND Sivaprakash Murugesan 2020-06-12 7:58 ` [PATCH V4 1/2] mtd: rawnand: qcom: avoid write to unavailable register Sivaprakash Murugesan 2020-06-15 8:49 ` Miquel Raynal 2020-06-15 8:59 ` Miquel Raynal 2020-06-12 7:58 ` [PATCH V4 2/2] mtd: rawnand: qcom: set BAM mode only if not set already Sivaprakash Murugesan 2020-06-15 8:59 ` Miquel Raynal
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