From: chao hao <Chao.Hao@mediatek.com>
To: Matthias Brugger <matthias.bgg@gmail.com>
Cc: Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>,
<iommu@lists.linux-foundation.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>, <wsd_upstream@mediatek.com>,
Yong Wu <yong.wu@mediatek.com>, FY Yang <fy.yang@mediatek.com>,
Chao Hao <chao.hao@mediatek.com>
Subject: Re: [PATCH v4 7/7] iommu/mediatek: Add mt6779 basic support
Date: Thu, 18 Jun 2020 19:54:07 +0800 [thread overview]
Message-ID: <1592481247.12647.9.camel@mbjsdccf07> (raw)
In-Reply-To: <64f63ccc-92a4-191c-3566-de00c9e04ca2@gmail.com>
On Wed, 2020-06-17 at 11:33 +0200, Matthias Brugger wrote:
>
> On 17/06/2020 05:00, Chao Hao wrote:
> > 1. Start from mt6779, INVLDT_SEL move to offset=0x2c, so we add
> > REG_MMU_INV_SEL_GEN2 definition and mt6779 uses it.
> > 2. Change PROTECT_PA_ALIGN from 128 byte to 256 byte.
> > 3. For REG_MMU_CTRL_REG register, we only need to change bit[2:0],
> > others bits keep default value, ex: enable victim tlb.
> > 4. Add mt6779_data to support mm_iommu HW init.
> >
> > Change since v3:
> > 1. When setting MMU_CTRL_REG, we don't need to include mt8173.
> >
> > Cc: Yong Wu <yong.wu@mediatek.com>
> > Signed-off-by: Chao Hao <chao.hao@mediatek.com>
> > ---
> > drivers/iommu/mtk_iommu.c | 20 ++++++++++++++++++--
> > drivers/iommu/mtk_iommu.h | 1 +
> > 2 files changed, 19 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> > index c706bca6487e..def2e996683f 100644
> > --- a/drivers/iommu/mtk_iommu.c
> > +++ b/drivers/iommu/mtk_iommu.c
> > @@ -37,6 +37,11 @@
> > #define REG_MMU_INVLD_START_A 0x024
> > #define REG_MMU_INVLD_END_A 0x028
> >
> > +/* In latest Coda, MMU_INV_SEL's offset is changed to 0x02c.
> > + * So we named offset = 0x02c to "REG_MMU_INV_SEL_GEN2"
> > + * and offset = 0x038 to "REG_MMU_INV_SEL_GEN1".
> > + */
>
> Please delete the comment, this should be understandable from the git history
ok, thanks
>
> > +#define REG_MMU_INV_SEL_GEN2 0x02c
> > #define REG_MMU_INV_SEL_GEN1 0x038
> > #define F_INVLD_EN0 BIT(0)
> > #define F_INVLD_EN1 BIT(1)
> > @@ -98,7 +103,7 @@
> > #define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7)
> > #define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f)
> >
> > -#define MTK_PROTECT_PA_ALIGN 128
> > +#define MTK_PROTECT_PA_ALIGN 256
>
> Do we need 512 bytes for all gen2 IOMMUs?
> I'm not sure if we should add this in plat_data or if we should just bump up the
> value for all SoCs.
> In both cases this should be a separate patch.
>
From mt6779, MTK_PROTECT_PA_ALIGN is extend to 256 bytes and don't be
changed for a long time from our HW designer comment. The legacy iommu
also can use it, mabye it doesn't set it by platform.
> >
> > /*
> > * Get the local arbiter ID and the portid within the larb arbiter
> > @@ -543,11 +548,12 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
> > return ret;
> > }
> >
> > + regval = readl_relaxed(data->base + REG_MMU_CTRL_REG);
> > if (data->plat_data->m4u_plat == M4U_MT8173)
> > regval = F_MMU_PREFETCH_RT_REPLACE_MOD |
> > F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173;
> > else
> > - regval = F_MMU_TF_PROT_TO_PROGRAM_ADDR;
> > + regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR;
>
> Why do we change this, is it that the bootloader for mt6779 set some values in
> the register we have to keep? In this case I think we should update the regval
> accordingly.
For REG_MMU_CTRL_REG, bit[12] represents victim_tlb_en feature and
victim_tlb is enable defaultly(bit[12]=1),but if we use "regval =
F_MMU_TF_PROT_TO_PROGRAM_ADDR", victim_tlb will disable, it will drop
iommu performace for mt6779
>
> > writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
> >
> > regval = F_L2_MULIT_HIT_EN |
> > @@ -797,6 +803,15 @@ static const struct mtk_iommu_plat_data mt2712_data = {
> > .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}},
> > };
> >
> > +static const struct mtk_iommu_plat_data mt6779_data = {
> > + .m4u_plat = M4U_MT6779,
> > + .has_sub_comm = true,
> > + .has_wr_len = true,
> > + .has_misc_ctrl = true,
> > + .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
> > + .larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}},
> > +};
> > +
> > static const struct mtk_iommu_plat_data mt8173_data = {
> > .m4u_plat = M4U_MT8173,
> > .has_4gb_mode = true,
> > @@ -815,6 +830,7 @@ static const struct mtk_iommu_plat_data mt8183_data = {
> >
> > static const struct of_device_id mtk_iommu_of_ids[] = {
> > { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
> > + { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data},
> > { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
> > { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},
> > {}
> > diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
> > index 9971cedd72ea..fb79e710c8d9 100644
> > --- a/drivers/iommu/mtk_iommu.h
> > +++ b/drivers/iommu/mtk_iommu.h
> > @@ -31,6 +31,7 @@ struct mtk_iommu_suspend_reg {
> > enum mtk_iommu_plat {
> > M4U_MT2701,
> > M4U_MT2712,
> > + M4U_MT6779,
> > M4U_MT8173,
> > M4U_MT8183,
> > };
> >
next prev parent reply other threads:[~2020-06-18 11:54 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-17 3:00 [PATCH v4 00/07] MT6779 IOMMU SUPPORT Chao Hao
2020-06-17 3:00 ` [PATCH v4 1/7] dt-bindings: mediatek: Add bindings for MT6779 Chao Hao
2020-06-17 3:00 ` [PATCH v4 2/7] iommu/mediatek: Rename the register STANDARD_AXI_MODE(0x48) to MISC_CTRL Chao Hao
2020-06-17 9:04 ` Matthias Brugger
2020-06-17 3:00 ` [PATCH v4 3/7] iommu/mediatek: Set MISC_CTRL register Chao Hao
2020-06-17 9:34 ` Matthias Brugger
2020-06-18 11:49 ` chao hao
[not found] ` <1592618616.3951.12.camel@mhfsdcap03>
2020-06-24 6:39 ` chao hao
2020-06-17 3:00 ` [PATCH v4 4/7] iommu/mediatek: Move inv_sel_reg into the plat_data Chao Hao
2020-06-17 9:09 ` Matthias Brugger
2020-06-17 3:00 ` [PATCH v4 5/7] iommu/mediatek: Add sub_comm id in translation fault Chao Hao
2020-06-17 9:17 ` Matthias Brugger
2020-06-17 11:11 ` Yong Wu
2020-06-18 11:44 ` chao hao
2020-06-17 3:00 ` [PATCH v4 6/7] iommu/mediatek: Add REG_MMU_WR_LEN definition preparing for mt6779 Chao Hao
2020-06-17 9:22 ` Matthias Brugger
2020-06-19 10:56 ` chao hao
2020-06-21 11:01 ` Matthias Brugger
2020-06-24 6:36 ` chao hao
2020-06-17 3:00 ` [PATCH v4 7/7] iommu/mediatek: Add mt6779 basic support Chao Hao
2020-06-17 9:33 ` Matthias Brugger
2020-06-18 11:54 ` chao hao [this message]
2020-06-18 16:00 ` Matthias Brugger
2020-06-19 10:50 ` chao hao
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