From: Matthias Brugger <matthias.bgg@gmail.com>
To: Chao Hao <chao.hao@mediatek.com>, Joerg Roedel <joro@8bytes.org>,
Rob Herring <robh+dt@kernel.org>
Cc: iommu@lists.linux-foundation.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, wsd_upstream@mediatek.com,
Yong Wu <yong.wu@mediatek.com>, FY Yang <fy.yang@mediatek.com>
Subject: Re: [PATCH v4 6/7] iommu/mediatek: Add REG_MMU_WR_LEN definition preparing for mt6779
Date: Wed, 17 Jun 2020 11:22:09 +0200 [thread overview]
Message-ID: <9e2c52d6-a887-1977-8877-fbcd30cb4261@gmail.com> (raw)
In-Reply-To: <20200617030029.4082-7-chao.hao@mediatek.com>
On 17/06/2020 05:00, Chao Hao wrote:
> Some platforms(ex: mt6779) have a new register called by REG_MMU_WR_LEN
> to improve performance.
> This patch add this register definition.
Please be more specific what this register is about.
>
> Signed-off-by: Chao Hao <chao.hao@mediatek.com>
> ---
> drivers/iommu/mtk_iommu.c | 10 ++++++++++
> drivers/iommu/mtk_iommu.h | 2 ++
> 2 files changed, 12 insertions(+)
>
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index a687e8db0e51..c706bca6487e 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -46,6 +46,8 @@
> #define F_MMU_STANDARD_AXI_MODE_BIT (BIT(3) | BIT(19))
>
> #define REG_MMU_DCM_DIS 0x050
> +#define REG_MMU_WR_LEN 0x054
> +#define F_MMU_WR_THROT_DIS_BIT (BIT(5) | BIT(21))
>
> #define REG_MMU_CTRL_REG 0x110
> #define F_MMU_TF_PROT_TO_PROGRAM_ADDR (2 << 4)
> @@ -581,6 +583,12 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
> writel_relaxed(regval, data->base + REG_MMU_VLD_PA_RNG);
> }
> writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
> + if (data->plat_data->has_wr_len) {
> + /* write command throttling mode */
> + regval = readl_relaxed(data->base + REG_MMU_WR_LEN);
> + regval &= ~F_MMU_WR_THROT_DIS_BIT;
> + writel_relaxed(regval, data->base + REG_MMU_WR_LEN);
> + }
>
> if (data->plat_data->reset_axi) {
> /* The register is called STANDARD_AXI_MODE in this case */
> @@ -737,6 +745,7 @@ static int __maybe_unused mtk_iommu_suspend(struct device *dev)
> struct mtk_iommu_suspend_reg *reg = &data->reg;
> void __iomem *base = data->base;
>
> + reg->wr_len = readl_relaxed(base + REG_MMU_WR_LEN);
Can we read/write the register without any side effect although hardware has not
implemented it (!has_wr_len)?
> reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL);
> reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS);
> reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
> @@ -761,6 +770,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
> dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret);
> return ret;
> }
> + writel_relaxed(reg->wr_len, base + REG_MMU_WR_LEN);
> writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL);
> writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS);
> writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
> diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
> index d51ff99c2c71..9971cedd72ea 100644
> --- a/drivers/iommu/mtk_iommu.h
> +++ b/drivers/iommu/mtk_iommu.h
> @@ -25,6 +25,7 @@ struct mtk_iommu_suspend_reg {
> u32 int_main_control;
> u32 ivrp_paddr;
> u32 vld_pa_rng;
> + u32 wr_len;
> };
>
> enum mtk_iommu_plat {
> @@ -43,6 +44,7 @@ struct mtk_iommu_plat_data {
> bool has_misc_ctrl;
> bool has_sub_comm;
> bool has_vld_pa_rng;
> + bool has_wr_len;
Given the fact that we are adding more and more plat_data bool values, I think
it would make sense to use a u32 flags register and add the appropriate macro
definitions to set and check for a flag present.
Regards,
Matthias
> bool reset_axi;
> u32 inv_sel_reg;
> unsigned char larbid_remap[8][4];
>
next prev parent reply other threads:[~2020-06-17 9:22 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-17 3:00 [PATCH v4 00/07] MT6779 IOMMU SUPPORT Chao Hao
2020-06-17 3:00 ` [PATCH v4 1/7] dt-bindings: mediatek: Add bindings for MT6779 Chao Hao
2020-06-17 3:00 ` [PATCH v4 2/7] iommu/mediatek: Rename the register STANDARD_AXI_MODE(0x48) to MISC_CTRL Chao Hao
2020-06-17 9:04 ` Matthias Brugger
2020-06-17 3:00 ` [PATCH v4 3/7] iommu/mediatek: Set MISC_CTRL register Chao Hao
2020-06-17 9:34 ` Matthias Brugger
2020-06-18 11:49 ` chao hao
[not found] ` <1592618616.3951.12.camel@mhfsdcap03>
2020-06-24 6:39 ` chao hao
2020-06-17 3:00 ` [PATCH v4 4/7] iommu/mediatek: Move inv_sel_reg into the plat_data Chao Hao
2020-06-17 9:09 ` Matthias Brugger
2020-06-17 3:00 ` [PATCH v4 5/7] iommu/mediatek: Add sub_comm id in translation fault Chao Hao
2020-06-17 9:17 ` Matthias Brugger
2020-06-17 11:11 ` Yong Wu
2020-06-18 11:44 ` chao hao
2020-06-17 3:00 ` [PATCH v4 6/7] iommu/mediatek: Add REG_MMU_WR_LEN definition preparing for mt6779 Chao Hao
2020-06-17 9:22 ` Matthias Brugger [this message]
2020-06-19 10:56 ` chao hao
2020-06-21 11:01 ` Matthias Brugger
2020-06-24 6:36 ` chao hao
2020-06-17 3:00 ` [PATCH v4 7/7] iommu/mediatek: Add mt6779 basic support Chao Hao
2020-06-17 9:33 ` Matthias Brugger
2020-06-18 11:54 ` chao hao
2020-06-18 16:00 ` Matthias Brugger
2020-06-19 10:50 ` chao hao
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