[PATCH v7 0/4] support gce on mt6779 platform

[PATCH v7 0/4] support gce on mt6779 platform

[Dennis YC Hsieh]

This patch support gce on mt6779 platform.

Change since v6:
- Separate all helper function to another patchset.

Change since v5:
- spearate address shift code in client helper and mailbox controller
- separate write_s/write_s_mask and write_s_value/write_s_mask_value so that
  client can decide use mask or not
- fix typo in header

Change since v4:
- do not clear disp event again in drm driver
- symbolize value 1 to jump relative

[... snip ...]


Dennis YC Hsieh (4):
  dt-binding: gce: add gce header file for mt6779
  mailbox: cmdq: variablize address shift in platform
  mailbox: cmdq: support mt6779 gce platform definition
  mailbox: mediatek: cmdq: clear task in channel before shutdown

 .../devicetree/bindings/mailbox/mtk-gce.txt   |   8 +-
 drivers/mailbox/mtk-cmdq-mailbox.c            | 101 ++++++--
 include/dt-bindings/gce/mt6779-gce.h          | 222 ++++++++++++++++++
 include/linux/mailbox/mtk-cmdq-mailbox.h      |   2 +
 4 files changed, 315 insertions(+), 18 deletions(-)
 create mode 100644 include/dt-bindings/gce/mt6779-gce.h

-- 
2.18.0

[PATCH v7 1/4] dt-binding: gce: add gce header file for mt6779

[Dennis YC Hsieh]

Add documentation for the mt6779 gce.

Add gce header file defined the gce hardware event,
subsys number and constant for mt6779.

Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
 .../devicetree/bindings/mailbox/mtk-gce.txt        |    8 +-
 include/dt-bindings/gce/mt6779-gce.h               |  222 ++++++++++++++++++++
 2 files changed, 227 insertions(+), 3 deletions(-)
 create mode 100644 include/dt-bindings/gce/mt6779-gce.h

diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
index 7b13787ab13d..82c0a83fed09 100644
--- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
+++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
@@ -9,7 +9,8 @@ CMDQ driver uses mailbox framework for communication. Please refer to
 mailbox.txt for generic information about mailbox device-tree bindings.
 
 Required properties:
-- compatible: can be "mediatek,mt8173-gce" or "mediatek,mt8183-gce"
+- compatible: can be "mediatek,mt8173-gce", "mediatek,mt8183-gce" or
+  "mediatek,mt6779-gce".
 - reg: Address range of the GCE unit
 - interrupts: The interrupt signal from the GCE block
 - clock: Clocks according to the common clock binding
@@ -36,8 +37,9 @@ Optional properties for a client device:
   start_offset: the start offset of register address that GCE can access.
   size: the total size of register address that GCE can access.
 
-Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h'
-or 'dt-binding/gce/mt8183-gce.h'. Such as sub-system ids, thread priority, event ids.
+Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h',
+'dt-binding/gce/mt8183-gce.h' or 'dt-bindings/gce/mt6779-gce.h'. Such as
+sub-system ids, thread priority, event ids.
 
 Example:
 
diff --git a/include/dt-bindings/gce/mt6779-gce.h b/include/dt-bindings/gce/mt6779-gce.h
new file mode 100644
index 000000000000..06101316ace4
--- /dev/null
+++ b/include/dt-bindings/gce/mt6779-gce.h
@@ -0,0 +1,222 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Dennis-YC Hsieh <dennis-yc.hsieh@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_GCE_MT6779_H
+#define _DT_BINDINGS_GCE_MT6779_H
+
+#define CMDQ_NO_TIMEOUT		0xffffffff
+
+/* GCE HW thread priority */
+#define CMDQ_THR_PRIO_LOWEST	0
+#define CMDQ_THR_PRIO_1		1
+#define CMDQ_THR_PRIO_2		2
+#define CMDQ_THR_PRIO_3		3
+#define CMDQ_THR_PRIO_4		4
+#define CMDQ_THR_PRIO_5		5
+#define CMDQ_THR_PRIO_6		6
+#define CMDQ_THR_PRIO_HIGHEST	7
+
+/* GCE subsys table */
+#define SUBSYS_1300XXXX		0
+#define SUBSYS_1400XXXX		1
+#define SUBSYS_1401XXXX		2
+#define SUBSYS_1402XXXX		3
+#define SUBSYS_1502XXXX		4
+#define SUBSYS_1880XXXX		5
+#define SUBSYS_1881XXXX		6
+#define SUBSYS_1882XXXX		7
+#define SUBSYS_1883XXXX		8
+#define SUBSYS_1884XXXX		9
+#define SUBSYS_1000XXXX		10
+#define SUBSYS_1001XXXX		11
+#define SUBSYS_1002XXXX		12
+#define SUBSYS_1003XXXX		13
+#define SUBSYS_1004XXXX		14
+#define SUBSYS_1005XXXX		15
+#define SUBSYS_1020XXXX		16
+#define SUBSYS_1028XXXX		17
+#define SUBSYS_1700XXXX		18
+#define SUBSYS_1701XXXX		19
+#define SUBSYS_1702XXXX		20
+#define SUBSYS_1703XXXX		21
+#define SUBSYS_1800XXXX		22
+#define SUBSYS_1801XXXX		23
+#define SUBSYS_1802XXXX		24
+#define SUBSYS_1804XXXX		25
+#define SUBSYS_1805XXXX		26
+#define SUBSYS_1808XXXX		27
+#define SUBSYS_180aXXXX		28
+#define SUBSYS_180bXXXX		29
+#define CMDQ_SUBSYS_OFF		32
+
+/* GCE hardware events */
+#define CMDQ_EVENT_DISP_RDMA0_SOF		0
+#define CMDQ_EVENT_DISP_RDMA1_SOF		1
+#define CMDQ_EVENT_MDP_RDMA0_SOF		2
+#define CMDQ_EVENT_MDP_RDMA1_SOF		3
+#define CMDQ_EVENT_MDP_RSZ0_SOF			4
+#define CMDQ_EVENT_MDP_RSZ1_SOF			5
+#define CMDQ_EVENT_MDP_TDSHP_SOF		6
+#define CMDQ_EVENT_MDP_WROT0_SOF		7
+#define CMDQ_EVENT_MDP_WROT1_SOF		8
+#define CMDQ_EVENT_DISP_OVL0_SOF		9
+#define CMDQ_EVENT_DISP_2L_OVL0_SOF		10
+#define CMDQ_EVENT_DISP_2L_OVL1_SOF		11
+#define CMDQ_EVENT_DISP_WDMA0_SOF		12
+#define CMDQ_EVENT_DISP_COLOR0_SOF		13
+#define CMDQ_EVENT_DISP_CCORR0_SOF		14
+#define CMDQ_EVENT_DISP_AAL0_SOF		15
+#define CMDQ_EVENT_DISP_GAMMA0_SOF		16
+#define CMDQ_EVENT_DISP_DITHER0_SOF		17
+#define CMDQ_EVENT_DISP_PWM0_SOF		18
+#define CMDQ_EVENT_DISP_DSI0_SOF		19
+#define CMDQ_EVENT_DISP_DPI0_SOF		20
+#define CMDQ_EVENT_DISP_POSTMASK0_SOF		21
+#define CMDQ_EVENT_DISP_RSZ0_SOF		22
+#define CMDQ_EVENT_MDP_AAL_SOF			23
+#define CMDQ_EVENT_MDP_CCORR_SOF		24
+#define CMDQ_EVENT_DISP_DBI0_SOF		25
+#define CMDQ_EVENT_ISP_RELAY_SOF		26
+#define CMDQ_EVENT_IPU_RELAY_SOF		27
+#define CMDQ_EVENT_DISP_RDMA0_EOF		28
+#define CMDQ_EVENT_DISP_RDMA1_EOF		29
+#define CMDQ_EVENT_MDP_RDMA0_EOF		30
+#define CMDQ_EVENT_MDP_RDMA1_EOF		31
+#define CMDQ_EVENT_MDP_RSZ0_EOF			32
+#define CMDQ_EVENT_MDP_RSZ1_EOF			33
+#define CMDQ_EVENT_MDP_TDSHP_EOF		34
+#define CMDQ_EVENT_MDP_WROT0_W_EOF		35
+#define CMDQ_EVENT_MDP_WROT1_W_EOF		36
+#define CMDQ_EVENT_DISP_OVL0_EOF		37
+#define CMDQ_EVENT_DISP_2L_OVL0_EOF		38
+#define CMDQ_EVENT_DISP_2L_OVL1_EOF		39
+#define CMDQ_EVENT_DISP_WDMA0_EOF		40
+#define CMDQ_EVENT_DISP_COLOR0_EOF		41
+#define CMDQ_EVENT_DISP_CCORR0_EOF		42
+#define CMDQ_EVENT_DISP_AAL0_EOF		43
+#define CMDQ_EVENT_DISP_GAMMA0_EOF		44
+#define CMDQ_EVENT_DISP_DITHER0_EOF		45
+#define CMDQ_EVENT_DISP_DSI0_EOF		46
+#define CMDQ_EVENT_DISP_DPI0_EOF		47
+#define CMDQ_EVENT_DISP_RSZ0_EOF		49
+#define CMDQ_EVENT_MDP_AAL_FRAME_DONE		50
+#define CMDQ_EVENT_MDP_CCORR_FRAME_DONE		51
+#define CMDQ_EVENT_DISP_POSTMASK0_FRAME_DONE	52
+#define CMDQ_EVENT_MUTEX0_STREAM_EOF		130
+#define CMDQ_EVENT_MUTEX1_STREAM_EOF		131
+#define CMDQ_EVENT_MUTEX2_STREAM_EOF		132
+#define CMDQ_EVENT_MUTEX3_STREAM_EOF		133
+#define CMDQ_EVENT_MUTEX4_STREAM_EOF		134
+#define CMDQ_EVENT_MUTEX5_STREAM_EOF		135
+#define CMDQ_EVENT_MUTEX6_STREAM_EOF		136
+#define CMDQ_EVENT_MUTEX7_STREAM_EOF		137
+#define CMDQ_EVENT_MUTEX8_STREAM_EOF		138
+#define CMDQ_EVENT_MUTEX9_STREAM_EOF		139
+#define CMDQ_EVENT_MUTEX10_STREAM_EOF		140
+#define CMDQ_EVENT_MUTEX11_STREAM_EOF		141
+#define CMDQ_EVENT_DISP_RDMA0_UNDERRUN		142
+#define CMDQ_EVENT_DISP_RDMA1_UNDERRUN		143
+#define CMDQ_EVENT_DISP_RDMA2_UNDERRUN		144
+#define CMDQ_EVENT_DISP_RDMA3_UNDERRUN		145
+#define CMDQ_EVENT_DSI0_TE			146
+#define CMDQ_EVENT_DSI0_IRQ_EVENT		147
+#define CMDQ_EVENT_DSI0_DONE_EVENT		148
+#define CMDQ_EVENT_DISP_POSTMASK0_RST_DONE	150
+#define CMDQ_EVENT_DISP_WDMA0_RST_DONE		151
+#define CMDQ_EVENT_MDP_WROT0_RST_DONE		153
+#define CMDQ_EVENT_MDP_RDMA0_RST_DONE		154
+#define CMDQ_EVENT_DISP_OVL0_RST_DONE		155
+#define CMDQ_EVENT_DISP_OVL0_2L_RST_DONE	156
+#define CMDQ_EVENT_DISP_OVL1_2L_RST_DONE	157
+#define CMDQ_EVENT_DIP_CQ_THREAD0_EOF		257
+#define CMDQ_EVENT_DIP_CQ_THREAD1_EOF		258
+#define CMDQ_EVENT_DIP_CQ_THREAD2_EOF		259
+#define CMDQ_EVENT_DIP_CQ_THREAD3_EOF		260
+#define CMDQ_EVENT_DIP_CQ_THREAD4_EOF		261
+#define CMDQ_EVENT_DIP_CQ_THREAD5_EOF		262
+#define CMDQ_EVENT_DIP_CQ_THREAD6_EOF		263
+#define CMDQ_EVENT_DIP_CQ_THREAD7_EOF		264
+#define CMDQ_EVENT_DIP_CQ_THREAD8_EOF		265
+#define CMDQ_EVENT_DIP_CQ_THREAD9_EOF		266
+#define CMDQ_EVENT_DIP_CQ_THREAD10_EOF		267
+#define CMDQ_EVENT_DIP_CQ_THREAD11_EOF		268
+#define CMDQ_EVENT_DIP_CQ_THREAD12_EOF		269
+#define CMDQ_EVENT_DIP_CQ_THREAD13_EOF		270
+#define CMDQ_EVENT_DIP_CQ_THREAD14_EOF		271
+#define CMDQ_EVENT_DIP_CQ_THREAD15_EOF		272
+#define CMDQ_EVENT_DIP_CQ_THREAD16_EOF		273
+#define CMDQ_EVENT_DIP_CQ_THREAD17_EOF		274
+#define CMDQ_EVENT_DIP_CQ_THREAD18_EOF		275
+#define CMDQ_EVENT_DIP_DMA_ERR_EVENT		276
+#define CMDQ_EVENT_AMD_FRAME_DONE		277
+#define CMDQ_EVENT_MFB_DONE			278
+#define CMDQ_EVENT_WPE_A_EOF			279
+#define CMDQ_EVENT_VENC_EOF			289
+#define CMDQ_EVENT_VENC_CMDQ_PAUSE_DONE		290
+#define CMDQ_EVENT_JPEG_ENC_EOF			291
+#define CMDQ_EVENT_VENC_MB_DONE			292
+#define CMDQ_EVENT_VENC_128BYTE_CNT_DONE	293
+#define CMDQ_EVENT_ISP_FRAME_DONE_A		321
+#define CMDQ_EVENT_ISP_FRAME_DONE_B		322
+#define CMDQ_EVENT_ISP_FRAME_DONE_C		323
+#define CMDQ_EVENT_ISP_CAMSV_0_PASS1_DONE	324
+#define CMDQ_EVENT_ISP_CAMSV_0_2_PASS1_DONE	325
+#define CMDQ_EVENT_ISP_CAMSV_1_PASS1_DONE	326
+#define CMDQ_EVENT_ISP_CAMSV_2_PASS1_DONE	327
+#define CMDQ_EVENT_ISP_CAMSV_3_PASS1_DONE	328
+#define CMDQ_EVENT_ISP_TSF_DONE			329
+#define CMDQ_EVENT_SENINF_0_FIFO_FULL		330
+#define CMDQ_EVENT_SENINF_1_FIFO_FULL		331
+#define CMDQ_EVENT_SENINF_2_FIFO_FULL		332
+#define CMDQ_EVENT_SENINF_3_FIFO_FULL		333
+#define CMDQ_EVENT_SENINF_4_FIFO_FULL		334
+#define CMDQ_EVENT_SENINF_5_FIFO_FULL		335
+#define CMDQ_EVENT_SENINF_6_FIFO_FULL		336
+#define CMDQ_EVENT_SENINF_7_FIFO_FULL		337
+#define CMDQ_EVENT_TG_OVRUN_A_INT_DLY		338
+#define CMDQ_EVENT_TG_OVRUN_B_INT_DLY		339
+#define CMDQ_EVENT_TG_OVRUN_C_INT		340
+#define CMDQ_EVENT_TG_GRABERR_A_INT_DLY		341
+#define CMDQ_EVENT_TG_GRABERR_B_INT_DLY		342
+#define CMDQ_EVENT_TG_GRABERR_C_INT		343
+#define CMDQ_EVENT_CQ_VR_SNAP_A_INT_DLY		344
+#define CMDQ_EVENT_CQ_VR_SNAP_B_INT_DLY		345
+#define CMDQ_EVENT_CQ_VR_SNAP_C_INT		346
+#define CMDQ_EVENT_DMA_R1_ERROR_A_INT_DLY	347
+#define CMDQ_EVENT_DMA_R1_ERROR_B_INT_DLY	348
+#define CMDQ_EVENT_DMA_R1_ERROR_C_INT		349
+#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_0	353
+#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_1	354
+#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_2	355
+#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_3	356
+#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_0	385
+#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_1	386
+#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_2	387
+#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_3	388
+#define CMDQ_EVENT_VDEC_EVENT_0			416
+#define CMDQ_EVENT_VDEC_EVENT_1			417
+#define CMDQ_EVENT_VDEC_EVENT_2			418
+#define CMDQ_EVENT_VDEC_EVENT_3			419
+#define CMDQ_EVENT_VDEC_EVENT_4			420
+#define CMDQ_EVENT_VDEC_EVENT_5			421
+#define CMDQ_EVENT_VDEC_EVENT_6			422
+#define CMDQ_EVENT_VDEC_EVENT_7			423
+#define CMDQ_EVENT_VDEC_EVENT_8			424
+#define CMDQ_EVENT_VDEC_EVENT_9			425
+#define CMDQ_EVENT_VDEC_EVENT_10		426
+#define CMDQ_EVENT_VDEC_EVENT_11		427
+#define CMDQ_EVENT_VDEC_EVENT_12		428
+#define CMDQ_EVENT_VDEC_EVENT_13		429
+#define CMDQ_EVENT_VDEC_EVENT_14		430
+#define CMDQ_EVENT_VDEC_EVENT_15		431
+#define CMDQ_EVENT_FDVT_DONE			449
+#define CMDQ_EVENT_FE_DONE			450
+#define CMDQ_EVENT_RSC_EOF			451
+#define CMDQ_EVENT_DVS_DONE_ASYNC_SHOT		452
+#define CMDQ_EVENT_DVP_DONE_ASYNC_SHOT		453
+#define CMDQ_EVENT_DSI0_TE_INFRA		898
+
+#endif
-- 
1.7.9.5

Re: [PATCH v7 1/4] dt-binding: gce: add gce header file for mt6779

[Bibby Hsieh]

Reviewed-by: Bibby Hsieh <bibby.hsieh@mediatek.com>

Thanks.


On Sun, 2020-06-21 at 21:22 +0800, Dennis YC Hsieh wrote:
> Add documentation for the mt6779 gce.
> 
> Add gce header file defined the gce hardware event,
> subsys number and constant for mt6779.
> 
> Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> ---
>  .../devicetree/bindings/mailbox/mtk-gce.txt        |    8 +-
>  include/dt-bindings/gce/mt6779-gce.h               |  222 ++++++++++++++++++++
>  2 files changed, 227 insertions(+), 3 deletions(-)
>  create mode 100644 include/dt-bindings/gce/mt6779-gce.h
> 
> diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
> index 7b13787ab13d..82c0a83fed09 100644
> --- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
> +++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
> @@ -9,7 +9,8 @@ CMDQ driver uses mailbox framework for communication. Please refer to
>  mailbox.txt for generic information about mailbox device-tree bindings.
>  
>  Required properties:
> -- compatible: can be "mediatek,mt8173-gce" or "mediatek,mt8183-gce"
> +- compatible: can be "mediatek,mt8173-gce", "mediatek,mt8183-gce" or
> +  "mediatek,mt6779-gce".
>  - reg: Address range of the GCE unit
>  - interrupts: The interrupt signal from the GCE block
>  - clock: Clocks according to the common clock binding
> @@ -36,8 +37,9 @@ Optional properties for a client device:
>    start_offset: the start offset of register address that GCE can access.
>    size: the total size of register address that GCE can access.
>  
> -Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h'
> -or 'dt-binding/gce/mt8183-gce.h'. Such as sub-system ids, thread priority, event ids.
> +Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h',
> +'dt-binding/gce/mt8183-gce.h' or 'dt-bindings/gce/mt6779-gce.h'. Such as
> +sub-system ids, thread priority, event ids.
>  
>  Example:
>  
> diff --git a/include/dt-bindings/gce/mt6779-gce.h b/include/dt-bindings/gce/mt6779-gce.h
> new file mode 100644
> index 000000000000..06101316ace4
> --- /dev/null
> +++ b/include/dt-bindings/gce/mt6779-gce.h
> @@ -0,0 +1,222 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2019 MediaTek Inc.
> + * Author: Dennis-YC Hsieh <dennis-yc.hsieh@mediatek.com>
> + */
> +
> +#ifndef _DT_BINDINGS_GCE_MT6779_H
> +#define _DT_BINDINGS_GCE_MT6779_H
> +
> +#define CMDQ_NO_TIMEOUT		0xffffffff
> +
> +/* GCE HW thread priority */
> +#define CMDQ_THR_PRIO_LOWEST	0
> +#define CMDQ_THR_PRIO_1		1
> +#define CMDQ_THR_PRIO_2		2
> +#define CMDQ_THR_PRIO_3		3
> +#define CMDQ_THR_PRIO_4		4
> +#define CMDQ_THR_PRIO_5		5
> +#define CMDQ_THR_PRIO_6		6
> +#define CMDQ_THR_PRIO_HIGHEST	7
> +
> +/* GCE subsys table */
> +#define SUBSYS_1300XXXX		0
> +#define SUBSYS_1400XXXX		1
> +#define SUBSYS_1401XXXX		2
> +#define SUBSYS_1402XXXX		3
> +#define SUBSYS_1502XXXX		4
> +#define SUBSYS_1880XXXX		5
> +#define SUBSYS_1881XXXX		6
> +#define SUBSYS_1882XXXX		7
> +#define SUBSYS_1883XXXX		8
> +#define SUBSYS_1884XXXX		9
> +#define SUBSYS_1000XXXX		10
> +#define SUBSYS_1001XXXX		11
> +#define SUBSYS_1002XXXX		12
> +#define SUBSYS_1003XXXX		13
> +#define SUBSYS_1004XXXX		14
> +#define SUBSYS_1005XXXX		15
> +#define SUBSYS_1020XXXX		16
> +#define SUBSYS_1028XXXX		17
> +#define SUBSYS_1700XXXX		18
> +#define SUBSYS_1701XXXX		19
> +#define SUBSYS_1702XXXX		20
> +#define SUBSYS_1703XXXX		21
> +#define SUBSYS_1800XXXX		22
> +#define SUBSYS_1801XXXX		23
> +#define SUBSYS_1802XXXX		24
> +#define SUBSYS_1804XXXX		25
> +#define SUBSYS_1805XXXX		26
> +#define SUBSYS_1808XXXX		27
> +#define SUBSYS_180aXXXX		28
> +#define SUBSYS_180bXXXX		29
> +#define CMDQ_SUBSYS_OFF		32
> +
> +/* GCE hardware events */
> +#define CMDQ_EVENT_DISP_RDMA0_SOF		0
> +#define CMDQ_EVENT_DISP_RDMA1_SOF		1
> +#define CMDQ_EVENT_MDP_RDMA0_SOF		2
> +#define CMDQ_EVENT_MDP_RDMA1_SOF		3
> +#define CMDQ_EVENT_MDP_RSZ0_SOF			4
> +#define CMDQ_EVENT_MDP_RSZ1_SOF			5
> +#define CMDQ_EVENT_MDP_TDSHP_SOF		6
> +#define CMDQ_EVENT_MDP_WROT0_SOF		7
> +#define CMDQ_EVENT_MDP_WROT1_SOF		8
> +#define CMDQ_EVENT_DISP_OVL0_SOF		9
> +#define CMDQ_EVENT_DISP_2L_OVL0_SOF		10
> +#define CMDQ_EVENT_DISP_2L_OVL1_SOF		11
> +#define CMDQ_EVENT_DISP_WDMA0_SOF		12
> +#define CMDQ_EVENT_DISP_COLOR0_SOF		13
> +#define CMDQ_EVENT_DISP_CCORR0_SOF		14
> +#define CMDQ_EVENT_DISP_AAL0_SOF		15
> +#define CMDQ_EVENT_DISP_GAMMA0_SOF		16
> +#define CMDQ_EVENT_DISP_DITHER0_SOF		17
> +#define CMDQ_EVENT_DISP_PWM0_SOF		18
> +#define CMDQ_EVENT_DISP_DSI0_SOF		19
> +#define CMDQ_EVENT_DISP_DPI0_SOF		20
> +#define CMDQ_EVENT_DISP_POSTMASK0_SOF		21
> +#define CMDQ_EVENT_DISP_RSZ0_SOF		22
> +#define CMDQ_EVENT_MDP_AAL_SOF			23
> +#define CMDQ_EVENT_MDP_CCORR_SOF		24
> +#define CMDQ_EVENT_DISP_DBI0_SOF		25
> +#define CMDQ_EVENT_ISP_RELAY_SOF		26
> +#define CMDQ_EVENT_IPU_RELAY_SOF		27
> +#define CMDQ_EVENT_DISP_RDMA0_EOF		28
> +#define CMDQ_EVENT_DISP_RDMA1_EOF		29
> +#define CMDQ_EVENT_MDP_RDMA0_EOF		30
> +#define CMDQ_EVENT_MDP_RDMA1_EOF		31
> +#define CMDQ_EVENT_MDP_RSZ0_EOF			32
> +#define CMDQ_EVENT_MDP_RSZ1_EOF			33
> +#define CMDQ_EVENT_MDP_TDSHP_EOF		34
> +#define CMDQ_EVENT_MDP_WROT0_W_EOF		35
> +#define CMDQ_EVENT_MDP_WROT1_W_EOF		36
> +#define CMDQ_EVENT_DISP_OVL0_EOF		37
> +#define CMDQ_EVENT_DISP_2L_OVL0_EOF		38
> +#define CMDQ_EVENT_DISP_2L_OVL1_EOF		39
> +#define CMDQ_EVENT_DISP_WDMA0_EOF		40
> +#define CMDQ_EVENT_DISP_COLOR0_EOF		41
> +#define CMDQ_EVENT_DISP_CCORR0_EOF		42
> +#define CMDQ_EVENT_DISP_AAL0_EOF		43
> +#define CMDQ_EVENT_DISP_GAMMA0_EOF		44
> +#define CMDQ_EVENT_DISP_DITHER0_EOF		45
> +#define CMDQ_EVENT_DISP_DSI0_EOF		46
> +#define CMDQ_EVENT_DISP_DPI0_EOF		47
> +#define CMDQ_EVENT_DISP_RSZ0_EOF		49
> +#define CMDQ_EVENT_MDP_AAL_FRAME_DONE		50
> +#define CMDQ_EVENT_MDP_CCORR_FRAME_DONE		51
> +#define CMDQ_EVENT_DISP_POSTMASK0_FRAME_DONE	52
> +#define CMDQ_EVENT_MUTEX0_STREAM_EOF		130
> +#define CMDQ_EVENT_MUTEX1_STREAM_EOF		131
> +#define CMDQ_EVENT_MUTEX2_STREAM_EOF		132
> +#define CMDQ_EVENT_MUTEX3_STREAM_EOF		133
> +#define CMDQ_EVENT_MUTEX4_STREAM_EOF		134
> +#define CMDQ_EVENT_MUTEX5_STREAM_EOF		135
> +#define CMDQ_EVENT_MUTEX6_STREAM_EOF		136
> +#define CMDQ_EVENT_MUTEX7_STREAM_EOF		137
> +#define CMDQ_EVENT_MUTEX8_STREAM_EOF		138
> +#define CMDQ_EVENT_MUTEX9_STREAM_EOF		139
> +#define CMDQ_EVENT_MUTEX10_STREAM_EOF		140
> +#define CMDQ_EVENT_MUTEX11_STREAM_EOF		141
> +#define CMDQ_EVENT_DISP_RDMA0_UNDERRUN		142
> +#define CMDQ_EVENT_DISP_RDMA1_UNDERRUN		143
> +#define CMDQ_EVENT_DISP_RDMA2_UNDERRUN		144
> +#define CMDQ_EVENT_DISP_RDMA3_UNDERRUN		145
> +#define CMDQ_EVENT_DSI0_TE			146
> +#define CMDQ_EVENT_DSI0_IRQ_EVENT		147
> +#define CMDQ_EVENT_DSI0_DONE_EVENT		148
> +#define CMDQ_EVENT_DISP_POSTMASK0_RST_DONE	150
> +#define CMDQ_EVENT_DISP_WDMA0_RST_DONE		151
> +#define CMDQ_EVENT_MDP_WROT0_RST_DONE		153
> +#define CMDQ_EVENT_MDP_RDMA0_RST_DONE		154
> +#define CMDQ_EVENT_DISP_OVL0_RST_DONE		155
> +#define CMDQ_EVENT_DISP_OVL0_2L_RST_DONE	156
> +#define CMDQ_EVENT_DISP_OVL1_2L_RST_DONE	157
> +#define CMDQ_EVENT_DIP_CQ_THREAD0_EOF		257
> +#define CMDQ_EVENT_DIP_CQ_THREAD1_EOF		258
> +#define CMDQ_EVENT_DIP_CQ_THREAD2_EOF		259
> +#define CMDQ_EVENT_DIP_CQ_THREAD3_EOF		260
> +#define CMDQ_EVENT_DIP_CQ_THREAD4_EOF		261
> +#define CMDQ_EVENT_DIP_CQ_THREAD5_EOF		262
> +#define CMDQ_EVENT_DIP_CQ_THREAD6_EOF		263
> +#define CMDQ_EVENT_DIP_CQ_THREAD7_EOF		264
> +#define CMDQ_EVENT_DIP_CQ_THREAD8_EOF		265
> +#define CMDQ_EVENT_DIP_CQ_THREAD9_EOF		266
> +#define CMDQ_EVENT_DIP_CQ_THREAD10_EOF		267
> +#define CMDQ_EVENT_DIP_CQ_THREAD11_EOF		268
> +#define CMDQ_EVENT_DIP_CQ_THREAD12_EOF		269
> +#define CMDQ_EVENT_DIP_CQ_THREAD13_EOF		270
> +#define CMDQ_EVENT_DIP_CQ_THREAD14_EOF		271
> +#define CMDQ_EVENT_DIP_CQ_THREAD15_EOF		272
> +#define CMDQ_EVENT_DIP_CQ_THREAD16_EOF		273
> +#define CMDQ_EVENT_DIP_CQ_THREAD17_EOF		274
> +#define CMDQ_EVENT_DIP_CQ_THREAD18_EOF		275
> +#define CMDQ_EVENT_DIP_DMA_ERR_EVENT		276
> +#define CMDQ_EVENT_AMD_FRAME_DONE		277
> +#define CMDQ_EVENT_MFB_DONE			278
> +#define CMDQ_EVENT_WPE_A_EOF			279
> +#define CMDQ_EVENT_VENC_EOF			289
> +#define CMDQ_EVENT_VENC_CMDQ_PAUSE_DONE		290
> +#define CMDQ_EVENT_JPEG_ENC_EOF			291
> +#define CMDQ_EVENT_VENC_MB_DONE			292
> +#define CMDQ_EVENT_VENC_128BYTE_CNT_DONE	293
> +#define CMDQ_EVENT_ISP_FRAME_DONE_A		321
> +#define CMDQ_EVENT_ISP_FRAME_DONE_B		322
> +#define CMDQ_EVENT_ISP_FRAME_DONE_C		323
> +#define CMDQ_EVENT_ISP_CAMSV_0_PASS1_DONE	324
> +#define CMDQ_EVENT_ISP_CAMSV_0_2_PASS1_DONE	325
> +#define CMDQ_EVENT_ISP_CAMSV_1_PASS1_DONE	326
> +#define CMDQ_EVENT_ISP_CAMSV_2_PASS1_DONE	327
> +#define CMDQ_EVENT_ISP_CAMSV_3_PASS1_DONE	328
> +#define CMDQ_EVENT_ISP_TSF_DONE			329
> +#define CMDQ_EVENT_SENINF_0_FIFO_FULL		330
> +#define CMDQ_EVENT_SENINF_1_FIFO_FULL		331
> +#define CMDQ_EVENT_SENINF_2_FIFO_FULL		332
> +#define CMDQ_EVENT_SENINF_3_FIFO_FULL		333
> +#define CMDQ_EVENT_SENINF_4_FIFO_FULL		334
> +#define CMDQ_EVENT_SENINF_5_FIFO_FULL		335
> +#define CMDQ_EVENT_SENINF_6_FIFO_FULL		336
> +#define CMDQ_EVENT_SENINF_7_FIFO_FULL		337
> +#define CMDQ_EVENT_TG_OVRUN_A_INT_DLY		338
> +#define CMDQ_EVENT_TG_OVRUN_B_INT_DLY		339
> +#define CMDQ_EVENT_TG_OVRUN_C_INT		340
> +#define CMDQ_EVENT_TG_GRABERR_A_INT_DLY		341
> +#define CMDQ_EVENT_TG_GRABERR_B_INT_DLY		342
> +#define CMDQ_EVENT_TG_GRABERR_C_INT		343
> +#define CMDQ_EVENT_CQ_VR_SNAP_A_INT_DLY		344
> +#define CMDQ_EVENT_CQ_VR_SNAP_B_INT_DLY		345
> +#define CMDQ_EVENT_CQ_VR_SNAP_C_INT		346
> +#define CMDQ_EVENT_DMA_R1_ERROR_A_INT_DLY	347
> +#define CMDQ_EVENT_DMA_R1_ERROR_B_INT_DLY	348
> +#define CMDQ_EVENT_DMA_R1_ERROR_C_INT		349
> +#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_0	353
> +#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_1	354
> +#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_2	355
> +#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_3	356
> +#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_0	385
> +#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_1	386
> +#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_2	387
> +#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_3	388
> +#define CMDQ_EVENT_VDEC_EVENT_0			416
> +#define CMDQ_EVENT_VDEC_EVENT_1			417
> +#define CMDQ_EVENT_VDEC_EVENT_2			418
> +#define CMDQ_EVENT_VDEC_EVENT_3			419
> +#define CMDQ_EVENT_VDEC_EVENT_4			420
> +#define CMDQ_EVENT_VDEC_EVENT_5			421
> +#define CMDQ_EVENT_VDEC_EVENT_6			422
> +#define CMDQ_EVENT_VDEC_EVENT_7			423
> +#define CMDQ_EVENT_VDEC_EVENT_8			424
> +#define CMDQ_EVENT_VDEC_EVENT_9			425
> +#define CMDQ_EVENT_VDEC_EVENT_10		426
> +#define CMDQ_EVENT_VDEC_EVENT_11		427
> +#define CMDQ_EVENT_VDEC_EVENT_12		428
> +#define CMDQ_EVENT_VDEC_EVENT_13		429
> +#define CMDQ_EVENT_VDEC_EVENT_14		430
> +#define CMDQ_EVENT_VDEC_EVENT_15		431
> +#define CMDQ_EVENT_FDVT_DONE			449
> +#define CMDQ_EVENT_FE_DONE			450
> +#define CMDQ_EVENT_RSC_EOF			451
> +#define CMDQ_EVENT_DVS_DONE_ASYNC_SHOT		452
> +#define CMDQ_EVENT_DVP_DONE_ASYNC_SHOT		453
> +#define CMDQ_EVENT_DSI0_TE_INFRA		898
> +
> +#endif

[PATCH v7 2/4] mailbox: cmdq: variablize address shift in platform

[Dennis YC Hsieh]

Some gce hardware shift pc and end address in register to support
large dram addressing.
Implement gce address shift when write or read pc and end register.
And add shift bit in platform definition.

Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com>
---
 drivers/mailbox/mtk-cmdq-mailbox.c       |   61 ++++++++++++++++++++++--------
 include/linux/mailbox/mtk-cmdq-mailbox.h |    2 +
 2 files changed, 48 insertions(+), 15 deletions(-)

diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index 9a6ce9f5a7db..4dbee9258127 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -76,8 +76,22 @@ struct cmdq {
 	struct cmdq_thread	*thread;
 	struct clk		*clock;
 	bool			suspended;
+	u8			shift_pa;
 };
 
+struct gce_plat {
+	u32 thread_nr;
+	u8 shift;
+};
+
+u8 cmdq_mbox_shift(struct mbox_chan *chan)
+{
+	struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox);
+
+	return cmdq->shift_pa;
+}
+EXPORT_SYMBOL(cmdq_mbox_shift);
+
 static int cmdq_thread_suspend(struct cmdq *cmdq, struct cmdq_thread *thread)
 {
 	u32 status;
@@ -183,7 +197,7 @@ static void cmdq_task_remove_wfe(struct cmdq_task *task)
 	for (i = 0; i < CMDQ_NUM_CMD(task->pkt); i++)
 		if (cmdq_command_is_wfe(base[i]))
 			base[i] = (u64)CMDQ_JUMP_BY_OFFSET << 32 |
-				  CMDQ_JUMP_PASS;
+				  CMDQ_JUMP_PASS >> task->cmdq->shift_pa;
 	dma_sync_single_for_device(dev, task->pa_base, task->pkt->cmd_buf_size,
 				   DMA_TO_DEVICE);
 }
@@ -221,13 +235,15 @@ static void cmdq_task_handle_error(struct cmdq_task *task)
 {
 	struct cmdq_thread *thread = task->thread;
 	struct cmdq_task *next_task;
+	struct cmdq *cmdq = task->cmdq;
 
-	dev_err(task->cmdq->mbox.dev, "task 0x%p error\n", task);
-	WARN_ON(cmdq_thread_suspend(task->cmdq, thread) < 0);
+	dev_err(cmdq->mbox.dev, "task 0x%p error\n", task);
+	WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
 	next_task = list_first_entry_or_null(&thread->task_busy_list,
 			struct cmdq_task, list_entry);
 	if (next_task)
-		writel(next_task->pa_base, thread->base + CMDQ_THR_CURR_ADDR);
+		writel(next_task->pa_base >> cmdq->shift_pa,
+		       thread->base + CMDQ_THR_CURR_ADDR);
 	cmdq_thread_resume(thread);
 }
 
@@ -257,7 +273,7 @@ static void cmdq_thread_irq_handler(struct cmdq *cmdq,
 	else
 		return;
 
-	curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR);
+	curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) << cmdq->shift_pa;
 
 	list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
 				 list_entry) {
@@ -373,16 +389,20 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
 		WARN_ON(clk_enable(cmdq->clock) < 0);
 		WARN_ON(cmdq_thread_reset(cmdq, thread) < 0);
 
-		writel(task->pa_base, thread->base + CMDQ_THR_CURR_ADDR);
-		writel(task->pa_base + pkt->cmd_buf_size,
+		writel(task->pa_base >> cmdq->shift_pa,
+		       thread->base + CMDQ_THR_CURR_ADDR);
+		writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa,
 		       thread->base + CMDQ_THR_END_ADDR);
+
 		writel(thread->priority, thread->base + CMDQ_THR_PRIORITY);
 		writel(CMDQ_THR_IRQ_EN, thread->base + CMDQ_THR_IRQ_ENABLE);
 		writel(CMDQ_THR_ENABLED, thread->base + CMDQ_THR_ENABLE_TASK);
 	} else {
 		WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
-		curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR);
-		end_pa = readl(thread->base + CMDQ_THR_END_ADDR);
+		curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) <<
+			cmdq->shift_pa;
+		end_pa = readl(thread->base + CMDQ_THR_END_ADDR) <<
+			cmdq->shift_pa;
 
 		/*
 		 * Atomic execution should remove the following wfe, i.e. only
@@ -395,7 +415,7 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
 				cmdq_thread_wait_end(thread, end_pa);
 				WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
 				/* set to this task directly */
-				writel(task->pa_base,
+				writel(task->pa_base >> cmdq->shift_pa,
 				       thread->base + CMDQ_THR_CURR_ADDR);
 			} else {
 				cmdq_task_insert_into_thread(task);
@@ -407,14 +427,14 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
 			if (curr_pa == end_pa - CMDQ_INST_SIZE ||
 			    curr_pa == end_pa) {
 				/* set to this task directly */
-				writel(task->pa_base,
+				writel(task->pa_base >> cmdq->shift_pa,
 				       thread->base + CMDQ_THR_CURR_ADDR);
 			} else {
 				cmdq_task_insert_into_thread(task);
 				smp_mb(); /* modify jump before enable thread */
 			}
 		}
-		writel(task->pa_base + pkt->cmd_buf_size,
+		writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa,
 		       thread->base + CMDQ_THR_END_ADDR);
 		cmdq_thread_resume(thread);
 	}
@@ -461,6 +481,7 @@ static int cmdq_probe(struct platform_device *pdev)
 	struct resource *res;
 	struct cmdq *cmdq;
 	int err, i;
+	struct gce_plat *plat_data;
 
 	cmdq = devm_kzalloc(dev, sizeof(*cmdq), GFP_KERNEL);
 	if (!cmdq)
@@ -479,7 +500,14 @@ static int cmdq_probe(struct platform_device *pdev)
 		return -EINVAL;
 	}
 
-	cmdq->thread_nr = (u32)(unsigned long)of_device_get_match_data(dev);
+	plat_data = (struct gce_plat *)of_device_get_match_data(dev);
+	if (!plat_data) {
+		dev_err(dev, "failed to get match data\n");
+		return -EINVAL;
+	}
+
+	cmdq->thread_nr = plat_data->thread_nr;
+	cmdq->shift_pa = plat_data->shift;
 	cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
 	err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
 			       "mtk_cmdq", cmdq);
@@ -542,9 +570,12 @@ static int cmdq_probe(struct platform_device *pdev)
 	.resume = cmdq_resume,
 };
 
+static const struct gce_plat gce_plat_v2 = {.thread_nr = 16};
+static const struct gce_plat gce_plat_v3 = {.thread_nr = 24};
+
 static const struct of_device_id cmdq_of_ids[] = {
-	{.compatible = "mediatek,mt8173-gce", .data = (void *)16},
-	{.compatible = "mediatek,mt8183-gce", .data = (void *)24},
+	{.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_v2},
+	{.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_v3},
 	{}
 };
 
diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h
index a4dc45fbec0a..dfe5b2eb85cc 100644
--- a/include/linux/mailbox/mtk-cmdq-mailbox.h
+++ b/include/linux/mailbox/mtk-cmdq-mailbox.h
@@ -88,4 +88,6 @@ struct cmdq_pkt {
 	void			*cl;
 };
 
+u8 cmdq_mbox_shift(struct mbox_chan *chan);
+
 #endif /* __MTK_CMDQ_MAILBOX_H__ */
-- 
1.7.9.5

Re: [PATCH v7 2/4] mailbox: cmdq: variablize address shift in platform

[Bibby Hsieh]

On Sun, 2020-06-21 at 21:22 +0800, Dennis YC Hsieh wrote:
> Some gce hardware shift pc and end address in register to support
> large dram addressing.
> Implement gce address shift when write or read pc and end register.
> And add shift bit in platform definition.
> 
> Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com>
> ---
>  drivers/mailbox/mtk-cmdq-mailbox.c       |   61 ++++++++++++++++++++++--------
>  include/linux/mailbox/mtk-cmdq-mailbox.h |    2 +
>  2 files changed, 48 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
> index 9a6ce9f5a7db..4dbee9258127 100644
> --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> @@ -76,8 +76,22 @@ struct cmdq {
>  	struct cmdq_thread	*thread;
>  	struct clk		*clock;
>  	bool			suspended;
> +	u8			shift_pa;
>  };
>  
> +struct gce_plat {
> +	u32 thread_nr;
> +	u8 shift;
> +};
> +
> +u8 cmdq_mbox_shift(struct mbox_chan *chan)

How about rename this function as cmdq_get_shift_pa()?


Bibby

> +{
> +	struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox);
> +
> +	return cmdq->shift_pa;
> +}
> +EXPORT_SYMBOL(cmdq_mbox_shift);
> +
>  static int cmdq_thread_suspend(struct cmdq *cmdq, struct cmdq_thread *thread)
>  {
>  	u32 status;
> @@ -183,7 +197,7 @@ static void cmdq_task_remove_wfe(struct cmdq_task *task)
>  	for (i = 0; i < CMDQ_NUM_CMD(task->pkt); i++)
>  		if (cmdq_command_is_wfe(base[i]))
>  			base[i] = (u64)CMDQ_JUMP_BY_OFFSET << 32 |
> -				  CMDQ_JUMP_PASS;
> +				  CMDQ_JUMP_PASS >> task->cmdq->shift_pa;
>  	dma_sync_single_for_device(dev, task->pa_base, task->pkt->cmd_buf_size,
>  				   DMA_TO_DEVICE);
>  }
> @@ -221,13 +235,15 @@ static void cmdq_task_handle_error(struct cmdq_task *task)
>  {
>  	struct cmdq_thread *thread = task->thread;
>  	struct cmdq_task *next_task;
> +	struct cmdq *cmdq = task->cmdq;
>  
> -	dev_err(task->cmdq->mbox.dev, "task 0x%p error\n", task);
> -	WARN_ON(cmdq_thread_suspend(task->cmdq, thread) < 0);
> +	dev_err(cmdq->mbox.dev, "task 0x%p error\n", task);
> +	WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
>  	next_task = list_first_entry_or_null(&thread->task_busy_list,
>  			struct cmdq_task, list_entry);
>  	if (next_task)
> -		writel(next_task->pa_base, thread->base + CMDQ_THR_CURR_ADDR);
> +		writel(next_task->pa_base >> cmdq->shift_pa,
> +		       thread->base + CMDQ_THR_CURR_ADDR);
>  	cmdq_thread_resume(thread);
>  }
>  
> @@ -257,7 +273,7 @@ static void cmdq_thread_irq_handler(struct cmdq *cmdq,
>  	else
>  		return;
>  
> -	curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR);
> +	curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) << cmdq->shift_pa;
>  
>  	list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
>  				 list_entry) {
> @@ -373,16 +389,20 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
>  		WARN_ON(clk_enable(cmdq->clock) < 0);
>  		WARN_ON(cmdq_thread_reset(cmdq, thread) < 0);
>  
> -		writel(task->pa_base, thread->base + CMDQ_THR_CURR_ADDR);
> -		writel(task->pa_base + pkt->cmd_buf_size,
> +		writel(task->pa_base >> cmdq->shift_pa,
> +		       thread->base + CMDQ_THR_CURR_ADDR);
> +		writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa,
>  		       thread->base + CMDQ_THR_END_ADDR);
> +
>  		writel(thread->priority, thread->base + CMDQ_THR_PRIORITY);
>  		writel(CMDQ_THR_IRQ_EN, thread->base + CMDQ_THR_IRQ_ENABLE);
>  		writel(CMDQ_THR_ENABLED, thread->base + CMDQ_THR_ENABLE_TASK);
>  	} else {
>  		WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
> -		curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR);
> -		end_pa = readl(thread->base + CMDQ_THR_END_ADDR);
> +		curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) <<
> +			cmdq->shift_pa;
> +		end_pa = readl(thread->base + CMDQ_THR_END_ADDR) <<
> +			cmdq->shift_pa;
>  
>  		/*
>  		 * Atomic execution should remove the following wfe, i.e. only
> @@ -395,7 +415,7 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
>  				cmdq_thread_wait_end(thread, end_pa);
>  				WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
>  				/* set to this task directly */
> -				writel(task->pa_base,
> +				writel(task->pa_base >> cmdq->shift_pa,
>  				       thread->base + CMDQ_THR_CURR_ADDR);
>  			} else {
>  				cmdq_task_insert_into_thread(task);
> @@ -407,14 +427,14 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
>  			if (curr_pa == end_pa - CMDQ_INST_SIZE ||
>  			    curr_pa == end_pa) {
>  				/* set to this task directly */
> -				writel(task->pa_base,
> +				writel(task->pa_base >> cmdq->shift_pa,
>  				       thread->base + CMDQ_THR_CURR_ADDR);
>  			} else {
>  				cmdq_task_insert_into_thread(task);
>  				smp_mb(); /* modify jump before enable thread */
>  			}
>  		}
> -		writel(task->pa_base + pkt->cmd_buf_size,
> +		writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa,
>  		       thread->base + CMDQ_THR_END_ADDR);
>  		cmdq_thread_resume(thread);
>  	}
> @@ -461,6 +481,7 @@ static int cmdq_probe(struct platform_device *pdev)
>  	struct resource *res;
>  	struct cmdq *cmdq;
>  	int err, i;
> +	struct gce_plat *plat_data;
>  
>  	cmdq = devm_kzalloc(dev, sizeof(*cmdq), GFP_KERNEL);
>  	if (!cmdq)
> @@ -479,7 +500,14 @@ static int cmdq_probe(struct platform_device *pdev)
>  		return -EINVAL;
>  	}
>  
> -	cmdq->thread_nr = (u32)(unsigned long)of_device_get_match_data(dev);
> +	plat_data = (struct gce_plat *)of_device_get_match_data(dev);
> +	if (!plat_data) {
> +		dev_err(dev, "failed to get match data\n");
> +		return -EINVAL;
> +	}
> +
> +	cmdq->thread_nr = plat_data->thread_nr;
> +	cmdq->shift_pa = plat_data->shift;
>  	cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
>  	err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
>  			       "mtk_cmdq", cmdq);
> @@ -542,9 +570,12 @@ static int cmdq_probe(struct platform_device *pdev)
>  	.resume = cmdq_resume,
>  };
>  
> +static const struct gce_plat gce_plat_v2 = {.thread_nr = 16};
> +static const struct gce_plat gce_plat_v3 = {.thread_nr = 24};
> +
>  static const struct of_device_id cmdq_of_ids[] = {
> -	{.compatible = "mediatek,mt8173-gce", .data = (void *)16},
> -	{.compatible = "mediatek,mt8183-gce", .data = (void *)24},
> +	{.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_v2},
> +	{.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_v3},
>  	{}
>  };
>  
> diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h
> index a4dc45fbec0a..dfe5b2eb85cc 100644
> --- a/include/linux/mailbox/mtk-cmdq-mailbox.h
> +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h
> @@ -88,4 +88,6 @@ struct cmdq_pkt {
>  	void			*cl;
>  };
>  
> +u8 cmdq_mbox_shift(struct mbox_chan *chan);
> +
>  #endif /* __MTK_CMDQ_MAILBOX_H__ */

Re: [PATCH v7 2/4] mailbox: cmdq: variablize address shift in platform

[Dennis-YC Hsieh]

Hi Bibby,

Thanks for your comment.

On Mon, 2020-06-22 at 10:33 +0800, Bibby Hsieh wrote:
> On Sun, 2020-06-21 at 21:22 +0800, Dennis YC Hsieh wrote:
> > Some gce hardware shift pc and end address in register to support
> > large dram addressing.
> > Implement gce address shift when write or read pc and end register.
> > And add shift bit in platform definition.
> > 
> > Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com>
> > ---
> >  drivers/mailbox/mtk-cmdq-mailbox.c       |   61 ++++++++++++++++++++++--------
> >  include/linux/mailbox/mtk-cmdq-mailbox.h |    2 +
> >  2 files changed, 48 insertions(+), 15 deletions(-)
> > 
> > diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
> > index 9a6ce9f5a7db..4dbee9258127 100644
> > --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> > +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> > @@ -76,8 +76,22 @@ struct cmdq {
> >  	struct cmdq_thread	*thread;
> >  	struct clk		*clock;
> >  	bool			suspended;
> > +	u8			shift_pa;
> >  };
> >  
> > +struct gce_plat {
> > +	u32 thread_nr;
> > +	u8 shift;
> > +};
> > +
> > +u8 cmdq_mbox_shift(struct mbox_chan *chan)
> 
> How about rename this function as cmdq_get_shift_pa()?

ok, I'll rename it, thanks


Regards,
Dennis


> 
> 
> Bibby
> 
> > +{
> > +	struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox);
> > +
> > +	return cmdq->shift_pa;
> > +}
> > +EXPORT_SYMBOL(cmdq_mbox_shift);
> > +
> >  static int cmdq_thread_suspend(struct cmdq *cmdq, struct cmdq_thread *thread)
> >  {
> >  	u32 status;
> > @@ -183,7 +197,7 @@ static void cmdq_task_remove_wfe(struct cmdq_task *task)
> >  	for (i = 0; i < CMDQ_NUM_CMD(task->pkt); i++)
> >  		if (cmdq_command_is_wfe(base[i]))
> >  			base[i] = (u64)CMDQ_JUMP_BY_OFFSET << 32 |
> > -				  CMDQ_JUMP_PASS;
> > +				  CMDQ_JUMP_PASS >> task->cmdq->shift_pa;
> >  	dma_sync_single_for_device(dev, task->pa_base, task->pkt->cmd_buf_size,
> >  				   DMA_TO_DEVICE);
> >  }
> > @@ -221,13 +235,15 @@ static void cmdq_task_handle_error(struct cmdq_task *task)
> >  {
> >  	struct cmdq_thread *thread = task->thread;
> >  	struct cmdq_task *next_task;
> > +	struct cmdq *cmdq = task->cmdq;
> >  
> > -	dev_err(task->cmdq->mbox.dev, "task 0x%p error\n", task);
> > -	WARN_ON(cmdq_thread_suspend(task->cmdq, thread) < 0);
> > +	dev_err(cmdq->mbox.dev, "task 0x%p error\n", task);
> > +	WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
> >  	next_task = list_first_entry_or_null(&thread->task_busy_list,
> >  			struct cmdq_task, list_entry);
> >  	if (next_task)
> > -		writel(next_task->pa_base, thread->base + CMDQ_THR_CURR_ADDR);
> > +		writel(next_task->pa_base >> cmdq->shift_pa,
> > +		       thread->base + CMDQ_THR_CURR_ADDR);
> >  	cmdq_thread_resume(thread);
> >  }
> >  
> > @@ -257,7 +273,7 @@ static void cmdq_thread_irq_handler(struct cmdq *cmdq,
> >  	else
> >  		return;
> >  
> > -	curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR);
> > +	curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) << cmdq->shift_pa;
> >  
> >  	list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
> >  				 list_entry) {
> > @@ -373,16 +389,20 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
> >  		WARN_ON(clk_enable(cmdq->clock) < 0);
> >  		WARN_ON(cmdq_thread_reset(cmdq, thread) < 0);
> >  
> > -		writel(task->pa_base, thread->base + CMDQ_THR_CURR_ADDR);
> > -		writel(task->pa_base + pkt->cmd_buf_size,
> > +		writel(task->pa_base >> cmdq->shift_pa,
> > +		       thread->base + CMDQ_THR_CURR_ADDR);
> > +		writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa,
> >  		       thread->base + CMDQ_THR_END_ADDR);
> > +
> >  		writel(thread->priority, thread->base + CMDQ_THR_PRIORITY);
> >  		writel(CMDQ_THR_IRQ_EN, thread->base + CMDQ_THR_IRQ_ENABLE);
> >  		writel(CMDQ_THR_ENABLED, thread->base + CMDQ_THR_ENABLE_TASK);
> >  	} else {
> >  		WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
> > -		curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR);
> > -		end_pa = readl(thread->base + CMDQ_THR_END_ADDR);
> > +		curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) <<
> > +			cmdq->shift_pa;
> > +		end_pa = readl(thread->base + CMDQ_THR_END_ADDR) <<
> > +			cmdq->shift_pa;
> >  
> >  		/*
> >  		 * Atomic execution should remove the following wfe, i.e. only
> > @@ -395,7 +415,7 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
> >  				cmdq_thread_wait_end(thread, end_pa);
> >  				WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
> >  				/* set to this task directly */
> > -				writel(task->pa_base,
> > +				writel(task->pa_base >> cmdq->shift_pa,
> >  				       thread->base + CMDQ_THR_CURR_ADDR);
> >  			} else {
> >  				cmdq_task_insert_into_thread(task);
> > @@ -407,14 +427,14 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
> >  			if (curr_pa == end_pa - CMDQ_INST_SIZE ||
> >  			    curr_pa == end_pa) {
> >  				/* set to this task directly */
> > -				writel(task->pa_base,
> > +				writel(task->pa_base >> cmdq->shift_pa,
> >  				       thread->base + CMDQ_THR_CURR_ADDR);
> >  			} else {
> >  				cmdq_task_insert_into_thread(task);
> >  				smp_mb(); /* modify jump before enable thread */
> >  			}
> >  		}
> > -		writel(task->pa_base + pkt->cmd_buf_size,
> > +		writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa,
> >  		       thread->base + CMDQ_THR_END_ADDR);
> >  		cmdq_thread_resume(thread);
> >  	}
> > @@ -461,6 +481,7 @@ static int cmdq_probe(struct platform_device *pdev)
> >  	struct resource *res;
> >  	struct cmdq *cmdq;
> >  	int err, i;
> > +	struct gce_plat *plat_data;
> >  
> >  	cmdq = devm_kzalloc(dev, sizeof(*cmdq), GFP_KERNEL);
> >  	if (!cmdq)
> > @@ -479,7 +500,14 @@ static int cmdq_probe(struct platform_device *pdev)
> >  		return -EINVAL;
> >  	}
> >  
> > -	cmdq->thread_nr = (u32)(unsigned long)of_device_get_match_data(dev);
> > +	plat_data = (struct gce_plat *)of_device_get_match_data(dev);
> > +	if (!plat_data) {
> > +		dev_err(dev, "failed to get match data\n");
> > +		return -EINVAL;
> > +	}
> > +
> > +	cmdq->thread_nr = plat_data->thread_nr;
> > +	cmdq->shift_pa = plat_data->shift;
> >  	cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
> >  	err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
> >  			       "mtk_cmdq", cmdq);
> > @@ -542,9 +570,12 @@ static int cmdq_probe(struct platform_device *pdev)
> >  	.resume = cmdq_resume,
> >  };
> >  
> > +static const struct gce_plat gce_plat_v2 = {.thread_nr = 16};
> > +static const struct gce_plat gce_plat_v3 = {.thread_nr = 24};
> > +
> >  static const struct of_device_id cmdq_of_ids[] = {
> > -	{.compatible = "mediatek,mt8173-gce", .data = (void *)16},
> > -	{.compatible = "mediatek,mt8183-gce", .data = (void *)24},
> > +	{.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_v2},
> > +	{.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_v3},
> >  	{}
> >  };
> >  
> > diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h
> > index a4dc45fbec0a..dfe5b2eb85cc 100644
> > --- a/include/linux/mailbox/mtk-cmdq-mailbox.h
> > +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h
> > @@ -88,4 +88,6 @@ struct cmdq_pkt {
> >  	void			*cl;
> >  };
> >  
> > +u8 cmdq_mbox_shift(struct mbox_chan *chan);
> > +
> >  #endif /* __MTK_CMDQ_MAILBOX_H__ */
> 
> 

[PATCH v7 3/4] mailbox: cmdq: support mt6779 gce platform definition

[Dennis YC Hsieh]

Add gce v4 hardware support with different thread number and shift.

Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
---
 drivers/mailbox/mtk-cmdq-mailbox.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index 4dbee9258127..9994ac9426d6 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -572,10 +572,12 @@ static int cmdq_probe(struct platform_device *pdev)
 
 static const struct gce_plat gce_plat_v2 = {.thread_nr = 16};
 static const struct gce_plat gce_plat_v3 = {.thread_nr = 24};
+static const struct gce_plat gce_plat_v4 = {.thread_nr = 24, .shift = 3};
 
 static const struct of_device_id cmdq_of_ids[] = {
 	{.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_v2},
 	{.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_v3},
+	{.compatible = "mediatek,mt6779-gce", .data = (void *)&gce_plat_v4},
 	{}
 };
 
-- 
1.7.9.5

Re: [PATCH v7 3/4] mailbox: cmdq: support mt6779 gce platform definition

[Bibby Hsieh]

Reviewed-by: Bibby Hsieh <bibby.hsieh@mediatek.com>

Thanks.

On Sun, 2020-06-21 at 21:22 +0800, Dennis YC Hsieh wrote:
> Add gce v4 hardware support with different thread number and shift.
> 
> Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
> ---
>  drivers/mailbox/mtk-cmdq-mailbox.c |    2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
> index 4dbee9258127..9994ac9426d6 100644
> --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> @@ -572,10 +572,12 @@ static int cmdq_probe(struct platform_device *pdev)
>  
>  static const struct gce_plat gce_plat_v2 = {.thread_nr = 16};
>  static const struct gce_plat gce_plat_v3 = {.thread_nr = 24};
> +static const struct gce_plat gce_plat_v4 = {.thread_nr = 24, .shift = 3};
>  
>  static const struct of_device_id cmdq_of_ids[] = {
>  	{.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_v2},
>  	{.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_v3},
> +	{.compatible = "mediatek,mt6779-gce", .data = (void *)&gce_plat_v4},
>  	{}
>  };
>  

[PATCH v7 4/4] mailbox: mediatek: cmdq: clear task in channel before shutdown

[Dennis YC Hsieh]

Do success callback in channel when shutdown. For those task not finish,
callback with error code thus client has chance to cleanup or reset.

Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
 drivers/mailbox/mtk-cmdq-mailbox.c |   38 ++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index 9994ac9426d6..b56d340c8982 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -387,6 +387,12 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
 
 	if (list_empty(&thread->task_busy_list)) {
 		WARN_ON(clk_enable(cmdq->clock) < 0);
+		/*
+		 * The thread reset will clear thread related register to 0,
+		 * including pc, end, priority, irq, suspend and enable. Thus
+		 * set CMDQ_THR_ENABLED to CMDQ_THR_ENABLE_TASK will enable
+		 * thread and make it running.
+		 */
 		WARN_ON(cmdq_thread_reset(cmdq, thread) < 0);
 
 		writel(task->pa_base >> cmdq->shift_pa,
@@ -450,6 +456,38 @@ static int cmdq_mbox_startup(struct mbox_chan *chan)
 
 static void cmdq_mbox_shutdown(struct mbox_chan *chan)
 {
+	struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv;
+	struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
+	struct cmdq_task *task, *tmp;
+	unsigned long flags;
+
+	spin_lock_irqsave(&thread->chan->lock, flags);
+	if (list_empty(&thread->task_busy_list))
+		goto done;
+
+	WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
+
+	/* make sure executed tasks have success callback */
+	cmdq_thread_irq_handler(cmdq, thread);
+	if (list_empty(&thread->task_busy_list))
+		goto done;
+
+	list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
+				 list_entry) {
+		cmdq_task_exec_done(task, CMDQ_CB_ERROR);
+		kfree(task);
+	}
+
+	cmdq_thread_disable(cmdq, thread);
+	clk_disable(cmdq->clock);
+done:
+	/*
+	 * The thread->task_busy_list empty means thread already disable. The
+	 * cmdq_mbox_send_data() always reset thread which clear disable and
+	 * suspend statue when first pkt send to channel, so there is no need
+	 * to do any operation here, only unlock and leave.
+	 */
+	spin_unlock_irqrestore(&thread->chan->lock, flags);
 }
 
 static const struct mbox_chan_ops cmdq_mbox_chan_ops = {
-- 
1.7.9.5

Re: [PATCH v7 4/4] mailbox: mediatek: cmdq: clear task in channel before shutdown

[Bibby Hsieh]

Reviewed-by: Bibby Hsieh <bibby.hsieh@mediatek.com>

Thanks.

On Sun, 2020-06-21 at 21:22 +0800, Dennis YC Hsieh wrote:
> Do success callback in channel when shutdown. For those task not finish,
> callback with error code thus client has chance to cleanup or reset.
> 
> Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> ---
>  drivers/mailbox/mtk-cmdq-mailbox.c |   38 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 38 insertions(+)
> 
> diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
> index 9994ac9426d6..b56d340c8982 100644
> --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> @@ -387,6 +387,12 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
>  
>  	if (list_empty(&thread->task_busy_list)) {
>  		WARN_ON(clk_enable(cmdq->clock) < 0);
> +		/*
> +		 * The thread reset will clear thread related register to 0,
> +		 * including pc, end, priority, irq, suspend and enable. Thus
> +		 * set CMDQ_THR_ENABLED to CMDQ_THR_ENABLE_TASK will enable
> +		 * thread and make it running.
> +		 */
>  		WARN_ON(cmdq_thread_reset(cmdq, thread) < 0);
>  
>  		writel(task->pa_base >> cmdq->shift_pa,
> @@ -450,6 +456,38 @@ static int cmdq_mbox_startup(struct mbox_chan *chan)
>  
>  static void cmdq_mbox_shutdown(struct mbox_chan *chan)
>  {
> +	struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv;
> +	struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
> +	struct cmdq_task *task, *tmp;
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&thread->chan->lock, flags);
> +	if (list_empty(&thread->task_busy_list))
> +		goto done;
> +
> +	WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
> +
> +	/* make sure executed tasks have success callback */
> +	cmdq_thread_irq_handler(cmdq, thread);
> +	if (list_empty(&thread->task_busy_list))
> +		goto done;
> +
> +	list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
> +				 list_entry) {
> +		cmdq_task_exec_done(task, CMDQ_CB_ERROR);
> +		kfree(task);
> +	}
> +
> +	cmdq_thread_disable(cmdq, thread);
> +	clk_disable(cmdq->clock);
> +done:
> +	/*
> +	 * The thread->task_busy_list empty means thread already disable. The
> +	 * cmdq_mbox_send_data() always reset thread which clear disable and
> +	 * suspend statue when first pkt send to channel, so there is no need
> +	 * to do any operation here, only unlock and leave.
> +	 */
> +	spin_unlock_irqrestore(&thread->chan->lock, flags);
>  }
>  
>  static const struct mbox_chan_ops cmdq_mbox_chan_ops = {