* [PATCH] clk: qcom: ipq8074: Add correct index for PCIe clocks
@ 2020-07-16 5:32 Sivaprakash Murugesan
2020-07-21 0:39 ` Stephen Boyd
0 siblings, 1 reply; 2+ messages in thread
From: Sivaprakash Murugesan @ 2020-07-16 5:32 UTC (permalink / raw)
To: agross, bjorn.andersson, robh+dt, mturquette, sboyd, p.zabel,
linux-arm-msm, linux-clk, devicetree, linux-kernel
Cc: Sivaprakash Murugesan
The PCIe clocks GCC_PCIE0_AXI_S_BRIDGE_CLK, GCC_PCIE0_RCHNG_CLK_SRC,
GCC_PCIE0_RCHNG_CLK are wrongly added to the gcc reset group.
Move them to the gcc clock group.
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
---
include/dt-bindings/clock/qcom,gcc-ipq8074.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
index e3e018565add..8e2bec1c91bf 100644
--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
@@ -230,6 +230,9 @@
#define GCC_GP1_CLK 221
#define GCC_GP2_CLK 222
#define GCC_GP3_CLK 223
+#define GCC_PCIE0_AXI_S_BRIDGE_CLK 224
+#define GCC_PCIE0_RCHNG_CLK_SRC 225
+#define GCC_PCIE0_RCHNG_CLK 226
#define GCC_BLSP1_BCR 0
#define GCC_BLSP1_QUP1_BCR 1
@@ -363,8 +366,5 @@
#define GCC_PCIE1_AHB_ARES 129
#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130
#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131
-#define GCC_PCIE0_AXI_S_BRIDGE_CLK 132
-#define GCC_PCIE0_RCHNG_CLK_SRC 133
-#define GCC_PCIE0_RCHNG_CLK 134
#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] clk: qcom: ipq8074: Add correct index for PCIe clocks
2020-07-16 5:32 [PATCH] clk: qcom: ipq8074: Add correct index for PCIe clocks Sivaprakash Murugesan
@ 2020-07-21 0:39 ` Stephen Boyd
0 siblings, 0 replies; 2+ messages in thread
From: Stephen Boyd @ 2020-07-21 0:39 UTC (permalink / raw)
To: Sivaprakash Murugesan, agross, bjorn.andersson, devicetree,
linux-arm-msm, linux-clk, linux-kernel, mturquette, p.zabel,
robh+dt
Cc: Sivaprakash Murugesan
Quoting Sivaprakash Murugesan (2020-07-15 22:32:50)
> The PCIe clocks GCC_PCIE0_AXI_S_BRIDGE_CLK, GCC_PCIE0_RCHNG_CLK_SRC,
> GCC_PCIE0_RCHNG_CLK are wrongly added to the gcc reset group.
>
> Move them to the gcc clock group.
>
> Reported-by: kernel test robot <lkp@intel.com>
> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 2+ messages in thread
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2020-07-21 0:39 ` Stephen Boyd
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