* [PATCH] coresight: etm4x: Modify core-commit of cpu to avoid the overflow of HiSilicon ETM
@ 2020-08-03 13:40 Qi Liu
0 siblings, 0 replies; 6+ messages in thread
From: Qi Liu @ 2020-08-03 13:40 UTC (permalink / raw)
To: gregkh, saiprakash.ranjan, suzuki.poulose
Cc: linux-arm-kernel, linux-kernel, linuxarm
When too much trace information is generated on-chip, the ETM will
overflow, and may cause data loss. This is a common phenomenon on
ETM devices.
But sometimes we do not want to lose any performance trace data, so
we suppress the speed of instructions sent from CPU core to ETM to
avoid the overflow of ETM.
Signed-off-by: Qi Liu <liuqi115@huawei.com>
---
drivers/hwtracing/coresight/coresight-etm4x.c | 46 +++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
index 4a4f0bd..ca9fb11 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -43,6 +43,11 @@ MODULE_PARM_DESC(boot_enable, "Enable tracing on boot");
#define PARAM_PM_SAVE_NEVER 1 /* never save any state */
#define PARAM_PM_SAVE_SELF_HOSTED 2 /* save self-hosted state only */
+#define CORE_COMMIT_CLEAR 0x3000
+#define CORE_COMMIT_SHIFT 12
+#define HISI_ETM_AMBA_ID_V1 0x000b6d01
+#define HISI_ETM_AMBA_ID_V2 0x000b6d02
+
static int pm_save_enable = PARAM_PM_SAVE_FIRMWARE;
module_param(pm_save_enable, int, 0444);
MODULE_PARM_DESC(pm_save_enable,
@@ -104,11 +109,41 @@ struct etm4_enable_arg {
int rc;
};
+static void etm4_cpu_actlr1_cfg(void *info)
+{
+ struct etm4_enable_arg *arg = (struct etm4_enable_arg *)info;
+ u64 val;
+
+ asm volatile("mrs %0,s3_1_c15_c2_5" : "=r"(val));
+ val &= ~CORE_COMMIT_CLEAR;
+ val |= arg->rc << CORE_COMMIT_SHIFT;
+ asm volatile("msr s3_1_c15_c2_5,%0" : : "r"(val));
+}
+
+static void etm4_config_core_commit(int cpu, int val)
+{
+ struct etm4_enable_arg arg = {0};
+
+ arg.rc = val;
+ smp_call_function_single(cpu, etm4_cpu_actlr1_cfg, &arg, 1);
+}
+
static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
{
int i, rc;
+ struct amba_device *adev;
struct etmv4_config *config = &drvdata->config;
struct device *etm_dev = &drvdata->csdev->dev;
+ struct device *dev = drvdata->csdev->dev.parent;
+
+ adev = container_of(dev, struct amba_device, dev);
+ /*
+ * If ETM device is HiSilicon ETM device, reduce the
+ * core-commit to avoid ETM overflow.
+ */
+ if (adev->periphid == HISI_ETM_AMBA_ID_V1 ||
+ adev->periphid == HISI_ETM_AMBA_ID_V2)
+ etm4_config_core_commit(drvdata->cpu, 1);
CS_UNLOCK(drvdata->base);
@@ -469,11 +504,22 @@ static int etm4_enable(struct coresight_device *csdev,
static void etm4_disable_hw(void *info)
{
u32 control;
+ struct amba_device *adev;
struct etmv4_drvdata *drvdata = info;
struct etmv4_config *config = &drvdata->config;
struct device *etm_dev = &drvdata->csdev->dev;
+ struct device *dev = drvdata->csdev->dev.parent;
int i;
+ adev = container_of(dev, struct amba_device, dev);
+ /*
+ * If ETM device is HiSilicon ETM device, resume the
+ * core-commit after ETM trace is complete.
+ */
+ if (adev->periphid == HISI_ETM_AMBA_ID_V1 ||
+ adev->periphid == HISI_ETM_AMBA_ID_V2)
+ etm4_config_core_commit(drvdata->cpu, 0);
+
CS_UNLOCK(drvdata->base);
/* power can be removed from the trace unit now */
--
2.8.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] coresight: etm4x: Modify core-commit of cpu to avoid the overflow of HiSilicon ETM
2020-11-23 14:12 ` Suzuki K Poulose
@ 2020-11-26 13:38 ` Qi Liu
0 siblings, 0 replies; 6+ messages in thread
From: Qi Liu @ 2020-11-26 13:38 UTC (permalink / raw)
To: Suzuki K Poulose, mathieu.poirier, mike.leach
Cc: coresight, linux-kernel, linux-arm-kernel, linuxarm
On 2020/11/23 22:12, Suzuki K Poulose wrote:
> Hi Qi
>
> Thanks for the changes. Mostly looks good to me, except for the
> name of the call back.
>
>
Hi Suzuki,
ok, I'll send a new patch to change the name of call back.
Thanks
Qi
> On 11/23/20 1:29 PM, Qi Liu wrote:
>> The ETM device can't keep up with the core pipeline when cpu core
>> is at full speed. This may cause overflow within core and its ETM.
>> This is a common phenomenon on ETM devices.
>>
>> On HiSilicon Hip08 platform, a specific feature is added to set
>> core pipeline. So commit rate can be reduced manually to avoid ETM
>> overflow.
>>
>> Signed-off-by: Qi Liu <liuqi115@huawei.com>
>
>
>> ---
>> Change since v1:
>> - add CONFIG_ETM4X_IMPDEF_FEATURE and CONFIG_ETM4X_IMPDEF_HISILICON
>> to keep specific feature off platforms which don't use it.
>> Change since v2:
>> - remove some unused variable.
>> Change since v3:
>> - use read/write_sysreg_s() to access register.
>>
>> drivers/hwtracing/coresight/Kconfig | 9 +++
>> drivers/hwtracing/coresight/coresight-etm4x-core.c | 84 ++++++++++++++++++++++
>> drivers/hwtracing/coresight/coresight-etm4x.h | 12 ++++
>> 3 files changed, 105 insertions(+)
>>
>
>>
>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
>> index eefc737..1784975 100644
>> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
>> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
>> @@ -8,6 +8,7 @@
>>
>> #include <asm/local.h>
>> #include <linux/spinlock.h>
>> +#include <linux/types.h>
>> #include "coresight-priv.h"
>>
>> /*
>> @@ -203,6 +204,11 @@
>> /* Interpretation of resource numbers change at ETM v4.3 architecture */
>> #define ETM4X_ARCH_4V3 0x43
>>
>> +enum etm_impdef_type {
>> + ETM4_IMPDEF_HISI_CORE_COMMIT,
>> + ETM4_IMPDEF_FEATURE_MAX,
>> +};
>> +
>> /**
>> * struct etmv4_config - configuration information related to an ETMv4
>> * @mode: Controls various modes supported by this ETM.
>> @@ -415,6 +421,7 @@ struct etmv4_save_state {
>> * @state_needs_restore: True when there is context to restore after PM exit
>> * @skip_power_up: Indicates if an implementation can skip powering up
>> * the trace unit.
>> + * @arch_features: Bitmap of arch features of etmv4 devices.
>> */
>> struct etmv4_drvdata {
>> void __iomem *base;
>> @@ -463,6 +470,11 @@ struct etmv4_drvdata {
>> struct etmv4_save_state *save_state;
>> bool state_needs_restore;
>> bool skip_power_up;
>> + DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX);
>> +};
>> +
>> +struct etm4_arch_features {
>> + void (*set_commit)(bool enable);
>
> The set_commit is too hisilicon specific :-). Could we please rename
> this to soemthing more generic. The callback for hisilicon etms, could still
> be xx_commit". May be simply call it
>
> callback() ?
>
> or may be even
> arch_callback() ?
>
>
>> };
>
> nit: This need not be part of the header file, as it is not used
> outside the etm4x-core.c
>
> Suzuki
>
> .
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] coresight: etm4x: Modify core-commit of cpu to avoid the overflow of HiSilicon ETM
2020-11-23 13:29 Qi Liu
2020-11-23 14:12 ` Suzuki K Poulose
@ 2020-11-24 1:00 ` kernel test robot
1 sibling, 0 replies; 6+ messages in thread
From: kernel test robot @ 2020-11-24 1:00 UTC (permalink / raw)
To: Qi Liu, mathieu.poirier, suzuki.poulose, mike.leach
Cc: kbuild-all, coresight, linux-kernel, linux-arm-kernel, linuxarm
[-- Attachment #1: Type: text/plain, Size: 2106 bytes --]
Hi Qi,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on linus/master]
[also build test WARNING on v5.10-rc5 next-20201123]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Qi-Liu/coresight-etm4x-Modify-core-commit-of-cpu-to-avoid-the-overflow-of-HiSilicon-ETM/20201123-213732
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 418baf2c28f3473039f2f7377760bd8f6897ae18
config: arm64-allyesconfig (attached as .config)
compiler: aarch64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/e21b077bb0d120583deb7cd6f1654d7c356175af
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Qi-Liu/coresight-etm4x-Modify-core-commit-of-cpu-to-avoid-the-overflow-of-HiSilicon-ETM/20201123-213732
git checkout e21b077bb0d120583deb7cd6f1654d7c356175af
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/hwtracing/coresight/coresight-etm4x-core.c:117:6: warning: no previous prototype for 'etm4_hisi_match_pid' [-Wmissing-prototypes]
117 | bool etm4_hisi_match_pid(unsigned int id)
| ^~~~~~~~~~~~~~~~~~~
vim +/etm4_hisi_match_pid +117 drivers/hwtracing/coresight/coresight-etm4x-core.c
116
> 117 bool etm4_hisi_match_pid(unsigned int id)
118 {
119 return (id & ETM4_AMBA_MASK) == HISI_HIP08_AMBA_ID;
120 }
121
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 75510 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] coresight: etm4x: Modify core-commit of cpu to avoid the overflow of HiSilicon ETM
2020-11-23 13:29 Qi Liu
@ 2020-11-23 14:12 ` Suzuki K Poulose
2020-11-26 13:38 ` Qi Liu
2020-11-24 1:00 ` kernel test robot
1 sibling, 1 reply; 6+ messages in thread
From: Suzuki K Poulose @ 2020-11-23 14:12 UTC (permalink / raw)
To: Qi Liu, mathieu.poirier, mike.leach
Cc: coresight, linux-kernel, linux-arm-kernel, linuxarm
Hi Qi
Thanks for the changes. Mostly looks good to me, except for the
name of the call back.
On 11/23/20 1:29 PM, Qi Liu wrote:
> The ETM device can't keep up with the core pipeline when cpu core
> is at full speed. This may cause overflow within core and its ETM.
> This is a common phenomenon on ETM devices.
>
> On HiSilicon Hip08 platform, a specific feature is added to set
> core pipeline. So commit rate can be reduced manually to avoid ETM
> overflow.
>
> Signed-off-by: Qi Liu <liuqi115@huawei.com>
> ---
> Change since v1:
> - add CONFIG_ETM4X_IMPDEF_FEATURE and CONFIG_ETM4X_IMPDEF_HISILICON
> to keep specific feature off platforms which don't use it.
> Change since v2:
> - remove some unused variable.
> Change since v3:
> - use read/write_sysreg_s() to access register.
>
> drivers/hwtracing/coresight/Kconfig | 9 +++
> drivers/hwtracing/coresight/coresight-etm4x-core.c | 84 ++++++++++++++++++++++
> drivers/hwtracing/coresight/coresight-etm4x.h | 12 ++++
> 3 files changed, 105 insertions(+)
>
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> index eefc737..1784975 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -8,6 +8,7 @@
>
> #include <asm/local.h>
> #include <linux/spinlock.h>
> +#include <linux/types.h>
> #include "coresight-priv.h"
>
> /*
> @@ -203,6 +204,11 @@
> /* Interpretation of resource numbers change at ETM v4.3 architecture */
> #define ETM4X_ARCH_4V3 0x43
>
> +enum etm_impdef_type {
> + ETM4_IMPDEF_HISI_CORE_COMMIT,
> + ETM4_IMPDEF_FEATURE_MAX,
> +};
> +
> /**
> * struct etmv4_config - configuration information related to an ETMv4
> * @mode: Controls various modes supported by this ETM.
> @@ -415,6 +421,7 @@ struct etmv4_save_state {
> * @state_needs_restore: True when there is context to restore after PM exit
> * @skip_power_up: Indicates if an implementation can skip powering up
> * the trace unit.
> + * @arch_features: Bitmap of arch features of etmv4 devices.
> */
> struct etmv4_drvdata {
> void __iomem *base;
> @@ -463,6 +470,11 @@ struct etmv4_drvdata {
> struct etmv4_save_state *save_state;
> bool state_needs_restore;
> bool skip_power_up;
> + DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX);
> +};
> +
> +struct etm4_arch_features {
> + void (*set_commit)(bool enable);
The set_commit is too hisilicon specific :-). Could we please rename
this to soemthing more generic. The callback for hisilicon etms, could still
be xx_commit". May be simply call it
callback() ?
or may be even
arch_callback() ?
> };
nit: This need not be part of the header file, as it is not used
outside the etm4x-core.c
Suzuki
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] coresight: etm4x: Modify core-commit of cpu to avoid the overflow of HiSilicon ETM
@ 2020-11-23 13:29 Qi Liu
2020-11-23 14:12 ` Suzuki K Poulose
2020-11-24 1:00 ` kernel test robot
0 siblings, 2 replies; 6+ messages in thread
From: Qi Liu @ 2020-11-23 13:29 UTC (permalink / raw)
To: mathieu.poirier, suzuki.poulose, mike.leach
Cc: coresight, linux-kernel, linux-arm-kernel, linuxarm
The ETM device can't keep up with the core pipeline when cpu core
is at full speed. This may cause overflow within core and its ETM.
This is a common phenomenon on ETM devices.
On HiSilicon Hip08 platform, a specific feature is added to set
core pipeline. So commit rate can be reduced manually to avoid ETM
overflow.
Signed-off-by: Qi Liu <liuqi115@huawei.com>
---
Change since v1:
- add CONFIG_ETM4X_IMPDEF_FEATURE and CONFIG_ETM4X_IMPDEF_HISILICON
to keep specific feature off platforms which don't use it.
Change since v2:
- remove some unused variable.
Change since v3:
- use read/write_sysreg_s() to access register.
drivers/hwtracing/coresight/Kconfig | 9 +++
drivers/hwtracing/coresight/coresight-etm4x-core.c | 84 ++++++++++++++++++++++
drivers/hwtracing/coresight/coresight-etm4x.h | 12 ++++
3 files changed, 105 insertions(+)
diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
index c119824..1cc3601 100644
--- a/drivers/hwtracing/coresight/Kconfig
+++ b/drivers/hwtracing/coresight/Kconfig
@@ -110,6 +110,15 @@ config CORESIGHT_SOURCE_ETM4X
To compile this driver as a module, choose M here: the
module will be called coresight-etm4x.
+config ETM4X_IMPDEF_FEATURE
+ bool "Control overflow impdef support in CoreSight ETM 4.x driver "
+ depends on CORESIGHT_SOURCE_ETM4X
+ help
+ This control provides overflow implement define for CoreSight
+ ETM 4.x tracer module which could not reduce commit race
+ automatically, and could avoid overflow within ETM tracer module
+ and its cpu core.
+
config CORESIGHT_STM
tristate "CoreSight System Trace Macrocell driver"
depends on (ARM && !(CPU_32v3 || CPU_32v4 || CPU_32v4T)) || ARM64
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index abd706b..a1cf215 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -3,6 +3,7 @@
* Copyright (c) 2014, The Linux Foundation. All rights reserved.
*/
+#include <linux/bitops.h>
#include <linux/kernel.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
@@ -28,7 +29,9 @@
#include <linux/perf_event.h>
#include <linux/pm_runtime.h>
#include <linux/property.h>
+
#include <asm/sections.h>
+#include <asm/sysreg.h>
#include <asm/local.h>
#include <asm/virt.h>
@@ -103,6 +106,83 @@ struct etm4_enable_arg {
int rc;
};
+#ifdef CONFIG_ETM4X_IMPDEF_FEATURE
+
+#define HISI_HIP08_AMBA_ID 0x000b6d01
+#define ETM4_AMBA_MASK 0xfffff
+#define HISI_HIP08_CORE_COMMIT_CLEAR 0x3000
+#define HISI_HIP08_CORE_COMMIT_SHIFT 12
+#define HISI_HIP08_CORE_COMMIT_REG sys_reg(3, 1, 15, 2, 5)
+
+bool etm4_hisi_match_pid(unsigned int id)
+{
+ return (id & ETM4_AMBA_MASK) == HISI_HIP08_AMBA_ID;
+}
+
+static void etm4_hisi_config_core_commit(bool enable)
+{
+ u64 val;
+
+ val = read_sysreg_s(HISI_HIP08_CORE_COMMIT_REG);
+ val &= ~HISI_HIP08_CORE_COMMIT_CLEAR;
+ val |= enable << HISI_HIP08_CORE_COMMIT_SHIFT;
+ write_sysreg_s(val, HISI_HIP08_CORE_COMMIT_REG);
+}
+
+static struct etm4_arch_features etm4_features[] = {
+ [ETM4_IMPDEF_HISI_CORE_COMMIT] = {
+ .set_commit = etm4_hisi_config_core_commit,
+ },
+ {},
+};
+
+static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
+{
+ struct etm4_arch_features *ftr;
+ int bit;
+
+ for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
+ ftr = &etm4_features[bit];
+
+ if (ftr->set_commit)
+ ftr->set_commit(true);
+ }
+}
+
+static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
+{
+ struct etm4_arch_features *ftr;
+ int bit;
+
+ for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
+ ftr = &etm4_features[bit];
+
+ if (ftr->set_commit)
+ ftr->set_commit(false);
+ }
+}
+
+static void etm4x_check_arch_features(struct etmv4_drvdata *drvdata,
+ unsigned int id)
+{
+ if (etm4_hisi_match_pid(id))
+ set_bit(ETM4_IMPDEF_HISI_CORE_COMMIT, drvdata->arch_features);
+}
+#else
+static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
+{
+}
+
+static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
+{
+}
+
+static void etm4_check_arch_features(struct etmv4_drvdata drvdata,
+ unsigned int id)
+{
+}
+#endif /* CONFIG_ETM4X_IMPDEF_FEATURE */
+
static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
{
int i, rc;
@@ -110,6 +190,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
struct device *etm_dev = &drvdata->csdev->dev;
CS_UNLOCK(drvdata->base);
+ etm4_enable_arch_specific(drvdata);
etm4_os_unlock(drvdata);
@@ -476,6 +557,7 @@ static void etm4_disable_hw(void *info)
int i;
CS_UNLOCK(drvdata->base);
+ etm4_disable_arch_specific(drvdata);
if (!drvdata->skip_power_up) {
/* power can be removed from the trace unit now */
@@ -1547,6 +1629,8 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
drvdata->boot_enable = true;
}
+ etm4x_check_arch_features(drvdata, id->id);
+
return 0;
}
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index eefc737..1784975 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -8,6 +8,7 @@
#include <asm/local.h>
#include <linux/spinlock.h>
+#include <linux/types.h>
#include "coresight-priv.h"
/*
@@ -203,6 +204,11 @@
/* Interpretation of resource numbers change at ETM v4.3 architecture */
#define ETM4X_ARCH_4V3 0x43
+enum etm_impdef_type {
+ ETM4_IMPDEF_HISI_CORE_COMMIT,
+ ETM4_IMPDEF_FEATURE_MAX,
+};
+
/**
* struct etmv4_config - configuration information related to an ETMv4
* @mode: Controls various modes supported by this ETM.
@@ -415,6 +421,7 @@ struct etmv4_save_state {
* @state_needs_restore: True when there is context to restore after PM exit
* @skip_power_up: Indicates if an implementation can skip powering up
* the trace unit.
+ * @arch_features: Bitmap of arch features of etmv4 devices.
*/
struct etmv4_drvdata {
void __iomem *base;
@@ -463,6 +470,11 @@ struct etmv4_drvdata {
struct etmv4_save_state *save_state;
bool state_needs_restore;
bool skip_power_up;
+ DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX);
+};
+
+struct etm4_arch_features {
+ void (*set_commit)(bool enable);
};
/* Address comparator access types */
--
2.8.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] coresight: etm4x: Modify core-commit of cpu to avoid the overflow of HiSilicon ETM
@ 2020-09-03 11:37 Qi Liu
0 siblings, 0 replies; 6+ messages in thread
From: Qi Liu @ 2020-09-03 11:37 UTC (permalink / raw)
To: mathieu.poirier, suzuki.poulose, Al.Grant
Cc: linux-arm-kernel, linux-kernel, linuxarm
The ETM device can't keep up with the core pipeline when cpu core
is at full speed. This may cause overflow within core and its ETM.
This is a common phenomenon on ETM devices.
On HiSilicon Hip08 platform, a specific feature is added to set
core pipeline. So commit rate can be reduced manually to avoid ETM
overflow.
Signed-off-by: Qi Liu <liuqi115@huawei.com>
---
link of the RFC patch:
https://lore.kernel.org/linux-arm-kernel/1597824397-29894-1-git-send-email-liuqi115@huawei.com/
drivers/hwtracing/coresight/coresight-etm4x.c | 46 +++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
index 7bcac88..5833be1 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -45,6 +45,10 @@ static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
static enum cpuhp_state hp_online;
+#define HISI_HIP08_CORE_COMMIT_CLEAR 0x3000
+#define HISI_HIP08_CORE_COMMIT_SHIFT 12
+#define HISI_HIP08_ETM_ID 0x000b6d01
+
static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
{
/* Writing any value to ETMOSLAR unlocks the trace registers */
@@ -84,12 +88,38 @@ struct etm4_enable_arg {
int rc;
};
+static void etm4_hisi_config_core_commit(int flag)
+{
+ u64 val;
+
+ asm volatile("mrs %0,s3_1_c15_c2_5" : "=r"(val));
+ val &= ~HISI_HIP08_CORE_COMMIT_CLEAR;
+ val |= flag << HISI_HIP08_CORE_COMMIT_SHIFT;
+ asm volatile("msr s3_1_c15_c2_5,%0" : : "r"(val));
+}
+
+static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
+{
+ struct device *dev = drvdata->csdev->dev.parent;
+ struct amba_device *adev;
+
+ adev = container_of(dev, struct amba_device, dev);
+
+ /*
+ * If ETM device is HiSilicon ETM device, reduce the
+ * core-commit to avoid ETM overflow.
+ */
+ if (adev->periphid == HISI_HIP08_ETM_ID)
+ etm4_hisi_config_core_commit(1);
+}
+
static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
{
int i, rc;
struct etmv4_config *config = &drvdata->config;
struct device *etm_dev = &drvdata->csdev->dev;
+ etm4_enable_arch_specific(drvdata);
CS_UNLOCK(drvdata->base);
etm4_os_unlock(drvdata);
@@ -436,11 +466,27 @@ static int etm4_enable(struct coresight_device *csdev,
return ret;
}
+static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
+{
+ struct device *dev = drvdata->csdev->dev.parent;
+ struct amba_device *adev;
+
+ adev = container_of(dev, struct amba_device, dev);
+
+ /*
+ * If ETM device is HiSilicon ETM device, resume the
+ * core-commit after ETM trace is complete.
+ */
+ if (adev->periphid == HISI_HIP08_ETM_ID)
+ etm4_hisi_config_core_commit(0);
+}
+
static void etm4_disable_hw(void *info)
{
u32 control;
struct etmv4_drvdata *drvdata = info;
+ etm4_disable_arch_specific(drvdata);
CS_UNLOCK(drvdata->base);
/* power can be removed from the trace unit now */
--
2.8.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-11-26 13:38 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-08-03 13:40 [PATCH] coresight: etm4x: Modify core-commit of cpu to avoid the overflow of HiSilicon ETM Qi Liu
2020-09-03 11:37 Qi Liu
2020-11-23 13:29 Qi Liu
2020-11-23 14:12 ` Suzuki K Poulose
2020-11-26 13:38 ` Qi Liu
2020-11-24 1:00 ` kernel test robot
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