From: "tip-bot2 for Zhang Rui" <tip-bot2@linutronix.de>
To: linux-tip-commits@vger.kernel.org
Cc: Zhang Rui <rui.zhang@intel.com>, Ingo Molnar <mingo@kernel.org>,
Kan Liang <kan.liang@linux.intel.com>,
Len Brown <len.brown@intel.com>, x86 <x86@kernel.org>,
LKML <linux-kernel@vger.kernel.org>
Subject: [tip: perf/urgent] perf/x86/rapl: Add support for Intel SPR platform
Date: Fri, 14 Aug 2020 15:23:28 -0000 [thread overview]
Message-ID: <159741860874.3192.8459468822006053326.tip-bot2@tip-bot2> (raw)
In-Reply-To: <20200811153149.12242-4-rui.zhang@intel.com>
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: bcfd218b66790243ef303c1b35ce59f786ded225
Gitweb: https://git.kernel.org/tip/bcfd218b66790243ef303c1b35ce59f786ded225
Author: Zhang Rui <rui.zhang@intel.com>
AuthorDate: Tue, 11 Aug 2020 23:31:49 +08:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Fri, 14 Aug 2020 12:35:12 +02:00
perf/x86/rapl: Add support for Intel SPR platform
Intel SPR platform uses fixed 16 bit energy unit for DRAM RAPL domain,
and fixed 0 bit energy unit for Psys RAPL domain.
After this, on SPR platform the energy counters appear in perf list.
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Acked-by: Len Brown <len.brown@intel.com>
Link: https://lore.kernel.org/r/20200811153149.12242-4-rui.zhang@intel.com
---
arch/x86/events/rapl.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c
index d0002eb..67b411f 100644
--- a/arch/x86/events/rapl.c
+++ b/arch/x86/events/rapl.c
@@ -133,6 +133,7 @@ struct rapl_pmus {
enum rapl_unit_quirk {
RAPL_UNIT_QUIRK_NONE,
RAPL_UNIT_QUIRK_INTEL_HSW,
+ RAPL_UNIT_QUIRK_INTEL_SPR,
};
struct rapl_model {
@@ -627,6 +628,14 @@ static int rapl_check_hw_unit(struct rapl_model *rm)
case RAPL_UNIT_QUIRK_INTEL_HSW:
rapl_hw_unit[PERF_RAPL_RAM] = 16;
break;
+ /*
+ * SPR shares the same DRAM domain energy unit as HSW, plus it
+ * also has a fixed energy unit for Psys domain.
+ */
+ case RAPL_UNIT_QUIRK_INTEL_SPR:
+ rapl_hw_unit[PERF_RAPL_RAM] = 16;
+ rapl_hw_unit[PERF_RAPL_PSYS] = 0;
+ break;
default:
break;
}
@@ -757,6 +766,16 @@ static struct rapl_model model_skl = {
.rapl_msrs = intel_rapl_msrs,
};
+static struct rapl_model model_spr = {
+ .events = BIT(PERF_RAPL_PP0) |
+ BIT(PERF_RAPL_PKG) |
+ BIT(PERF_RAPL_RAM) |
+ BIT(PERF_RAPL_PSYS),
+ .unit_quirk = RAPL_UNIT_QUIRK_INTEL_SPR,
+ .msr_power_unit = MSR_RAPL_POWER_UNIT,
+ .rapl_msrs = intel_rapl_msrs,
+};
+
static struct rapl_model model_amd_fam17h = {
.events = BIT(PERF_RAPL_PKG),
.msr_power_unit = MSR_AMD_RAPL_POWER_UNIT,
@@ -793,6 +812,7 @@ static const struct x86_cpu_id rapl_model_match[] __initconst = {
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &model_hsx),
X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L, &model_skl),
X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE, &model_skl),
+ X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &model_spr),
X86_MATCH_VENDOR_FAM(AMD, 0x17, &model_amd_fam17h),
X86_MATCH_VENDOR_FAM(HYGON, 0x18, &model_amd_fam17h),
{},
prev parent reply other threads:[~2020-08-14 15:23 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-11 15:31 [PATCH v2 0/3] perf/x86/rapl: Add Intel SapphireRapids support Zhang Rui
2020-08-11 15:31 ` [PATCH v2 1/3] perf/x86/rapl: Fix missing psys sysfs attributes Zhang Rui
2020-08-14 15:23 ` [tip: perf/urgent] " tip-bot2 for Zhang Rui
2020-08-11 15:31 ` [PATCH v2 2/3] perf/x86/rapl: Support multiple rapl unit quirks Zhang Rui
2020-08-11 18:19 ` Joe Perches
2020-08-12 3:29 ` Zhang Rui
2020-08-12 3:51 ` Joe Perches
2020-08-14 15:23 ` [tip: perf/urgent] perf/x86/rapl: Support multiple RAPL " tip-bot2 for Zhang Rui
2020-08-11 15:31 ` [PATCH v2 3/3] perf/x86/rapl: Add support for Intel SPR platform Zhang Rui
2020-08-14 15:23 ` tip-bot2 for Zhang Rui [this message]
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