* [PATCH 1/5] clk: imx: add imx8m_clk_hw_composite_bus_critical
2020-10-21 8:31 [PATCH 0/5] clk: imx: fix bus critical clk registration peng.fan
@ 2020-10-21 8:31 ` peng.fan
2020-10-21 8:31 ` [PATCH 2/5] clk: imx8mq: fix noc and noc_io registration peng.fan
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: peng.fan @ 2020-10-21 8:31 UTC (permalink / raw)
To: sboyd, shawnguo, s.hauer, festevam, abel.vesa
Cc: kernel, linux-imx, Anson.Huang, linux-clk, linux-arm-kernel,
linux-kernel, aisheng.dong, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
Add imx8m_clk_hw_composite_bus_critical for bus critical clock usage.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/clk/imx/clk.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 3b796b3da249..1d7be0c86538 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -549,6 +549,11 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
IMX_COMPOSITE_BUS, \
CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
+#define imx8m_clk_hw_composite_bus_critical(name, parent_names, reg) \
+ imx8m_clk_hw_composite_flags(name, parent_names, ARRAY_SIZE(parent_names), reg, \
+ IMX_COMPOSITE_BUS, \
+ CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE | CLK_IS_CRITICAL)
+
#define imx8m_clk_hw_composite_core(name, parent_names, reg) \
imx8m_clk_hw_composite_flags(name, parent_names, \
ARRAY_SIZE(parent_names), reg, \
--
2.28.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/5] clk: imx8mq: fix noc and noc_io registration
2020-10-21 8:31 [PATCH 0/5] clk: imx: fix bus critical clk registration peng.fan
2020-10-21 8:31 ` [PATCH 1/5] clk: imx: add imx8m_clk_hw_composite_bus_critical peng.fan
@ 2020-10-21 8:31 ` peng.fan
2020-10-21 8:31 ` [PATCH 3/5] clk: imx8mm: fix bus critical clk registration peng.fan
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: peng.fan @ 2020-10-21 8:31 UTC (permalink / raw)
To: sboyd, shawnguo, s.hauer, festevam, abel.vesa
Cc: kernel, linux-imx, Anson.Huang, linux-clk, linux-arm-kernel,
linux-kernel, aisheng.dong, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
noc/axi/ahb are bus clk, not peripheral clk.
Since peripheral clk has a limitation that for peripheral clock slice,
IP clock slices must be stopped to change the clock source.
So we added CLK_SET_PARENT_GATE flag to avoid glitch.
However if noc is marked as critical clk peripheral, the
assigned clock parent operation will fail.
Fix to register as composite bus critical.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/clk/imx/clk-imx8mq.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index a06cc21181b4..28290e717d9c 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -431,7 +431,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
hws[IMX8MQ_CLK_A53_CORE] = imx_clk_hw_mux2("arm_a53_core", base + 0x9880, 24, 1, imx8mq_a53_core_sels, ARRAY_SIZE(imx8mq_a53_core_sels));
/* BUS */
- hws[IMX8MQ_CLK_MAIN_AXI] = imx8m_clk_hw_composite_critical("main_axi", imx8mq_main_axi_sels, base + 0x8800);
+ hws[IMX8MQ_CLK_MAIN_AXI] = imx8m_clk_hw_composite_bus_critical("main_axi", imx8mq_main_axi_sels, base + 0x8800);
hws[IMX8MQ_CLK_ENET_AXI] = imx8m_clk_hw_composite_bus("enet_axi", imx8mq_enet_axi_sels, base + 0x8880);
hws[IMX8MQ_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite_bus("nand_usdhc_bus", imx8mq_nand_usdhc_sels, base + 0x8900);
hws[IMX8MQ_CLK_VPU_BUS] = imx8m_clk_hw_composite_bus("vpu_bus", imx8mq_vpu_bus_sels, base + 0x8980);
@@ -441,12 +441,12 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
hws[IMX8MQ_CLK_USB_BUS] = imx8m_clk_hw_composite_bus("usb_bus", imx8mq_usb_bus_sels, base + 0x8b80);
hws[IMX8MQ_CLK_GPU_AXI] = imx8m_clk_hw_composite_bus("gpu_axi", imx8mq_gpu_axi_sels, base + 0x8c00);
hws[IMX8MQ_CLK_GPU_AHB] = imx8m_clk_hw_composite_bus("gpu_ahb", imx8mq_gpu_ahb_sels, base + 0x8c80);
- hws[IMX8MQ_CLK_NOC] = imx8m_clk_hw_composite_critical("noc", imx8mq_noc_sels, base + 0x8d00);
- hws[IMX8MQ_CLK_NOC_APB] = imx8m_clk_hw_composite_critical("noc_apb", imx8mq_noc_apb_sels, base + 0x8d80);
+ hws[IMX8MQ_CLK_NOC] = imx8m_clk_hw_composite_bus_critical("noc", imx8mq_noc_sels, base + 0x8d00);
+ hws[IMX8MQ_CLK_NOC_APB] = imx8m_clk_hw_composite_bus_critical("noc_apb", imx8mq_noc_apb_sels, base + 0x8d80);
/* AHB */
/* AHB clock is used by the AHB bus therefore marked as critical */
- hws[IMX8MQ_CLK_AHB] = imx8m_clk_hw_composite_critical("ahb", imx8mq_ahb_sels, base + 0x9000);
+ hws[IMX8MQ_CLK_AHB] = imx8m_clk_hw_composite_bus_critical("ahb", imx8mq_ahb_sels, base + 0x9000);
hws[IMX8MQ_CLK_AUDIO_AHB] = imx8m_clk_hw_composite_bus("audio_ahb", imx8mq_audio_ahb_sels, base + 0x9100);
/* IPG */
--
2.28.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/5] clk: imx8mm: fix bus critical clk registration
2020-10-21 8:31 [PATCH 0/5] clk: imx: fix bus critical clk registration peng.fan
2020-10-21 8:31 ` [PATCH 1/5] clk: imx: add imx8m_clk_hw_composite_bus_critical peng.fan
2020-10-21 8:31 ` [PATCH 2/5] clk: imx8mq: fix noc and noc_io registration peng.fan
@ 2020-10-21 8:31 ` peng.fan
2020-10-21 8:31 ` [PATCH 4/5] clk: imx8mn: " peng.fan
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: peng.fan @ 2020-10-21 8:31 UTC (permalink / raw)
To: sboyd, shawnguo, s.hauer, festevam, abel.vesa
Cc: kernel, linux-imx, Anson.Huang, linux-clk, linux-arm-kernel,
linux-kernel, aisheng.dong, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
noc/axi/ahb are bus clk, not peripheral clk.
Since peripheral clk has a limitation that for peripheral clock slice,
IP clock slices must be stopped to change the clock source.
So we added CLK_SET_PARENT_GATE flag to avoid glitch.
However if noc is marked as critical clk peripheral, the
assigned clock parent operation will fail.
Fix to register as composite bus critical.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/clk/imx/clk-imx8mm.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 0de0be0cf548..f358ad907299 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -443,9 +443,9 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
hws[IMX8MM_CLK_A53_CORE] = imx_clk_hw_mux2("arm_a53_core", base + 0x9880, 24, 1, imx8mm_a53_core_sels, ARRAY_SIZE(imx8mm_a53_core_sels));
/* BUS */
- hws[IMX8MM_CLK_MAIN_AXI] = imx8m_clk_hw_composite_critical("main_axi", imx8mm_main_axi_sels, base + 0x8800);
+ hws[IMX8MM_CLK_MAIN_AXI] = imx8m_clk_hw_composite_bus_critical("main_axi", imx8mm_main_axi_sels, base + 0x8800);
hws[IMX8MM_CLK_ENET_AXI] = imx8m_clk_hw_composite_bus("enet_axi", imx8mm_enet_axi_sels, base + 0x8880);
- hws[IMX8MM_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite_critical("nand_usdhc_bus", imx8mm_nand_usdhc_sels, base + 0x8900);
+ hws[IMX8MM_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite_bus_critical("nand_usdhc_bus", imx8mm_nand_usdhc_sels, base + 0x8900);
hws[IMX8MM_CLK_VPU_BUS] = imx8m_clk_hw_composite_bus("vpu_bus", imx8mm_vpu_bus_sels, base + 0x8980);
hws[IMX8MM_CLK_DISP_AXI] = imx8m_clk_hw_composite_bus("disp_axi", imx8mm_disp_axi_sels, base + 0x8a00);
hws[IMX8MM_CLK_DISP_APB] = imx8m_clk_hw_composite_bus("disp_apb", imx8mm_disp_apb_sels, base + 0x8a80);
@@ -453,11 +453,11 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
hws[IMX8MM_CLK_USB_BUS] = imx8m_clk_hw_composite_bus("usb_bus", imx8mm_usb_bus_sels, base + 0x8b80);
hws[IMX8MM_CLK_GPU_AXI] = imx8m_clk_hw_composite_bus("gpu_axi", imx8mm_gpu_axi_sels, base + 0x8c00);
hws[IMX8MM_CLK_GPU_AHB] = imx8m_clk_hw_composite_bus("gpu_ahb", imx8mm_gpu_ahb_sels, base + 0x8c80);
- hws[IMX8MM_CLK_NOC] = imx8m_clk_hw_composite_critical("noc", imx8mm_noc_sels, base + 0x8d00);
- hws[IMX8MM_CLK_NOC_APB] = imx8m_clk_hw_composite_critical("noc_apb", imx8mm_noc_apb_sels, base + 0x8d80);
+ hws[IMX8MM_CLK_NOC] = imx8m_clk_hw_composite_bus_critical("noc", imx8mm_noc_sels, base + 0x8d00);
+ hws[IMX8MM_CLK_NOC_APB] = imx8m_clk_hw_composite_bus_critical("noc_apb", imx8mm_noc_apb_sels, base + 0x8d80);
/* AHB */
- hws[IMX8MM_CLK_AHB] = imx8m_clk_hw_composite_critical("ahb", imx8mm_ahb_sels, base + 0x9000);
+ hws[IMX8MM_CLK_AHB] = imx8m_clk_hw_composite_bus_critical("ahb", imx8mm_ahb_sels, base + 0x9000);
hws[IMX8MM_CLK_AUDIO_AHB] = imx8m_clk_hw_composite_bus("audio_ahb", imx8mm_audio_ahb_sels, base + 0x9100);
/* IPG */
--
2.28.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 4/5] clk: imx8mn: fix bus critical clk registration
2020-10-21 8:31 [PATCH 0/5] clk: imx: fix bus critical clk registration peng.fan
` (2 preceding siblings ...)
2020-10-21 8:31 ` [PATCH 3/5] clk: imx8mm: fix bus critical clk registration peng.fan
@ 2020-10-21 8:31 ` peng.fan
2020-10-21 8:31 ` [PATCH 5/5] clk: imx8mp: " peng.fan
2020-10-21 10:39 ` [PATCH 0/5] clk: imx: " Abel Vesa
5 siblings, 0 replies; 7+ messages in thread
From: peng.fan @ 2020-10-21 8:31 UTC (permalink / raw)
To: sboyd, shawnguo, s.hauer, festevam, abel.vesa
Cc: kernel, linux-imx, Anson.Huang, linux-clk, linux-arm-kernel,
linux-kernel, aisheng.dong, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
noc/axi/ahb are bus clk, not peripheral clk.
Since peripheral clk has a limitation that for peripheral clock slice,
IP clock slices must be stopped to change the clock source.
So we added CLK_SET_PARENT_GATE flag to avoid glitch.
However if noc is marked as critical clk peripheral, the
assigned clock parent operation will fail.
Fix to register as composite bus critical.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/clk/imx/clk-imx8mn.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index e984de543f0b..f3c5e6cf55dd 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -431,7 +431,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
hws[IMX8MN_CLK_A53_CORE] = imx_clk_hw_mux2("arm_a53_core", base + 0x9880, 24, 1, imx8mn_a53_core_sels, ARRAY_SIZE(imx8mn_a53_core_sels));
/* BUS */
- hws[IMX8MN_CLK_MAIN_AXI] = imx8m_clk_hw_composite_critical("main_axi", imx8mn_main_axi_sels, base + 0x8800);
+ hws[IMX8MN_CLK_MAIN_AXI] = imx8m_clk_hw_composite_bus_critical("main_axi", imx8mn_main_axi_sels, base + 0x8800);
hws[IMX8MN_CLK_ENET_AXI] = imx8m_clk_hw_composite_bus("enet_axi", imx8mn_enet_axi_sels, base + 0x8880);
hws[IMX8MN_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite_bus("nand_usdhc_bus", imx8mn_nand_usdhc_sels, base + 0x8900);
hws[IMX8MN_CLK_DISP_AXI] = imx8m_clk_hw_composite_bus("disp_axi", imx8mn_disp_axi_sels, base + 0x8a00);
@@ -439,9 +439,9 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
hws[IMX8MN_CLK_USB_BUS] = imx8m_clk_hw_composite_bus("usb_bus", imx8mn_usb_bus_sels, base + 0x8b80);
hws[IMX8MN_CLK_GPU_AXI] = imx8m_clk_hw_composite_bus("gpu_axi", imx8mn_gpu_axi_sels, base + 0x8c00);
hws[IMX8MN_CLK_GPU_AHB] = imx8m_clk_hw_composite_bus("gpu_ahb", imx8mn_gpu_ahb_sels, base + 0x8c80);
- hws[IMX8MN_CLK_NOC] = imx8m_clk_hw_composite_critical("noc", imx8mn_noc_sels, base + 0x8d00);
+ hws[IMX8MN_CLK_NOC] = imx8m_clk_hw_composite_bus_critical("noc", imx8mn_noc_sels, base + 0x8d00);
- hws[IMX8MN_CLK_AHB] = imx8m_clk_hw_composite_critical("ahb", imx8mn_ahb_sels, base + 0x9000);
+ hws[IMX8MN_CLK_AHB] = imx8m_clk_hw_composite_bus_critical("ahb", imx8mn_ahb_sels, base + 0x9000);
hws[IMX8MN_CLK_AUDIO_AHB] = imx8m_clk_hw_composite_bus("audio_ahb", imx8mn_audio_ahb_sels, base + 0x9100);
hws[IMX8MN_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb", base + 0x9080, 0, 1);
hws[IMX8MN_CLK_IPG_AUDIO_ROOT] = imx_clk_hw_divider2("ipg_audio_root", "audio_ahb", base + 0x9180, 0, 1);
--
2.28.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 5/5] clk: imx8mp: fix bus critical clk registration
2020-10-21 8:31 [PATCH 0/5] clk: imx: fix bus critical clk registration peng.fan
` (3 preceding siblings ...)
2020-10-21 8:31 ` [PATCH 4/5] clk: imx8mn: " peng.fan
@ 2020-10-21 8:31 ` peng.fan
2020-10-21 10:39 ` [PATCH 0/5] clk: imx: " Abel Vesa
5 siblings, 0 replies; 7+ messages in thread
From: peng.fan @ 2020-10-21 8:31 UTC (permalink / raw)
To: sboyd, shawnguo, s.hauer, festevam, abel.vesa
Cc: kernel, linux-imx, Anson.Huang, linux-clk, linux-arm-kernel,
linux-kernel, aisheng.dong, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
noc/axi/ahb are bus clk, not peripheral clk.
Since peripheral clk has a limitation that for peripheral clock slice,
IP clock slices must be stopped to change the clock source.
So we added CLK_SET_PARENT_GATE flag to avoid glitch.
However if noc is marked as critical clk peripheral, the
assigned clock parent operation will fail.
Fix to register as composite bus critical.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/clk/imx/clk-imx8mp.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index 12ce4770f702..48e212477f52 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -557,9 +557,9 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
/* CORE SEL */
hws[IMX8MP_CLK_A53_CORE] = imx_clk_hw_mux2("arm_a53_core", ccm_base + 0x9880, 24, 1, imx8mp_a53_core_sels, ARRAY_SIZE(imx8mp_a53_core_sels));
- hws[IMX8MP_CLK_MAIN_AXI] = imx8m_clk_hw_composite_critical("main_axi", imx8mp_main_axi_sels, ccm_base + 0x8800);
+ hws[IMX8MP_CLK_MAIN_AXI] = imx8m_clk_hw_composite_bus_critical("main_axi", imx8mp_main_axi_sels, ccm_base + 0x8800);
hws[IMX8MP_CLK_ENET_AXI] = imx8m_clk_hw_composite_bus("enet_axi", imx8mp_enet_axi_sels, ccm_base + 0x8880);
- hws[IMX8MP_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite_critical("nand_usdhc_bus", imx8mp_nand_usdhc_sels, ccm_base + 0x8900);
+ hws[IMX8MP_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite_bus_critical("nand_usdhc_bus", imx8mp_nand_usdhc_sels, ccm_base + 0x8900);
hws[IMX8MP_CLK_VPU_BUS] = imx8m_clk_hw_composite_bus("vpu_bus", imx8mp_vpu_bus_sels, ccm_base + 0x8980);
hws[IMX8MP_CLK_MEDIA_AXI] = imx8m_clk_hw_composite_bus("media_axi", imx8mp_media_axi_sels, ccm_base + 0x8a00);
hws[IMX8MP_CLK_MEDIA_APB] = imx8m_clk_hw_composite_bus("media_apb", imx8mp_media_apb_sels, ccm_base + 0x8a80);
@@ -567,12 +567,12 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
hws[IMX8MP_CLK_HDMI_AXI] = imx8m_clk_hw_composite_bus("hdmi_axi", imx8mp_media_axi_sels, ccm_base + 0x8b80);
hws[IMX8MP_CLK_GPU_AXI] = imx8m_clk_hw_composite_bus("gpu_axi", imx8mp_gpu_axi_sels, ccm_base + 0x8c00);
hws[IMX8MP_CLK_GPU_AHB] = imx8m_clk_hw_composite_bus("gpu_ahb", imx8mp_gpu_ahb_sels, ccm_base + 0x8c80);
- hws[IMX8MP_CLK_NOC] = imx8m_clk_hw_composite_critical("noc", imx8mp_noc_sels, ccm_base + 0x8d00);
- hws[IMX8MP_CLK_NOC_IO] = imx8m_clk_hw_composite_critical("noc_io", imx8mp_noc_io_sels, ccm_base + 0x8d80);
+ hws[IMX8MP_CLK_NOC] = imx8m_clk_hw_composite_bus_critical("noc", imx8mp_noc_sels, ccm_base + 0x8d00);
+ hws[IMX8MP_CLK_NOC_IO] = imx8m_clk_hw_composite_bus_critical("noc_io", imx8mp_noc_io_sels, ccm_base + 0x8d80);
hws[IMX8MP_CLK_ML_AXI] = imx8m_clk_hw_composite_bus("ml_axi", imx8mp_ml_axi_sels, ccm_base + 0x8e00);
hws[IMX8MP_CLK_ML_AHB] = imx8m_clk_hw_composite_bus("ml_ahb", imx8mp_ml_ahb_sels, ccm_base + 0x8e80);
- hws[IMX8MP_CLK_AHB] = imx8m_clk_hw_composite_critical("ahb_root", imx8mp_ahb_sels, ccm_base + 0x9000);
+ hws[IMX8MP_CLK_AHB] = imx8m_clk_hw_composite_bus_critical("ahb_root", imx8mp_ahb_sels, ccm_base + 0x9000);
hws[IMX8MP_CLK_AUDIO_AHB] = imx8m_clk_hw_composite_bus("audio_ahb", imx8mp_audio_ahb_sels, ccm_base + 0x9100);
hws[IMX8MP_CLK_MIPI_DSI_ESC_RX] = imx8m_clk_hw_composite_bus("mipi_dsi_esc_rx", imx8mp_mipi_dsi_esc_rx_sels, ccm_base + 0x9200);
--
2.28.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 0/5] clk: imx: fix bus critical clk registration
2020-10-21 8:31 [PATCH 0/5] clk: imx: fix bus critical clk registration peng.fan
` (4 preceding siblings ...)
2020-10-21 8:31 ` [PATCH 5/5] clk: imx8mp: " peng.fan
@ 2020-10-21 10:39 ` Abel Vesa
5 siblings, 0 replies; 7+ messages in thread
From: Abel Vesa @ 2020-10-21 10:39 UTC (permalink / raw)
To: peng.fan
Cc: sboyd, shawnguo, s.hauer, festevam, kernel, linux-imx,
Anson.Huang, linux-clk, linux-arm-kernel, linux-kernel,
aisheng.dong
On 20-10-21 16:31:29, peng.fan@nxp.com wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> The issue is exposed by
> https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/
> linux.git/commit/?h=for-next&id=936c383673b9e3007432f17140ac62de53d87db9
>
> Since the upper patch not in Linus tree, I not add Fixed tag.
>
> The issue is bus clk should be registered using bus composite api, not
> peripheral api. Otherwise we will met failed to assigned clock parents error log.
> Because peripheral critical clk has CLK_SET_PARENT_GATE and CLK_IS_CRITICAL,
> you will not able to set clk parents.
>
> We need use bus critical clk api to register the clks, so introduce
> a new helper and use it.
>
I already had this change in the devfreq+icc tree.
Thanks for speeding up this work.
After our discussion yesterday, there is a further change needed for the bus
clocks and that is the 'right' to reparent on rate change. I'll probably send
that myself.
For this entire series:
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
> Peng Fan (5):
> clk: imx: add imx8m_clk_hw_composite_bus_critical
> clk: imx8mq: fix noc and noc_io registration
> clk: imx8mm: fix bus critical clk registration
> clk: imx8mn: fix bus critical clk registration
> clk: imx8mp: fix bus critical clk registration
>
> drivers/clk/imx/clk-imx8mm.c | 10 +++++-----
> drivers/clk/imx/clk-imx8mn.c | 6 +++---
> drivers/clk/imx/clk-imx8mp.c | 10 +++++-----
> drivers/clk/imx/clk-imx8mq.c | 8 ++++----
> drivers/clk/imx/clk.h | 5 +++++
> 5 files changed, 22 insertions(+), 17 deletions(-)
>
> --
> 2.28.0
>
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