From: "tip-bot2 for Thomas Gleixner" <tip-bot2@linutronix.de>
To: linux-tip-commits@vger.kernel.org
Cc: Thomas Gleixner <tglx@linutronix.de>,
David Woodhouse <dwmw@amazon.co.uk>, x86 <x86@kernel.org>,
LKML <linux-kernel@vger.kernel.org>
Subject: [tip: x86/apic] x86/apic: Cleanup destination mode
Date: Thu, 29 Oct 2020 12:15:45 -0000 [thread overview]
Message-ID: <160397374521.397.410261489835128681.tip-bot2@tip-bot2> (raw)
In-Reply-To: <20201024213535.443185-9-dwmw2@infradead.org>
The following commit has been merged into the x86/apic branch of tip:
Commit-ID: 8c44963b603db76e3e5f57d90d027657ba43c1fe
Gitweb: https://git.kernel.org/tip/8c44963b603db76e3e5f57d90d027657ba43c1fe
Author: Thomas Gleixner <tglx@linutronix.de>
AuthorDate: Sat, 24 Oct 2020 22:35:08 +01:00
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Wed, 28 Oct 2020 20:26:25 +01:00
x86/apic: Cleanup destination mode
apic::irq_dest_mode is actually a boolean, but defined as u32 and named in
a way which does not explain what it means.
Make it a boolean and rename it to 'dest_mode_logical'
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20201024213535.443185-9-dwmw2@infradead.org
---
arch/x86/include/asm/apic.h | 2 +-
arch/x86/kernel/apic/apic.c | 2 +-
arch/x86/kernel/apic/apic_flat_64.c | 4 ++--
arch/x86/kernel/apic/apic_noop.c | 4 +---
arch/x86/kernel/apic/apic_numachip.c | 4 ++--
arch/x86/kernel/apic/bigsmp_32.c | 3 +--
arch/x86/kernel/apic/io_apic.c | 2 +-
arch/x86/kernel/apic/msi.c | 6 +++---
arch/x86/kernel/apic/probe_32.c | 3 +--
arch/x86/kernel/apic/x2apic_cluster.c | 2 +-
arch/x86/kernel/apic/x2apic_phys.c | 2 +-
arch/x86/kernel/apic/x2apic_uv_x.c | 2 +-
arch/x86/kernel/smpboot.c | 7 ++-----
arch/x86/platform/uv/uv_irq.c | 2 +-
arch/x86/xen/apic.c | 3 +--
drivers/iommu/amd/amd_iommu_types.h | 2 +-
drivers/iommu/amd/iommu.c | 8 ++++----
drivers/iommu/intel/irq_remapping.c | 2 +-
18 files changed, 26 insertions(+), 34 deletions(-)
diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index e230ed2..c1f64c6 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -309,7 +309,7 @@ struct apic {
u32 disable_esr;
enum apic_delivery_modes delivery_mode;
- u32 irq_dest_mode;
+ bool dest_mode_logical;
u32 (*calc_dest_apicid)(unsigned int cpu);
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 29d28b3..54f0435 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1591,7 +1591,7 @@ static void setup_local_APIC(void)
apic->init_apic_ldr();
#ifdef CONFIG_X86_32
- if (apic->irq_dest_mode == 1) {
+ if (apic->dest_mode_logical) {
int logical_apicid, ldr_apicid;
/*
diff --git a/arch/x86/kernel/apic/apic_flat_64.c b/arch/x86/kernel/apic/apic_flat_64.c
index bbb1b89..8f72b43 100644
--- a/arch/x86/kernel/apic/apic_flat_64.c
+++ b/arch/x86/kernel/apic/apic_flat_64.c
@@ -114,7 +114,7 @@ static struct apic apic_flat __ro_after_init = {
.apic_id_registered = flat_apic_id_registered,
.delivery_mode = APIC_DELIVERY_MODE_FIXED,
- .irq_dest_mode = 1, /* logical */
+ .dest_mode_logical = true,
.disable_esr = 0,
@@ -205,7 +205,7 @@ static struct apic apic_physflat __ro_after_init = {
.apic_id_registered = flat_apic_id_registered,
.delivery_mode = APIC_DELIVERY_MODE_FIXED,
- .irq_dest_mode = 0, /* physical */
+ .dest_mode_logical = false,
.disable_esr = 0,
diff --git a/arch/x86/kernel/apic/apic_noop.c b/arch/x86/kernel/apic/apic_noop.c
index 38f167c..fe78319 100644
--- a/arch/x86/kernel/apic/apic_noop.c
+++ b/arch/x86/kernel/apic/apic_noop.c
@@ -96,8 +96,7 @@ struct apic apic_noop __ro_after_init = {
.apic_id_registered = noop_apic_id_registered,
.delivery_mode = APIC_DELIVERY_MODE_FIXED,
- /* logical delivery broadcast to all CPUs: */
- .irq_dest_mode = 1,
+ .dest_mode_logical = true,
.disable_esr = 0,
@@ -105,7 +104,6 @@ struct apic apic_noop __ro_after_init = {
.init_apic_ldr = noop_init_apic_ldr,
.ioapic_phys_id_map = default_ioapic_phys_id_map,
.setup_apic_routing = NULL,
-
.cpu_present_to_apicid = default_cpu_present_to_apicid,
.apicid_to_cpu_present = physid_set_mask_of_physid,
diff --git a/arch/x86/kernel/apic/apic_numachip.c b/arch/x86/kernel/apic/apic_numachip.c
index 4ebf9fe..a54d817 100644
--- a/arch/x86/kernel/apic/apic_numachip.c
+++ b/arch/x86/kernel/apic/apic_numachip.c
@@ -247,7 +247,7 @@ static const struct apic apic_numachip1 __refconst = {
.apic_id_registered = numachip_apic_id_registered,
.delivery_mode = APIC_DELIVERY_MODE_FIXED,
- .irq_dest_mode = 0, /* physical */
+ .dest_mode_logical = false,
.disable_esr = 0,
@@ -294,7 +294,7 @@ static const struct apic apic_numachip2 __refconst = {
.apic_id_registered = numachip_apic_id_registered,
.delivery_mode = APIC_DELIVERY_MODE_FIXED,
- .irq_dest_mode = 0, /* physical */
+ .dest_mode_logical = false,
.disable_esr = 0,
diff --git a/arch/x86/kernel/apic/bigsmp_32.c b/arch/x86/kernel/apic/bigsmp_32.c
index 64c375b..77555f6 100644
--- a/arch/x86/kernel/apic/bigsmp_32.c
+++ b/arch/x86/kernel/apic/bigsmp_32.c
@@ -128,8 +128,7 @@ static struct apic apic_bigsmp __ro_after_init = {
.apic_id_registered = bigsmp_apic_id_registered,
.delivery_mode = APIC_DELIVERY_MODE_FIXED,
- /* phys delivery to target CPU: */
- .irq_dest_mode = 0,
+ .dest_mode_logical = false,
.disable_esr = 1,
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index cff6cbc..c6d92d2 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -2950,7 +2950,7 @@ static void mp_setup_entry(struct irq_cfg *cfg, struct mp_chip_data *data,
{
memset(entry, 0, sizeof(*entry));
entry->delivery_mode = apic->delivery_mode;
- entry->dest_mode = apic->irq_dest_mode;
+ entry->dest_mode = apic->dest_mode_logical;
entry->dest = cfg->dest_apicid;
entry->vector = cfg->vector;
entry->trigger = data->trigger;
diff --git a/arch/x86/kernel/apic/msi.c b/arch/x86/kernel/apic/msi.c
index 516df47..46ffd41 100644
--- a/arch/x86/kernel/apic/msi.c
+++ b/arch/x86/kernel/apic/msi.c
@@ -30,9 +30,9 @@ static void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg,
msg->address_lo =
MSI_ADDR_BASE_LO |
- ((apic->irq_dest_mode == 0) ?
- MSI_ADDR_DEST_MODE_PHYSICAL :
- MSI_ADDR_DEST_MODE_LOGICAL) |
+ (apic->dest_mode_logical ?
+ MSI_ADDR_DEST_MODE_LOGICAL :
+ MSI_ADDR_DEST_MODE_PHYSICAL) |
MSI_ADDR_REDIRECTION_CPU |
MSI_ADDR_DEST_ID(cfg->dest_apicid);
diff --git a/arch/x86/kernel/apic/probe_32.c b/arch/x86/kernel/apic/probe_32.c
index 97652aa..a61f642 100644
--- a/arch/x86/kernel/apic/probe_32.c
+++ b/arch/x86/kernel/apic/probe_32.c
@@ -70,8 +70,7 @@ static struct apic apic_default __ro_after_init = {
.apic_id_registered = default_apic_id_registered,
.delivery_mode = APIC_DELIVERY_MODE_FIXED,
- /* logical delivery broadcast to all CPUs: */
- .irq_dest_mode = 1,
+ .dest_mode_logical = true,
.disable_esr = 0,
diff --git a/arch/x86/kernel/apic/x2apic_cluster.c b/arch/x86/kernel/apic/x2apic_cluster.c
index 53390fc..df6adc5 100644
--- a/arch/x86/kernel/apic/x2apic_cluster.c
+++ b/arch/x86/kernel/apic/x2apic_cluster.c
@@ -185,7 +185,7 @@ static struct apic apic_x2apic_cluster __ro_after_init = {
.apic_id_registered = x2apic_apic_id_registered,
.delivery_mode = APIC_DELIVERY_MODE_FIXED,
- .irq_dest_mode = 1, /* logical */
+ .dest_mode_logical = true,
.disable_esr = 0,
diff --git a/arch/x86/kernel/apic/x2apic_phys.c b/arch/x86/kernel/apic/x2apic_phys.c
index ee0c4d0..0e4e819 100644
--- a/arch/x86/kernel/apic/x2apic_phys.c
+++ b/arch/x86/kernel/apic/x2apic_phys.c
@@ -158,7 +158,7 @@ static struct apic apic_x2apic_phys __ro_after_init = {
.apic_id_registered = x2apic_apic_id_registered,
.delivery_mode = APIC_DELIVERY_MODE_FIXED,
- .irq_dest_mode = 0, /* physical */
+ .dest_mode_logical = false,
.disable_esr = 0,
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index d21a685..de94181 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -808,7 +808,7 @@ static struct apic apic_x2apic_uv_x __ro_after_init = {
.apic_id_registered = uv_apic_id_registered,
.delivery_mode = APIC_DELIVERY_MODE_FIXED,
- .irq_dest_mode = 0, /* Physical */
+ .dest_mode_logical = false,
.disable_esr = 0,
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index 6c14f10..d133d65 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -747,7 +747,7 @@ static void __init smp_quirk_init_udelay(void)
int
wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
{
- u32 dm = apic->irq_dest_mode ? APIC_DEST_LOGICAL : APIC_DEST_PHYSICAL;
+ u32 dm = apic->dest_mode_logical ? APIC_DEST_LOGICAL : APIC_DEST_PHYSICAL;
unsigned long send_status, accept_status = 0;
int maxlvt;
@@ -981,10 +981,7 @@ wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
if (!boot_error) {
enable_start_cpu0 = 1;
*cpu0_nmi_registered = 1;
- if (apic->irq_dest_mode)
- id = cpu0_logical_apicid;
- else
- id = apicid;
+ id = apic->dest_mode_logical ? cpu0_logical_apicid : apicid;
boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
}
diff --git a/arch/x86/platform/uv/uv_irq.c b/arch/x86/platform/uv/uv_irq.c
index e7020d1..1a536a1 100644
--- a/arch/x86/platform/uv/uv_irq.c
+++ b/arch/x86/platform/uv/uv_irq.c
@@ -36,7 +36,7 @@ static void uv_program_mmr(struct irq_cfg *cfg, struct uv_irq_2_mmr_pnode *info)
entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
entry->vector = cfg->vector;
entry->delivery_mode = apic->delivery_mode;
- entry->dest_mode = apic->irq_dest_mode;
+ entry->dest_mode = apic->dest_mode_logical;
entry->polarity = 0;
entry->trigger = 0;
entry->mask = 0;
diff --git a/arch/x86/xen/apic.c b/arch/x86/xen/apic.c
index c35c24b..0d46cc2 100644
--- a/arch/x86/xen/apic.c
+++ b/arch/x86/xen/apic.c
@@ -148,8 +148,7 @@ static struct apic xen_pv_apic = {
.apic_id_valid = xen_id_always_valid,
.apic_id_registered = xen_id_always_registered,
- /* .irq_delivery_mode - used in native_compose_msi_msg only */
- /* .irq_dest_mode - used in native_compose_msi_msg only */
+ /* .delivery_mode and .dest_mode_logical not used by XENPV */
.disable_esr = 0,
diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
index f696ac7..ba74a72 100644
--- a/drivers/iommu/amd/amd_iommu_types.h
+++ b/drivers/iommu/amd/amd_iommu_types.h
@@ -893,7 +893,7 @@ struct amd_ir_data {
};
struct amd_irte_ops {
- void (*prepare)(void *, u32, u32, u8, u32, int);
+ void (*prepare)(void *, u32, bool, u8, u32, int);
void (*activate)(void *, u16, u16);
void (*deactivate)(void *, u16, u16);
void (*set_affinity)(void *, u16, u16, u8, u32);
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index bc81b91..d7f0c89 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -3466,7 +3466,7 @@ static void free_irte(u16 devid, int index)
}
static void irte_prepare(void *entry,
- u32 delivery_mode, u32 dest_mode,
+ u32 delivery_mode, bool dest_mode,
u8 vector, u32 dest_apicid, int devid)
{
union irte *irte = (union irte *) entry;
@@ -3480,7 +3480,7 @@ static void irte_prepare(void *entry,
}
static void irte_ga_prepare(void *entry,
- u32 delivery_mode, u32 dest_mode,
+ u32 delivery_mode, bool dest_mode,
u8 vector, u32 dest_apicid, int devid)
{
struct irte_ga *irte = (struct irte_ga *) entry;
@@ -3672,7 +3672,7 @@ static void irq_remapping_prepare_irte(struct amd_ir_data *data,
data->irq_2_irte.devid = devid;
data->irq_2_irte.index = index + sub_handle;
iommu->irte_ops->prepare(data->entry, apic->delivery_mode,
- apic->irq_dest_mode, irq_cfg->vector,
+ apic->dest_mode_logical, irq_cfg->vector,
irq_cfg->dest_apicid, devid);
switch (info->type) {
@@ -3943,7 +3943,7 @@ int amd_iommu_deactivate_guest_mode(void *data)
entry->hi.val = 0;
entry->lo.fields_remap.valid = valid;
- entry->lo.fields_remap.dm = apic->irq_dest_mode;
+ entry->lo.fields_remap.dm = apic->dest_mode_logical;
entry->lo.fields_remap.int_type = apic->delivery_mode;
entry->hi.fields.vector = cfg->vector;
entry->lo.fields_remap.destination =
diff --git a/drivers/iommu/intel/irq_remapping.c b/drivers/iommu/intel/irq_remapping.c
index d44e719..5628d43 100644
--- a/drivers/iommu/intel/irq_remapping.c
+++ b/drivers/iommu/intel/irq_remapping.c
@@ -1113,7 +1113,7 @@ static void prepare_irte(struct irte *irte, int vector, unsigned int dest)
memset(irte, 0, sizeof(*irte));
irte->present = 1;
- irte->dst_mode = apic->irq_dest_mode;
+ irte->dst_mode = apic->dest_mode_logical;
/*
* Trigger mode in the IRTE will always be edge, and for IO-APIC, the
* actual level or edge trigger will be setup in the IO-APIC
next prev parent reply other threads:[~2020-10-29 12:16 UTC|newest]
Thread overview: 192+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-07 12:20 [PATCH 0/5] Fix x2apic enablement and allow up to 32768 CPUs without IR where supported David Woodhouse
2020-10-07 12:20 ` [PATCH 1/5] x86/apic: Fix x2apic enablement without interrupt remapping David Woodhouse
2020-10-07 12:20 ` [PATCH 2/5] x86/msi: Only use high bits of MSI address for DMAR unit David Woodhouse
2020-10-07 12:20 ` [PATCH 3/5] x86/ioapic: Handle Extended Destination ID field in RTE David Woodhouse
2020-10-08 9:12 ` Peter Zijlstra
2020-10-08 17:05 ` David Woodhouse
2020-10-08 11:41 ` Thomas Gleixner
2020-10-07 12:20 ` [PATCH 4/5] x86/apic: Support 15 bits of APIC ID in IOAPIC/MSI where available David Woodhouse
2020-10-08 11:54 ` Thomas Gleixner
2020-10-08 12:02 ` Thomas Gleixner
2020-10-08 13:00 ` David Woodhouse
2020-10-07 12:20 ` [PATCH 5/5] x86/kvm: Add KVM_FEATURE_MSI_EXT_DEST_ID David Woodhouse
2020-10-08 12:05 ` Thomas Gleixner
2020-10-08 12:55 ` David Woodhouse
2020-10-08 16:08 ` David Woodhouse
2020-10-08 21:14 ` Thomas Gleixner
2020-10-08 21:39 ` David Woodhouse
2020-10-08 23:27 ` Thomas Gleixner
2020-10-09 6:07 ` David Woodhouse
2020-10-10 10:06 ` David Woodhouse
2020-10-10 11:44 ` Thomas Gleixner
2020-10-10 11:58 ` David Woodhouse
2020-10-11 17:12 ` Thomas Gleixner
2020-10-11 21:15 ` David Woodhouse
2020-10-12 9:33 ` Thomas Gleixner
2020-10-12 16:06 ` David Woodhouse
2020-10-12 18:38 ` Thomas Gleixner
2020-10-12 20:20 ` David Woodhouse
2020-10-12 22:13 ` Thomas Gleixner
2020-10-13 7:52 ` David Woodhouse
2020-10-13 8:11 ` [PATCH 0/9] Remove irq_remapping_get_irq_domain() David Woodhouse
2020-10-13 8:11 ` [PATCH 1/9] genirq/irqdomain: Implement get_name() method on irqchip fwnodes David Woodhouse
2020-10-13 8:11 ` [PATCH 2/9] x86/apic: Add select() method on vector irqdomain David Woodhouse
2020-10-13 8:11 ` [PATCH 3/9] iommu/amd: Implement select() method on remapping irqdomain David Woodhouse
2020-10-13 8:11 ` [PATCH 4/9] iommu/vt-d: " David Woodhouse
2020-10-13 8:11 ` [PATCH 5/9] iommu/hyper-v: " David Woodhouse
2020-10-13 8:11 ` [PATCH 6/9] x86/hpet: Use irq_find_matching_fwspec() to find " David Woodhouse
2020-10-13 8:11 ` [PATCH 7/9] x86/ioapic: " David Woodhouse
2020-10-13 8:11 ` [PATCH 8/9] x86: Kill all traces of irq_remapping_get_irq_domain() David Woodhouse
2020-10-13 8:11 ` [PATCH 9/9] iommu/vt-d: Simplify intel_irq_remapping_select() David Woodhouse
2020-10-13 9:28 ` [PATCH 5/5] x86/kvm: Add KVM_FEATURE_MSI_EXT_DEST_ID Thomas Gleixner
2020-10-13 10:15 ` David Woodhouse
2020-10-13 10:46 ` Thomas Gleixner
2020-10-13 10:53 ` David Woodhouse
2020-10-13 11:51 ` David Woodhouse
2020-10-13 12:40 ` Thomas Gleixner
2020-10-08 11:46 ` [PATCH 1/5] x86/apic: Fix x2apic enablement without interrupt remapping Thomas Gleixner
2020-10-09 10:46 ` [PATCH v2 0/8] Fix x2apic enablement and allow up to 32768 CPUs without IR where supported David Woodhouse
2020-10-09 10:46 ` [PATCH v2 1/8] x86/apic: Fix x2apic enablement without interrupt remapping David Woodhouse
2020-10-09 10:46 ` [PATCH v2 2/8] x86/msi: Only use high bits of MSI address for DMAR unit David Woodhouse
2020-10-09 10:46 ` [PATCH v2 3/8] x86/apic: Always provide irq_compose_msi_msg() method for vector domain David Woodhouse
2020-10-09 10:46 ` [PATCH v2 4/8] x86/ioapic: Handle Extended Destination ID field in RTE David Woodhouse
2020-10-09 10:46 ` [PATCH v2 5/8] x86/apic: Support 15 bits of APIC ID in MSI where available David Woodhouse
2020-10-09 10:46 ` [PATCH v2 6/8] x86/kvm: Add KVM_FEATURE_MSI_EXT_DEST_ID David Woodhouse
2020-10-09 10:46 ` [PATCH v2 7/8] x86/hpet: Move MSI support into hpet.c David Woodhouse
2020-10-09 10:46 ` [PATCH v2 8/8] x86/ioapic: Generate RTE directly from parent irqchip's MSI message David Woodhouse
2020-10-22 21:43 ` Thomas Gleixner
2020-10-22 22:10 ` Thomas Gleixner
2020-10-23 17:04 ` David Woodhouse
2020-10-23 10:10 ` David Woodhouse
2020-10-23 21:28 ` Thomas Gleixner
2020-10-24 8:26 ` David Woodhouse
2020-10-24 8:41 ` David Woodhouse
2020-10-24 9:13 ` Paolo Bonzini
2020-10-24 10:13 ` David Woodhouse
2020-10-24 12:44 ` David Woodhouse
2020-10-24 21:35 ` [PATCH v3 00/35] Fix x2apic enablement and allow more CPUs, clean up I/OAPIC and MSI bitfields David Woodhouse
2020-10-24 21:35 ` [PATCH v3 01/35] x86/apic: Fix x2apic enablement without interrupt remapping David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-24 21:35 ` [PATCH v3 02/35] x86/msi: Only use high bits of MSI address for DMAR unit David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-24 21:35 ` [PATCH v3 03/35] x86/apic/uv: Fix inconsistent destination mode David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for Thomas Gleixner
2020-10-24 21:35 ` [PATCH v3 04/35] x86/devicetree: Fix the ioapic interrupt type table David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for Thomas Gleixner
2020-10-24 21:35 ` [PATCH v3 05/35] x86/apic: Cleanup delivery mode defines David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for Thomas Gleixner
2020-10-24 21:35 ` [PATCH v3 06/35] x86/apic: Replace pointless apic::dest_logical usage David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] x86/apic: Replace pointless apic:: Dest_logical usage tip-bot2 for Thomas Gleixner
2020-10-24 21:35 ` [PATCH v3 07/35] x86/apic: Get rid of apic::dest_logical David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] x86/apic: Get rid of apic:: Dest_logical tip-bot2 for Thomas Gleixner
2020-10-24 21:35 ` [PATCH v3 08/35] x86/apic: Cleanup destination mode David Woodhouse
2020-10-29 12:15 ` tip-bot2 for Thomas Gleixner [this message]
2020-10-24 21:35 ` [PATCH v3 09/35] x86/apic: Always provide irq_compose_msi_msg() method for vector domain David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-24 21:35 ` [PATCH v3 10/35] x86/hpet: Move MSI support into hpet.c David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-24 21:35 ` [PATCH v3 11/35] genirq/msi: Allow shadow declarations of msi_msg::$member David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] genirq/msi: Allow shadow declarations of msi_msg:: $member tip-bot2 for Thomas Gleixner
2020-10-24 21:35 ` [PATCH v3 12/35] x86/msi: Provide msi message shadow structs David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for Thomas Gleixner
2022-04-06 8:36 ` [PATCH v3 12/35] " Reto Buerki
2022-04-06 8:36 ` [PATCH] x86/msi: Fix msi message data shadow struct Reto Buerki
2022-04-06 22:11 ` Thomas Gleixner
2022-04-07 11:06 ` Reto Buerki
2022-04-07 13:24 ` [tip: x86/urgent] " tip-bot2 for Reto Buerki
2022-04-06 22:07 ` [PATCH v3 12/35] x86/msi: Provide msi message shadow structs Thomas Gleixner
2020-10-24 21:35 ` [PATCH v3 13/35] iommu/intel: Use msi_msg " David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for Thomas Gleixner
2020-10-24 21:35 ` [PATCH v3 14/35] iommu/amd: " David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for Thomas Gleixner
2020-10-24 21:35 ` [PATCH v3 15/35] PCI: vmd: " David Woodhouse
2020-10-28 20:49 ` Kees Cook
2020-10-28 21:13 ` Thomas Gleixner
2020-10-28 23:22 ` Kees Cook
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for Thomas Gleixner
2020-10-24 21:35 ` [PATCH v3 16/35] x86/kvm: " David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for Thomas Gleixner
2020-10-24 21:35 ` [PATCH v3 17/35] x86/pci/xen: " David Woodhouse
2020-10-25 9:49 ` David Laight
2020-10-25 10:26 ` David Woodhouse
2020-10-25 13:20 ` David Laight
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for Thomas Gleixner
2020-10-24 21:35 ` [PATCH v3 18/35] x86/msi: Remove msidef.h David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for Thomas Gleixner
2020-10-24 21:35 ` [PATCH v3 19/35] x86/io_apic: Cleanup trigger/polarity helpers David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for Thomas Gleixner
2020-11-09 23:15 ` Tom Lendacky
2020-11-10 3:30 ` [EXTERNAL] " David Woodhouse
2020-11-10 6:10 ` Borislav Petkov
2020-11-10 14:34 ` Thomas Gleixner
2020-11-10 14:55 ` Tom Lendacky
2020-11-10 15:54 ` Thomas Gleixner
2020-11-10 16:01 ` [EXTERNAL] " David Woodhouse
2020-11-10 16:17 ` Tom Lendacky
2020-11-10 16:33 ` [EXTERNAL] " David Woodhouse
2020-11-10 17:04 ` Tom Lendacky
2020-11-10 17:50 ` Thomas Gleixner
2020-11-10 18:56 ` Thomas Gleixner
2020-11-10 19:21 ` David Woodhouse
2020-11-10 21:01 ` Thomas Gleixner
2020-11-10 21:30 ` David Woodhouse
2020-11-10 22:00 ` Tom Lendacky
2020-11-10 22:48 ` Thomas Gleixner
2020-11-10 23:05 ` Tom Lendacky
2020-11-11 8:16 ` David Woodhouse
2020-11-11 9:46 ` Thomas Gleixner
2020-11-11 10:36 ` David Woodhouse
2020-11-11 12:32 ` David Woodhouse
2020-11-11 20:30 ` Tom Lendacky
2020-11-11 21:19 ` David Woodhouse
2020-11-13 15:14 ` David Woodhouse
2020-11-16 18:02 ` David Woodhouse
2020-11-17 2:00 ` Suravee Suthikulpanit
2020-11-18 10:29 ` Suravee Suthikulpanit
2020-11-18 10:52 ` David Woodhouse
2020-11-18 14:06 ` Thomas Gleixner
2020-11-18 16:51 ` Suravee Suthikulpanit
2020-11-18 17:08 ` David Woodhouse
2020-11-18 20:16 ` [tip: x86/apic] iommu/amd: Fix IOMMU interrupt generation in X2APIC mode tip-bot2 for David Woodhouse
2020-11-11 14:43 ` [PATCH 1/3] iommu/amd: Don't register interrupt remapping irqdomain when IR is disabled David Woodhouse
2020-11-11 14:43 ` [PATCH 2/3] iommu/amd: Fix union of bitfields in intcapxt support David Woodhouse
2020-11-11 22:06 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-11-11 14:43 ` [PATCH 3/3] iommu/amd: Fix IOMMU interrupt generation in X2APIC mode David Woodhouse
2020-11-11 22:06 ` [tip: x86/apic] iommu/amd: Don't register interrupt remapping irqdomain when IR is disabled tip-bot2 for David Woodhouse
2020-11-10 17:47 ` [tip: x86/apic] x86/ioapic: Correct the PCI/ISA trigger type selection tip-bot2 for Thomas Gleixner
2020-11-10 6:31 ` [PATCH v3 19/35] x86/io_apic: Cleanup trigger/polarity helpers Qian Cai
2020-11-10 8:59 ` David Woodhouse
2020-11-10 16:26 ` Paolo Bonzini
2020-10-24 21:35 ` [PATCH v3 20/35] x86/ioapic: Cleanup IO/APIC route entry structs David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for Thomas Gleixner
2020-10-24 21:35 ` [PATCH v3 21/35] x86/ioapic: Generate RTE directly from parent irqchip's MSI message David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-24 21:35 ` [PATCH v3 22/35] genirq/irqdomain: Implement get_name() method on irqchip fwnodes David Woodhouse
2020-10-25 9:41 ` Marc Zyngier
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-24 21:35 ` [PATCH v3 23/35] x86/apic: Add select() method on vector irqdomain David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-24 21:35 ` [PATCH v3 24/35] iommu/amd: Implement select() method on remapping irqdomain David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-24 21:35 ` [PATCH v3 25/35] iommu/vt-d: " David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-24 21:35 ` [PATCH v3 26/35] iommu/hyper-v: " David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-24 21:35 ` [PATCH v3 27/35] x86/hpet: Use irq_find_matching_fwspec() to find " David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-24 21:35 ` [PATCH v3 28/35] x86/ioapic: " David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-24 21:35 ` [PATCH v3 29/35] x86: Kill all traces of irq_remapping_get_irq_domain() David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-24 21:35 ` [PATCH v3 30/35] iommu/vt-d: Simplify intel_irq_remapping_select() David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-24 21:35 ` [PATCH v3 31/35] x86/ioapic: Handle Extended Destination ID field in RTE David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-24 21:35 ` [PATCH v3 32/35] x86/apic: Support 15 bits of APIC ID in MSI where available David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-24 21:35 ` [PATCH v3 33/35] iommu/hyper-v: Disable IRQ pseudo-remapping if 15 bit APIC IDs are available David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-24 21:35 ` [PATCH v3 34/35] x86/kvm: Reserve KVM_FEATURE_MSI_EXT_DEST_ID David Woodhouse
2020-10-24 21:35 ` [PATCH v3 35/35] x86/kvm: Enable 15-bit extension when KVM_FEATURE_MSI_EXT_DEST_ID detected David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-25 8:12 ` [PATCH v3 00/35] Fix x2apic enablement and allow more CPUs, clean up I/OAPIC and MSI bitfields David Woodhouse
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