[PATCH 0/2] Clean up and fix up cpu_cache_init()

[PATCH 0/2] Clean up and fix up cpu_cache_init()

[Tiezhu Yang]

Tiezhu Yang (2):
  MIPS: Remove cpu_has_6k_cache and cpu_has_8k_cache in cpu_cache_init()
  MIPS: Loongson64: Fix wrong scache size when execute lscpu

 arch/mips/include/asm/cpu-features.h |  2 --
 arch/mips/mm/c-r4k.c                 | 10 ++++------
 arch/mips/mm/cache.c                 | 10 ----------
 3 files changed, 4 insertions(+), 18 deletions(-)

-- 
2.1.0

[PATCH 1/2] MIPS: Remove cpu_has_6k_cache and cpu_has_8k_cache in cpu_cache_init()

[Tiezhu Yang]

Since commit 02cf2119684e ("Cleanup the mess in cpu_cache_init."),
cpu_has_6k_cache and cpu_has_8k_cache have no user, r6k_cache_init()
and r8k_cache_init() are not defined for over 15 years, just remove
them.

Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
---
 arch/mips/include/asm/cpu-features.h |  2 --
 arch/mips/mm/cache.c                 | 10 ----------
 2 files changed, 12 deletions(-)

diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index f2e216e..336e02b 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -115,8 +115,6 @@
 #ifndef cpu_has_3k_cache
 #define cpu_has_3k_cache	__isa_lt_and_opt(1, MIPS_CPU_3K_CACHE)
 #endif
-#define cpu_has_6k_cache	0
-#define cpu_has_8k_cache	0
 #ifndef cpu_has_4k_cache
 #define cpu_has_4k_cache	__isa_ge_or_opt(1, MIPS_CPU_4K_CACHE)
 #endif
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 3e81ba0..ed99cde 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -203,21 +203,11 @@ void cpu_cache_init(void)
 
 		r3k_cache_init();
 	}
-	if (cpu_has_6k_cache) {
-		extern void __weak r6k_cache_init(void);
-
-		r6k_cache_init();
-	}
 	if (cpu_has_4k_cache) {
 		extern void __weak r4k_cache_init(void);
 
 		r4k_cache_init();
 	}
-	if (cpu_has_8k_cache) {
-		extern void __weak r8k_cache_init(void);
-
-		r8k_cache_init();
-	}
 	if (cpu_has_tx39_cache) {
 		extern void __weak tx39_cache_init(void);
 
-- 
2.1.0

[PATCH 2/2] MIPS: Loongson64: Fix wrong scache size when execute lscpu

[Tiezhu Yang]

As the user manual and code comment said, Loongson-3 has 4-scache banks,
while Loongson-2K has only 2 banks, so we should multiply the number of
scache banks, this multiply operation should be done by c->scache.sets
instead of scache_size, otherwise we will get the wrong scache size when
execute lscpu. For example, the scache size should be 8192K instead of
2048K on the Loongson 3A3000 and 3A4000 platform, we can see the related
info in the following boot message:

[loongson@linux ~]$ dmesg | grep "Unified secondary cache"
[    0.000000] Unified secondary cache 8192kB 16-way, linesize 64 bytes.
[    4.061909] Unified secondary cache 8192kB 16-way, linesize 64 bytes.
[    4.125629] Unified secondary cache 8192kB 16-way, linesize 64 bytes.
[    4.188379] Unified secondary cache 8192kB 16-way, linesize 64 bytes.

E.g. without this patch:

[loongson@linux ~]$ cat /sys/devices/system/cpu/cpu*/cache/index2/size
2048K
2048K
2048K
2048K
[loongson@linux ~]$ lscpu | grep "L2 cache"
L2 cache:              2048K

With this patch:

[loongson@linux ~]$ cat /sys/devices/system/cpu/cpu*/cache/index2/size
8192K
8192K
8192K
8192K
[loongson@linux ~]$ lscpu | grep "L2 cache"
L2 cache:              8192K

Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
---
 arch/mips/mm/c-r4k.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 9cede7c..9952176 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1623,15 +1623,13 @@ static void __init loongson3_sc_init(void)
 	c->scache.sets = 64 << ((config2 >> 8) & 15);
 	c->scache.ways = 1 + (config2 & 15);
 
-	scache_size = c->scache.sets *
-				  c->scache.ways *
-				  c->scache.linesz;
-
 	/* Loongson-3 has 4-Scache banks, while Loongson-2K have only 2 banks */
 	if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R)
-		scache_size *= 2;
+		c->scache.sets *= 2;
 	else
-		scache_size *= 4;
+		c->scache.sets *= 4;
+
+	scache_size = c->scache.sets * c->scache.ways * c->scache.linesz;
 
 	c->scache.waybit = 0;
 	c->scache.waysize = scache_size / c->scache.ways;
-- 
2.1.0

Re: [PATCH 0/2] Clean up and fix up cpu_cache_init()

[Thomas Bogendoerfer]

On Thu, Nov 19, 2020 at 03:52:59PM +0800, Tiezhu Yang wrote:
> Tiezhu Yang (2):
>   MIPS: Remove cpu_has_6k_cache and cpu_has_8k_cache in cpu_cache_init()
>   MIPS: Loongson64: Fix wrong scache size when execute lscpu
> 
>  arch/mips/include/asm/cpu-features.h |  2 --
>  arch/mips/mm/c-r4k.c                 | 10 ++++------
>  arch/mips/mm/cache.c                 | 10 ----------
>  3 files changed, 4 insertions(+), 18 deletions(-)

applied to mips-next.

Thomas.

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