From: Claudiu Beznea <claudiu.beznea@microchip.com>
To: <mturquette@baylibre.com>, <sboyd@kernel.org>,
<nicolas.ferre@microchip.com>, <alexandre.belloni@bootlin.com>,
<ludovic.desroches@microchip.com>, <robh+dt@kernel.org>
Cc: <linux-clk@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
Eugen Hristev <eugen.hristev@microchip.com>,
Claudiu Beznea <claudiu.beznea@microchip.com>
Subject: [PATCH v6 02/11] dt-bindings: clock: at91: add sama7g5 pll defines
Date: Thu, 19 Nov 2020 17:43:08 +0200 [thread overview]
Message-ID: <1605800597-16720-3-git-send-email-claudiu.beznea@microchip.com> (raw)
In-Reply-To: <1605800597-16720-1-git-send-email-claudiu.beznea@microchip.com>
From: Eugen Hristev <eugen.hristev@microchip.com>
Add SAMA7G5 specific PLL defines to be referenced in a phandle as a
PMC_TYPE_CORE clock.
Suggested-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
[claudiu.beznea@microchip.com: adapt comit message, adapt sama7g5.c]
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
drivers/clk/at91/sama7g5.c | 6 +++---
include/dt-bindings/clock/at91.h | 10 ++++++++++
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
index a092a940baa4..7ef7963126b6 100644
--- a/drivers/clk/at91/sama7g5.c
+++ b/drivers/clk/at91/sama7g5.c
@@ -182,13 +182,13 @@ static const struct {
.p = "audiopll_fracck",
.l = &pll_layout_divpmc,
.t = PLL_TYPE_DIV,
- .eid = PMC_I2S0_MUX, },
+ .eid = PMC_AUDIOPMCPLL, },
{ .n = "audiopll_diviock",
.p = "audiopll_fracck",
.l = &pll_layout_divio,
.t = PLL_TYPE_DIV,
- .eid = PMC_I2S1_MUX, },
+ .eid = PMC_AUDIOIOPLL, },
},
[PLL_ID_ETH] = {
@@ -835,7 +835,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
if (IS_ERR(regmap))
return;
- sama7g5_pmc = pmc_data_allocate(PMC_I2S1_MUX + 1,
+ sama7g5_pmc = pmc_data_allocate(PMC_ETHPLL + 1,
nck(sama7g5_systemck),
nck(sama7g5_periphck),
nck(sama7g5_gck), 8);
diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h
index eba17106608b..fab313f62e8f 100644
--- a/include/dt-bindings/clock/at91.h
+++ b/include/dt-bindings/clock/at91.h
@@ -25,6 +25,16 @@
#define PMC_PLLBCK 8
#define PMC_AUDIOPLLCK 9
+/* SAMA7G5 */
+#define PMC_CPUPLL (PMC_MAIN + 1)
+#define PMC_SYSPLL (PMC_MAIN + 2)
+#define PMC_DDRPLL (PMC_MAIN + 3)
+#define PMC_IMGPLL (PMC_MAIN + 4)
+#define PMC_BAUDPLL (PMC_MAIN + 5)
+#define PMC_AUDIOPMCPLL (PMC_MAIN + 6)
+#define PMC_AUDIOIOPLL (PMC_MAIN + 7)
+#define PMC_ETHPLL (PMC_MAIN + 8)
+
#ifndef AT91_PMC_MOSCS
#define AT91_PMC_MOSCS 0 /* MOSCS Flag */
#define AT91_PMC_LOCKA 1 /* PLLA Lock */
--
2.7.4
next prev parent reply other threads:[~2020-11-19 15:44 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-19 15:43 [PATCH v6 00/11] clk: at91: clk-master: re-factor master clock Claudiu Beznea
2020-11-19 15:43 ` [PATCH v6 01/11] clk: at91: sama7g5: fix compilation error Claudiu Beznea
2020-12-19 19:53 ` Stephen Boyd
2020-11-19 15:43 ` Claudiu Beznea [this message]
2020-12-19 19:53 ` [PATCH v6 02/11] dt-bindings: clock: at91: add sama7g5 pll defines Stephen Boyd
2020-11-19 15:43 ` [PATCH v6 03/11] clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT Claudiu Beznea
2020-12-19 19:53 ` Stephen Boyd
2020-11-19 15:43 ` [PATCH v6 04/11] clk: at91: clk-master: add 5th divisor for mck master Claudiu Beznea
2020-12-19 19:53 ` Stephen Boyd
2020-11-19 15:43 ` [PATCH v6 05/11] clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics Claudiu Beznea
2020-12-19 19:53 ` Stephen Boyd
2020-12-19 23:31 ` Stephen Boyd
2020-11-19 15:43 ` [PATCH v6 06/11] clk: at91: clk-sam9x60-pll: allow runtime changes for pll Claudiu Beznea
2020-12-19 19:53 ` Stephen Boyd
2020-12-19 23:31 ` Stephen Boyd
2020-11-19 15:43 ` [PATCH v6 07/11] clk: at91: sama7g5: remove mck0 from parent list of other clocks Claudiu Beznea
2020-12-19 23:32 ` Stephen Boyd
2020-11-19 15:43 ` [PATCH v6 08/11] clk: at91: sama7g5: decrease lower limit for MCK0 rate Claudiu Beznea
2020-12-19 23:32 ` Stephen Boyd
2020-11-19 15:43 ` [PATCH v6 09/11] clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz Claudiu Beznea
2020-12-19 23:32 ` Stephen Boyd
2020-11-19 15:43 ` [PATCH v6 10/11] clk: at91: clk-master: re-factor master clock Claudiu Beznea
2020-12-19 23:32 ` Stephen Boyd
2020-11-19 15:43 ` [PATCH v6 11/11] clk: at91: sama7g5: register cpu clock Claudiu Beznea
2020-12-19 23:32 ` Stephen Boyd
2020-11-27 12:12 ` [PATCH v6 00/11] clk: at91: clk-master: re-factor master clock Claudiu.Beznea
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