* [PATCH v3 0/6] Add AHCI support for Tegra186
@ 2020-11-23 20:17 Sowjanya Komatineni
2020-11-23 20:17 ` [PATCH v3 1/6] arm: tegra: Change order of SATA resets for Tegra124 Sowjanya Komatineni
` (5 more replies)
0 siblings, 6 replies; 8+ messages in thread
From: Sowjanya Komatineni @ 2020-11-23 20:17 UTC (permalink / raw)
To: skomatineni, thierry.reding, jonathanh, robh+dt
Cc: pchandru, devicetree, linux-ide, linux-tegra, linux-kernel
This series adds support for AHCI-compliant SATA to Tegra186 SoC.
This series includes patches for
- Converting text based dt-binding document to YAML.
- Adding dt-bindings for Tegra186.
- Enabling AHCI-compliance SATA for Jetson TX2.
- Adding Tegra186 support to Tegra AHCI driver.
Delta between patch versions:
[v3]: fixed yaml example to pass dt_binding_check
[v2]: v1 feedback related to yaml dt-binding.
Removed conditional reset order in yaml and updated dts files
to maintain same order for commonly available resets across
Tegra124 thru Tegra186.
Sowjanya Komatineni (6):
arm: tegra: Change order of SATA resets for Tegra124
arm64: tegra: Change order of SATA resets for Tegra132 and Tegra210
dt-bindings: ata: tegra: Convert binding documentation to YAML
dt-binding: ata: tegra: Add dt-binding documentation for Tegra186
arm64: tegra: Enable AHCI on Jetson TX2
ata: ahci_tegra: Add AHCI support for Tegra186
.../devicetree/bindings/ata/nvidia,tegra-ahci.yaml | 176 +++++++++++++++++++++
.../bindings/ata/nvidia,tegra124-ahci.txt | 44 ------
arch/arm/boot/dts/tegra124.dtsi | 6 +-
arch/arm64/boot/dts/nvidia/tegra132.dtsi | 6 +-
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 4 +
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 28 ++++
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 6 +-
drivers/ata/ahci_tegra.c | 60 +++++--
8 files changed, 264 insertions(+), 66 deletions(-)
create mode 100644 Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml
delete mode 100644 Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
--
2.7.4
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v3 1/6] arm: tegra: Change order of SATA resets for Tegra124
2020-11-23 20:17 [PATCH v3 0/6] Add AHCI support for Tegra186 Sowjanya Komatineni
@ 2020-11-23 20:17 ` Sowjanya Komatineni
2020-11-23 20:17 ` [PATCH v3 2/6] arm64: tegra: Change order of SATA resets for Tegra132 and Tegra210 Sowjanya Komatineni
` (4 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Sowjanya Komatineni @ 2020-11-23 20:17 UTC (permalink / raw)
To: skomatineni, thierry.reding, jonathanh, robh+dt
Cc: pchandru, devicetree, linux-ide, linux-tegra, linux-kernel
Tegra AHCI dt-binding doc is converted from text based to yaml based.
dtbs_check valdiation strictly follows reset-names order specified
in yaml dt-binding.
Tegra124 thru Tegra210 has 3 resets sata, sata-oob and sata-cold.
Tegra186 has 2 resets sata and sata-cold.
This patch changes order of SATA resets to maintain proper resets
order for commonly available resets across Tegra124 thru Tegra186
for dtbs_check to pass.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
arch/arm/boot/dts/tegra124.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index d7001b2..e61e68a 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -650,9 +650,9 @@
<&tegra_car TEGRA124_CLK_PLL_E>;
clock-names = "sata", "sata-oob", "cml1", "pll_e";
resets = <&tegra_car 124>,
- <&tegra_car 123>,
- <&tegra_car 129>;
- reset-names = "sata", "sata-oob", "sata-cold";
+ <&tegra_car 129>,
+ <&tegra_car 123>;
+ reset-names = "sata", "sata-cold", "sata-oob";
status = "disabled";
};
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3 2/6] arm64: tegra: Change order of SATA resets for Tegra132 and Tegra210
2020-11-23 20:17 [PATCH v3 0/6] Add AHCI support for Tegra186 Sowjanya Komatineni
2020-11-23 20:17 ` [PATCH v3 1/6] arm: tegra: Change order of SATA resets for Tegra124 Sowjanya Komatineni
@ 2020-11-23 20:17 ` Sowjanya Komatineni
2020-11-23 20:17 ` [PATCH v3 3/6] dt-bindings: ata: tegra: Convert binding documentation to YAML Sowjanya Komatineni
` (3 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Sowjanya Komatineni @ 2020-11-23 20:17 UTC (permalink / raw)
To: skomatineni, thierry.reding, jonathanh, robh+dt
Cc: pchandru, devicetree, linux-ide, linux-tegra, linux-kernel
Tegra AHCI dt-binding doc is converted from text based to yaml based.
dtbs_check valdiation strictly follows reset-names order specified
in yaml dt-binding.
Tegra124 thru Tegra210 has 3 resets sata, sata-oob and sata-cold.
Tegra186 has 2 resets sata and sata-cold.
This patch changes order of SATA resets to maintain proper resets
order for commonly available resets across Tegra124 thru Tegra186
for dtbs_check to pass.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra132.dtsi | 6 +++---
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi
index 0ce958a..9928a87 100644
--- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi
@@ -629,9 +629,9 @@
<&tegra_car TEGRA124_CLK_PLL_E>;
clock-names = "sata", "sata-oob", "cml1", "pll_e";
resets = <&tegra_car 124>,
- <&tegra_car 123>,
- <&tegra_car 129>;
- reset-names = "sata", "sata-oob", "sata-cold";
+ <&tegra_car 129>,
+ <&tegra_car 123>;
+ reset-names = "sata", "sata-cold", "sata-oob";
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 6d2a9d2..ffe5da7 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -979,9 +979,9 @@
<&tegra_car TEGRA210_CLK_SATA_OOB>;
clock-names = "sata", "sata-oob";
resets = <&tegra_car 124>,
- <&tegra_car 123>,
- <&tegra_car 129>;
- reset-names = "sata", "sata-oob", "sata-cold";
+ <&tegra_car 129>,
+ <&tegra_car 123>;
+ reset-names = "sata", "sata-cold", "sata-oob";
status = "disabled";
};
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3 3/6] dt-bindings: ata: tegra: Convert binding documentation to YAML
2020-11-23 20:17 [PATCH v3 0/6] Add AHCI support for Tegra186 Sowjanya Komatineni
2020-11-23 20:17 ` [PATCH v3 1/6] arm: tegra: Change order of SATA resets for Tegra124 Sowjanya Komatineni
2020-11-23 20:17 ` [PATCH v3 2/6] arm64: tegra: Change order of SATA resets for Tegra132 and Tegra210 Sowjanya Komatineni
@ 2020-11-23 20:17 ` Sowjanya Komatineni
2020-12-07 22:51 ` Rob Herring
2020-11-23 20:17 ` [PATCH v3 4/6] dt-binding: ata: tegra: Add dt-binding documentation for Tegra186 Sowjanya Komatineni
` (2 subsequent siblings)
5 siblings, 1 reply; 8+ messages in thread
From: Sowjanya Komatineni @ 2020-11-23 20:17 UTC (permalink / raw)
To: skomatineni, thierry.reding, jonathanh, robh+dt
Cc: pchandru, devicetree, linux-ide, linux-tegra, linux-kernel
This patch converts text based dt-binding document to YAML based
dt-binding document.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
.../devicetree/bindings/ata/nvidia,tegra-ahci.yaml | 138 +++++++++++++++++++++
.../bindings/ata/nvidia,tegra124-ahci.txt | 44 -------
2 files changed, 138 insertions(+), 44 deletions(-)
create mode 100644 Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml
delete mode 100644 Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
diff --git a/Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml b/Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml
new file mode 100644
index 0000000..3c15aea
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml
@@ -0,0 +1,138 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ata/nvidia,tegra-ahci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Tegra AHCI SATA Controller
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jonathan Hunter <jonathanh@nvidia.com>
+
+properties:
+ compatible:
+ enum:
+ - nvidia,tegra124-ahci
+ - nvidia,tegra132-ahci
+ - nvidia,tegra210-ahci
+
+ reg:
+ minItems: 2
+ maxItems: 3
+ items:
+ - description: AHCI registers
+ - description: SATA configuration and IPFS registers
+ - description: SATA AUX registers
+
+ interrupts:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: sata
+ - const: sata-oob
+
+ clocks:
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: sata
+ - const: sata-cold
+ - const: sata-oob
+
+ resets:
+ maxItems: 3
+
+ phy-names:
+ items:
+ - const: sata-0
+
+ phys:
+ maxItems: 1
+
+ hvdd-supply:
+ description: SATA HVDD regulator supply.
+
+ vddio-supply:
+ description: SATA VDDIO regulator supply.
+
+ avdd-supply:
+ description: SATA AVDD regulator supply.
+
+ target-5v-supply:
+ description: SATA 5V power regulator supply.
+
+ target-12v-supply:
+ description: SATA 12V power regulator supply.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clock-names
+ - clocks
+ - reset-names
+ - resets
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nvidia,tegra124-ahci
+ - nvidia,tegra132-ahci
+ then:
+ properties:
+ reg:
+ maxItems: 2
+ reset-names:
+ minItems: 3
+ resets:
+ minItems: 3
+ required:
+ - phys
+ - phy-names
+ - hvdd-supply
+ - vddio-supply
+ - avdd-supply
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nvidia,tegra210-ahci
+ then:
+ properties:
+ reg:
+ minItems: 3
+ reset-names:
+ minItems: 3
+ resets:
+ minItems: 3
+
+additionalProperties: true
+
+examples:
+ - |
+ #include <dt-bindings/clock/tegra210-car.h>
+ #include <dt-bindings/reset/tegra210-car.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ sata@70020000 {
+ compatible = "nvidia,tegra210-ahci";
+ reg = <0x70027000 0x00002000>, /* AHCI */
+ <0x70020000 0x00007000>, /* SATA */
+ <0x70001100 0x00010000>; /* SATA AUX */
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA210_CLK_SATA>,
+ <&tegra_car TEGRA210_CLK_SATA_OOB>;
+ clock-names = "sata", "sata-oob";
+ resets = <&tegra_car 124>,
+ <&tegra_car 129>,
+ <&tegra_car 123>;
+ reset-names = "sata", "sata-cold", "sata-oob";
+ };
diff --git a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
deleted file mode 100644
index 12ab2f7..0000000
--- a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
+++ /dev/null
@@ -1,44 +0,0 @@
-Tegra SoC SATA AHCI controller
-
-Required properties :
-- compatible : Must be one of:
- - Tegra124 : "nvidia,tegra124-ahci"
- - Tegra132 : "nvidia,tegra132-ahci", "nvidia,tegra124-ahci"
- - Tegra210 : "nvidia,tegra210-ahci"
-- reg : Should contain 2 entries:
- - AHCI register set (SATA BAR5)
- - SATA register set
-- interrupts : Defines the interrupt used by SATA
-- clocks : Must contain an entry for each entry in clock-names.
- See ../clocks/clock-bindings.txt for details.
-- clock-names : Must include the following entries:
- - sata
- - sata-oob
-- resets : Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
-- reset-names : Must include the following entries:
- - sata
- - sata-oob
- - sata-cold
-- phys : Must contain an entry for each entry in phy-names.
- See ../phy/phy-bindings.txt for details.
-- phy-names : Must include the following entries:
- - For Tegra124 and Tegra132:
- - sata-phy : XUSB PADCTL SATA PHY
-- For Tegra124 and Tegra132:
- - hvdd-supply : Defines the SATA HVDD regulator
- - vddio-supply : Defines the SATA VDDIO regulator
- - avdd-supply : Defines the SATA AVDD regulator
- - target-5v-supply : Defines the SATA 5V power regulator
- - target-12v-supply : Defines the SATA 12V power regulator
-
-Optional properties:
-- reg :
- - AUX register set
-- clock-names :
- - cml1 :
- cml1 clock should be defined here if the PHY driver
- doesn't manage them. If it does, they should not be.
-- phy-names :
- - For T210:
- - sata-phy
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3 4/6] dt-binding: ata: tegra: Add dt-binding documentation for Tegra186
2020-11-23 20:17 [PATCH v3 0/6] Add AHCI support for Tegra186 Sowjanya Komatineni
` (2 preceding siblings ...)
2020-11-23 20:17 ` [PATCH v3 3/6] dt-bindings: ata: tegra: Convert binding documentation to YAML Sowjanya Komatineni
@ 2020-11-23 20:17 ` Sowjanya Komatineni
2020-11-23 20:17 ` [PATCH v3 5/6] arm64: tegra: Enable AHCI on Jetson TX2 Sowjanya Komatineni
2020-11-23 20:17 ` [PATCH v3 6/6] ata: ahci_tegra: Add AHCI support for Tegra186 Sowjanya Komatineni
5 siblings, 0 replies; 8+ messages in thread
From: Sowjanya Komatineni @ 2020-11-23 20:17 UTC (permalink / raw)
To: skomatineni, thierry.reding, jonathanh, robh+dt
Cc: pchandru, devicetree, linux-ide, linux-tegra, linux-kernel
This patch adds dt-bindings documentation for Tegra186 AHCI
controller.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
.../devicetree/bindings/ata/nvidia,tegra-ahci.yaml | 38 ++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml b/Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml
index 3c15aea..a75e9a8 100644
--- a/Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml
+++ b/Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml
@@ -16,6 +16,7 @@ properties:
- nvidia,tegra124-ahci
- nvidia,tegra132-ahci
- nvidia,tegra210-ahci
+ - nvidia,tegra186-ahci
reg:
minItems: 2
@@ -37,14 +38,31 @@ properties:
maxItems: 2
reset-names:
+ minItems: 2
items:
- const: sata
- const: sata-cold
- const: sata-oob
resets:
+ minItems: 2
maxItems: 3
+ iommus:
+ maxItems: 1
+
+ interconnect-names:
+ items:
+ - const: dma-mem
+ - const: write
+
+ interconnects:
+ maxItems: 2
+
+ power-domains:
+ items:
+ - description: SAX power-domain
+
phy-names:
items:
- const: sata-0
@@ -114,6 +132,26 @@ allOf:
resets:
minItems: 3
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nvidia,tegra186-ahci
+ then:
+ properties:
+ reg:
+ minItems: 3
+ reset-names:
+ maxItems: 2
+ resets:
+ maxItems: 2
+ required:
+ - iommus
+ - interconnect-names
+ - interconnects
+ - power-domains
+
additionalProperties: true
examples:
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3 5/6] arm64: tegra: Enable AHCI on Jetson TX2
2020-11-23 20:17 [PATCH v3 0/6] Add AHCI support for Tegra186 Sowjanya Komatineni
` (3 preceding siblings ...)
2020-11-23 20:17 ` [PATCH v3 4/6] dt-binding: ata: tegra: Add dt-binding documentation for Tegra186 Sowjanya Komatineni
@ 2020-11-23 20:17 ` Sowjanya Komatineni
2020-11-23 20:17 ` [PATCH v3 6/6] ata: ahci_tegra: Add AHCI support for Tegra186 Sowjanya Komatineni
5 siblings, 0 replies; 8+ messages in thread
From: Sowjanya Komatineni @ 2020-11-23 20:17 UTC (permalink / raw)
To: skomatineni, thierry.reding, jonathanh, robh+dt
Cc: pchandru, devicetree, linux-ide, linux-tegra, linux-kernel
This patch enables AHCI on Jetson TX2.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 4 ++++
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 28 ++++++++++++++++++++++
2 files changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
index c28d51c..6fd2e05 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
@@ -285,6 +285,10 @@
};
};
+ sata@3507000 {
+ status = "okay";
+ };
+
gpio-keys {
compatible = "gpio-keys";
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 98544d1..a303f45 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -1503,6 +1503,34 @@
};
};
+ sata@3507000 {
+ compatible = "nvidia,tegra186-ahci";
+ reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */
+ <0x0 0x03500000 0x0 0x00007000>, /* SATA */
+ <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+
+ power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>;
+ interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA186_SID_SATA>;
+
+ clocks = <&bpmp TEGRA186_CLK_SATA>,
+ <&bpmp TEGRA186_CLK_SATA_OOB>;
+ clock-names = "sata", "sata-oob";
+ assigned-clocks = <&bpmp TEGRA186_CLK_SATA>,
+ <&bpmp TEGRA186_CLK_SATA_OOB>;
+ assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>,
+ <&bpmp TEGRA186_CLK_PLLP>;
+ assigned-clock-rates = <102000000>,
+ <204000000>;
+ resets = <&bpmp TEGRA186_RESET_SATA>,
+ <&bpmp TEGRA186_RESET_SATACOLD>;
+ reset-names = "sata", "sata-cold";
+ status = "disabled";
+ };
+
bpmp: bpmp {
compatible = "nvidia,tegra186-bpmp";
interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3 6/6] ata: ahci_tegra: Add AHCI support for Tegra186
2020-11-23 20:17 [PATCH v3 0/6] Add AHCI support for Tegra186 Sowjanya Komatineni
` (4 preceding siblings ...)
2020-11-23 20:17 ` [PATCH v3 5/6] arm64: tegra: Enable AHCI on Jetson TX2 Sowjanya Komatineni
@ 2020-11-23 20:17 ` Sowjanya Komatineni
5 siblings, 0 replies; 8+ messages in thread
From: Sowjanya Komatineni @ 2020-11-23 20:17 UTC (permalink / raw)
To: skomatineni, thierry.reding, jonathanh, robh+dt
Cc: pchandru, devicetree, linux-ide, linux-tegra, linux-kernel
This patch adds support for AHCI-compliant Serial ATA controller
on Tegra186 SoC.
Tegra186 does not have sata-oob reset.
Tegra186 SATA_NVOOB register filed COMMA_CNT position and width are
different compared to Tegra210 and prior.
So, this patch adds a flag has_sata_oob_rst and tegra_ahci_regs to
SoC specific strcuture tegra_ahci_soc and updated their implementation
accordingly.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
drivers/ata/ahci_tegra.c | 60 +++++++++++++++++++++++++++++++++++++-----------
1 file changed, 47 insertions(+), 13 deletions(-)
diff --git a/drivers/ata/ahci_tegra.c b/drivers/ata/ahci_tegra.c
index cb55ebc1..56612af 100644
--- a/drivers/ata/ahci_tegra.c
+++ b/drivers/ata/ahci_tegra.c
@@ -59,8 +59,6 @@
#define T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN BIT(22)
#define T_SATA0_NVOOB 0x114
-#define T_SATA0_NVOOB_COMMA_CNT_MASK (0xff << 16)
-#define T_SATA0_NVOOB_COMMA_CNT (0x07 << 16)
#define T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK (0x3 << 24)
#define T_SATA0_NVOOB_SQUELCH_FILTER_MODE (0x1 << 24)
#define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK (0x3 << 26)
@@ -154,11 +152,18 @@ struct tegra_ahci_ops {
int (*init)(struct ahci_host_priv *hpriv);
};
+struct tegra_ahci_regs {
+ unsigned int nvoob_comma_cnt_mask;
+ unsigned int nvoob_comma_cnt_val;
+};
+
struct tegra_ahci_soc {
const char *const *supply_names;
u32 num_supplies;
bool supports_devslp;
+ bool has_sata_oob_rst;
const struct tegra_ahci_ops *ops;
+ const struct tegra_ahci_regs *regs;
};
struct tegra_ahci_priv {
@@ -240,11 +245,13 @@ static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
if (ret)
return ret;
- ret = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SATA,
- tegra->sata_clk,
- tegra->sata_rst);
- if (ret)
- goto disable_regulators;
+ if (!tegra->pdev->dev.pm_domain) {
+ ret = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SATA,
+ tegra->sata_clk,
+ tegra->sata_rst);
+ if (ret)
+ goto disable_regulators;
+ }
reset_control_assert(tegra->sata_oob_rst);
reset_control_assert(tegra->sata_cold_rst);
@@ -330,10 +337,10 @@ static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv)
writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0);
val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB);
- val &= ~(T_SATA0_NVOOB_COMMA_CNT_MASK |
+ val &= ~(tegra->soc->regs->nvoob_comma_cnt_mask |
T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK |
T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK);
- val |= (T_SATA0_NVOOB_COMMA_CNT |
+ val |= (tegra->soc->regs->nvoob_comma_cnt_val |
T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH |
T_SATA0_NVOOB_SQUELCH_FILTER_MODE);
writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB);
@@ -449,15 +456,35 @@ static const struct tegra_ahci_ops tegra124_ahci_ops = {
.init = tegra124_ahci_init,
};
+static const struct tegra_ahci_regs tegra124_ahci_regs = {
+ .nvoob_comma_cnt_mask = GENMASK(30, 28),
+ .nvoob_comma_cnt_val = (7 << 28),
+};
+
static const struct tegra_ahci_soc tegra124_ahci_soc = {
.supply_names = tegra124_supply_names,
.num_supplies = ARRAY_SIZE(tegra124_supply_names),
.supports_devslp = false,
+ .has_sata_oob_rst = true,
.ops = &tegra124_ahci_ops,
+ .regs = &tegra124_ahci_regs,
};
static const struct tegra_ahci_soc tegra210_ahci_soc = {
.supports_devslp = false,
+ .has_sata_oob_rst = true,
+ .regs = &tegra124_ahci_regs,
+};
+
+static const struct tegra_ahci_regs tegra186_ahci_regs = {
+ .nvoob_comma_cnt_mask = GENMASK(23, 16),
+ .nvoob_comma_cnt_val = (7 << 16),
+};
+
+static const struct tegra_ahci_soc tegra186_ahci_soc = {
+ .supports_devslp = false,
+ .has_sata_oob_rst = false,
+ .regs = &tegra186_ahci_regs,
};
static const struct of_device_id tegra_ahci_of_match[] = {
@@ -469,6 +496,10 @@ static const struct of_device_id tegra_ahci_of_match[] = {
.compatible = "nvidia,tegra210-ahci",
.data = &tegra210_ahci_soc
},
+ {
+ .compatible = "nvidia,tegra186-ahci",
+ .data = &tegra186_ahci_soc
+ },
{}
};
MODULE_DEVICE_TABLE(of, tegra_ahci_of_match);
@@ -518,10 +549,13 @@ static int tegra_ahci_probe(struct platform_device *pdev)
return PTR_ERR(tegra->sata_rst);
}
- tegra->sata_oob_rst = devm_reset_control_get(&pdev->dev, "sata-oob");
- if (IS_ERR(tegra->sata_oob_rst)) {
- dev_err(&pdev->dev, "Failed to get sata-oob reset\n");
- return PTR_ERR(tegra->sata_oob_rst);
+ if (tegra->soc->has_sata_oob_rst) {
+ tegra->sata_oob_rst = devm_reset_control_get(&pdev->dev,
+ "sata-oob");
+ if (IS_ERR(tegra->sata_oob_rst)) {
+ dev_err(&pdev->dev, "Failed to get sata-oob reset\n");
+ return PTR_ERR(tegra->sata_oob_rst);
+ }
}
tegra->sata_cold_rst = devm_reset_control_get(&pdev->dev, "sata-cold");
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v3 3/6] dt-bindings: ata: tegra: Convert binding documentation to YAML
2020-11-23 20:17 ` [PATCH v3 3/6] dt-bindings: ata: tegra: Convert binding documentation to YAML Sowjanya Komatineni
@ 2020-12-07 22:51 ` Rob Herring
0 siblings, 0 replies; 8+ messages in thread
From: Rob Herring @ 2020-12-07 22:51 UTC (permalink / raw)
To: Sowjanya Komatineni
Cc: linux-ide, robh+dt, thierry.reding, linux-kernel, pchandru,
linux-tegra, jonathanh, devicetree
On Mon, 23 Nov 2020 12:17:22 -0800, Sowjanya Komatineni wrote:
> This patch converts text based dt-binding document to YAML based
> dt-binding document.
>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> .../devicetree/bindings/ata/nvidia,tegra-ahci.yaml | 138 +++++++++++++++++++++
> .../bindings/ata/nvidia,tegra124-ahci.txt | 44 -------
> 2 files changed, 138 insertions(+), 44 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml
> delete mode 100644 Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-12-07 22:52 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-11-23 20:17 [PATCH v3 0/6] Add AHCI support for Tegra186 Sowjanya Komatineni
2020-11-23 20:17 ` [PATCH v3 1/6] arm: tegra: Change order of SATA resets for Tegra124 Sowjanya Komatineni
2020-11-23 20:17 ` [PATCH v3 2/6] arm64: tegra: Change order of SATA resets for Tegra132 and Tegra210 Sowjanya Komatineni
2020-11-23 20:17 ` [PATCH v3 3/6] dt-bindings: ata: tegra: Convert binding documentation to YAML Sowjanya Komatineni
2020-12-07 22:51 ` Rob Herring
2020-11-23 20:17 ` [PATCH v3 4/6] dt-binding: ata: tegra: Add dt-binding documentation for Tegra186 Sowjanya Komatineni
2020-11-23 20:17 ` [PATCH v3 5/6] arm64: tegra: Enable AHCI on Jetson TX2 Sowjanya Komatineni
2020-11-23 20:17 ` [PATCH v3 6/6] ata: ahci_tegra: Add AHCI support for Tegra186 Sowjanya Komatineni
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