* [PATCH v2 1/5] clk: Add clk_gate_ro_ops for read-only gate clocks
2020-11-26 12:40 [PATCH v2 0/5] clk: imx: Register the dram_apb and dram_alt as read-only Abel Vesa
@ 2020-11-26 12:40 ` Abel Vesa
2020-11-26 12:40 ` [PATCH v2 2/5] clk: Add CLK_GET_PARENT_NOCACHE flag Abel Vesa
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Abel Vesa @ 2020-11-26 12:40 UTC (permalink / raw)
To: Stephen Boyd, Sascha Hauer, Peng Fan, Fabio Estevam, Anson Huang,
Dong Aisheng, Jacky Bai
Cc: NXP Linux Team, linux-clk, Linux Kernel Mailing List,
linux-arm-kernel, Abel Vesa
The clocks that can be changed from outside of the clock common framework
scope (for example, EL3) need to have only the .is_enabled gate op.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
drivers/clk/clk-gate.c | 5 +++++
include/linux/clk-provider.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index 070dc47..41ca887 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -123,6 +123,11 @@ const struct clk_ops clk_gate_ops = {
};
EXPORT_SYMBOL_GPL(clk_gate_ops);
+const struct clk_ops clk_gate_ro_ops = {
+ .is_enabled = clk_gate_is_enabled,
+};
+EXPORT_SYMBOL_GPL(clk_gate_ro_ops);
+
struct clk_hw *__clk_hw_register_gate(struct device *dev,
struct device_node *np, const char *name,
const char *parent_name, const struct clk_hw *parent_hw,
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 86b7075..81ba1aa 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -483,6 +483,7 @@ struct clk_gate {
#define CLK_GATE_BIG_ENDIAN BIT(2)
extern const struct clk_ops clk_gate_ops;
+extern const struct clk_ops clk_gate_ro_ops;
struct clk_hw *__clk_hw_register_gate(struct device *dev,
struct device_node *np, const char *name,
const char *parent_name, const struct clk_hw *parent_hw,
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 2/5] clk: Add CLK_GET_PARENT_NOCACHE flag
2020-11-26 12:40 [PATCH v2 0/5] clk: imx: Register the dram_apb and dram_alt as read-only Abel Vesa
2020-11-26 12:40 ` [PATCH v2 1/5] clk: Add clk_gate_ro_ops for read-only gate clocks Abel Vesa
@ 2020-11-26 12:40 ` Abel Vesa
2020-11-26 12:40 ` [PATCH v2 3/5] clk: composite: Allow gate ops with only .is_enabled op Abel Vesa
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Abel Vesa @ 2020-11-26 12:40 UTC (permalink / raw)
To: Stephen Boyd, Sascha Hauer, Peng Fan, Fabio Estevam, Anson Huang,
Dong Aisheng, Jacky Bai
Cc: NXP Linux Team, linux-clk, Linux Kernel Mailing List,
linux-arm-kernel, Abel Vesa
This can be used by the clocks that have their parents changed from EL3.
This way the clk_get_parent will read the value from register instead of
using the value stored in the core framework.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Suggested-by: Peng Fan <peng.fan@nxp.com>
---
drivers/clk/clk.c | 31 +++++++++++++++++--------------
include/linux/clk-provider.h | 1 +
2 files changed, 18 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index c77feb6..2dd4bf4 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -2401,6 +2401,16 @@ int clk_set_max_rate(struct clk *clk, unsigned long rate)
}
EXPORT_SYMBOL_GPL(clk_set_max_rate);
+static struct clk_core *__clk_get_parent(struct clk_core *core)
+{
+ u8 index = 0;
+
+ if (core->num_parents > 1 && core->ops->get_parent)
+ index = core->ops->get_parent(core->hw);
+
+ return clk_core_get_parent_by_index(core, index);
+}
+
/**
* clk_get_parent - return the parent of a clk
* @clk: the clk whose parent gets returned
@@ -2415,24 +2425,17 @@ struct clk *clk_get_parent(struct clk *clk)
return NULL;
clk_prepare_lock();
- /* TODO: Create a per-user clk and change callers to call clk_put */
- parent = !clk->core->parent ? NULL : clk->core->parent->hw->clk;
+ if (clk->core && (clk->core->flags & CLK_GET_PARENT_NOCACHE))
+ parent = __clk_get_parent(clk->core)->hw->clk;
+ else
+ /* TODO: Create a per-user clk and change callers to call clk_put */
+ parent = !clk->core->parent ? NULL : clk->core->parent->hw->clk;
clk_prepare_unlock();
return parent;
}
EXPORT_SYMBOL_GPL(clk_get_parent);
-static struct clk_core *__clk_init_parent(struct clk_core *core)
-{
- u8 index = 0;
-
- if (core->num_parents > 1 && core->ops->get_parent)
- index = core->ops->get_parent(core->hw);
-
- return clk_core_get_parent_by_index(core, index);
-}
-
static void clk_core_reparent(struct clk_core *core,
struct clk_core *new_parent)
{
@@ -3352,7 +3355,7 @@ static void clk_core_reparent_orphans_nolock(void)
* parent.
*/
hlist_for_each_entry_safe(orphan, tmp2, &clk_orphan_list, child_node) {
- struct clk_core *parent = __clk_init_parent(orphan);
+ struct clk_core *parent = __clk_get_parent(orphan);
/*
* We need to use __clk_set_parent_before() and _after() to
@@ -3453,7 +3456,7 @@ static int __clk_core_init(struct clk_core *core)
goto out;
}
- parent = core->parent = __clk_init_parent(core);
+ parent = core->parent = __clk_get_parent(core);
/*
* Populate core->parent if parent has already been clk_core_init'd. If
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 81ba1aa..f871991b 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -32,6 +32,7 @@
#define CLK_OPS_PARENT_ENABLE BIT(12)
/* duty cycle call may be forwarded to the parent clock */
#define CLK_DUTY_CYCLE_PARENT BIT(13)
+#define CLK_GET_PARENT_NOCACHE BIT(14) /* read the parent from reg */
struct clk;
struct clk_hw;
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 3/5] clk: composite: Allow gate ops with only .is_enabled op
2020-11-26 12:40 [PATCH v2 0/5] clk: imx: Register the dram_apb and dram_alt as read-only Abel Vesa
2020-11-26 12:40 ` [PATCH v2 1/5] clk: Add clk_gate_ro_ops for read-only gate clocks Abel Vesa
2020-11-26 12:40 ` [PATCH v2 2/5] clk: Add CLK_GET_PARENT_NOCACHE flag Abel Vesa
@ 2020-11-26 12:40 ` Abel Vesa
2020-11-26 12:40 ` [PATCH v2 4/5] clk: imx: composite-8m: Add DRAM clock registration variant Abel Vesa
2020-11-26 12:40 ` [PATCH v2 5/5] clk: imx8m: Use dram variant registration for dram clocks Abel Vesa
4 siblings, 0 replies; 6+ messages in thread
From: Abel Vesa @ 2020-11-26 12:40 UTC (permalink / raw)
To: Stephen Boyd, Sascha Hauer, Peng Fan, Fabio Estevam, Anson Huang,
Dong Aisheng, Jacky Bai
Cc: NXP Linux Team, linux-clk, Linux Kernel Mailing List,
linux-arm-kernel, Abel Vesa
Some composite clocks might be enabled/disabled from outside the
clock framework. So allow the composite clock register successfully
with only the .is_enabled op for gate ops.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
drivers/clk/clk-composite.c | 19 ++++++++++---------
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index 2ddb54f..29f00a9 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -278,17 +278,18 @@ static struct clk_hw *__clk_hw_register_composite(struct device *dev,
}
if (gate_hw && gate_ops) {
- if (!gate_ops->is_enabled || !gate_ops->enable ||
- !gate_ops->disable) {
- hw = ERR_PTR(-EINVAL);
- goto err;
- }
-
composite->gate_hw = gate_hw;
composite->gate_ops = gate_ops;
- clk_composite_ops->is_enabled = clk_composite_is_enabled;
- clk_composite_ops->enable = clk_composite_enable;
- clk_composite_ops->disable = clk_composite_disable;
+ if (gate_ops->is_enabled) {
+ clk_composite_ops->is_enabled = clk_composite_is_enabled;
+ } else {
+ hw = ERR_PTR(-EINVAL);
+ goto err;
+ }
+ if (gate_ops->enable)
+ clk_composite_ops->enable = clk_composite_enable;
+ if (gate_ops->disable)
+ clk_composite_ops->disable = clk_composite_disable;
}
init.ops = clk_composite_ops;
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 4/5] clk: imx: composite-8m: Add DRAM clock registration variant
2020-11-26 12:40 [PATCH v2 0/5] clk: imx: Register the dram_apb and dram_alt as read-only Abel Vesa
` (2 preceding siblings ...)
2020-11-26 12:40 ` [PATCH v2 3/5] clk: composite: Allow gate ops with only .is_enabled op Abel Vesa
@ 2020-11-26 12:40 ` Abel Vesa
2020-11-26 12:40 ` [PATCH v2 5/5] clk: imx8m: Use dram variant registration for dram clocks Abel Vesa
4 siblings, 0 replies; 6+ messages in thread
From: Abel Vesa @ 2020-11-26 12:40 UTC (permalink / raw)
To: Stephen Boyd, Sascha Hauer, Peng Fan, Fabio Estevam, Anson Huang,
Dong Aisheng, Jacky Bai
Cc: NXP Linux Team, linux-clk, Linux Kernel Mailing List,
linux-arm-kernel, Abel Vesa
The switch between parents for dram_apb and dram_alt is done in EL3,
so make all the ops read-only. That means none of the ops that write
any of the registers is used for such a clock.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
drivers/clk/imx/clk-composite-8m.c | 12 +++++++++++-
drivers/clk/imx/clk.h | 7 +++++++
2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c
index 2c309e3..cf0c2b4 100644
--- a/drivers/clk/imx/clk-composite-8m.c
+++ b/drivers/clk/imx/clk-composite-8m.c
@@ -184,6 +184,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
struct clk_mux *mux = NULL;
const struct clk_ops *divider_ops;
const struct clk_ops *mux_ops;
+ const struct clk_ops *gate_ops;
mux = kzalloc(sizeof(*mux), GFP_KERNEL);
if (!mux)
@@ -206,16 +207,25 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
div->width = PCG_CORE_DIV_WIDTH;
divider_ops = &clk_divider_ops;
mux_ops = &imx8m_clk_composite_mux_ops;
+ gate_ops = &clk_gate_ops;
} else if (composite_flags & IMX_COMPOSITE_BUS) {
div->shift = PCG_PREDIV_SHIFT;
div->width = PCG_PREDIV_WIDTH;
divider_ops = &imx8m_clk_composite_divider_ops;
mux_ops = &imx8m_clk_composite_mux_ops;
+ gate_ops = &clk_gate_ops;
+ } else if (composite_flags & IMX_COMPOSITE_RO) {
+ div->shift = PCG_PREDIV_SHIFT;
+ div->width = PCG_PREDIV_WIDTH;
+ divider_ops = &clk_divider_ro_ops;
+ mux_ops = &clk_mux_ro_ops;
+ gate_ops = &clk_gate_ro_ops;
} else {
div->shift = PCG_PREDIV_SHIFT;
div->width = PCG_PREDIV_WIDTH;
divider_ops = &imx8m_clk_composite_divider_ops;
mux_ops = &clk_mux_ops;
+ gate_ops = &clk_gate_ops;
flags |= CLK_SET_PARENT_GATE;
}
@@ -233,7 +243,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
mux_hw, mux_ops, div_hw,
- divider_ops, gate_hw, &clk_gate_ops, flags);
+ divider_ops, gate_hw, gate_ops, flags);
if (IS_ERR(hw))
goto fail;
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 4f04c82..878ceb0 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -532,6 +532,7 @@ struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name,
#define IMX_COMPOSITE_CORE BIT(0)
#define IMX_COMPOSITE_BUS BIT(1)
+#define IMX_COMPOSITE_RO BIT(2)
struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
const char * const *parent_names,
@@ -557,6 +558,12 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
IMX_COMPOSITE_CORE, \
CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
+#define imx8m_clk_hw_composite_dram(name, parent_names, reg) \
+ imx8m_clk_hw_composite_flags(name, parent_names, \
+ ARRAY_SIZE(parent_names), reg, IMX_COMPOSITE_RO, \
+ CLK_GET_RATE_NOCACHE | CLK_GET_PARENT_NOCACHE \
+ | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
+
#define imx8m_clk_composite_flags(name, parent_names, num_parents, reg, \
flags) \
to_clk(imx8m_clk_hw_composite_flags(name, parent_names, \
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 5/5] clk: imx8m: Use dram variant registration for dram clocks
2020-11-26 12:40 [PATCH v2 0/5] clk: imx: Register the dram_apb and dram_alt as read-only Abel Vesa
` (3 preceding siblings ...)
2020-11-26 12:40 ` [PATCH v2 4/5] clk: imx: composite-8m: Add DRAM clock registration variant Abel Vesa
@ 2020-11-26 12:40 ` Abel Vesa
4 siblings, 0 replies; 6+ messages in thread
From: Abel Vesa @ 2020-11-26 12:40 UTC (permalink / raw)
To: Stephen Boyd, Sascha Hauer, Peng Fan, Fabio Estevam, Anson Huang,
Dong Aisheng, Jacky Bai
Cc: NXP Linux Team, linux-clk, Linux Kernel Mailing List,
linux-arm-kernel, Abel Vesa
Both dram_apb and dram_alt are controlled by EL3. Using the dram
variant registration of the composite-8m clock, the mux and the
divider will be read only. Do this for all i.MX8M platforms.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
drivers/clk/imx/clk-imx8mm.c | 4 ++--
drivers/clk/imx/clk-imx8mn.c | 4 ++--
drivers/clk/imx/clk-imx8mp.c | 4 ++--
drivers/clk/imx/clk-imx8mq.c | 4 ++--
4 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 7c90586..f94f0a4 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -468,8 +468,8 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
* DRAM clocks are manipulated from TF-A outside clock framework.
* Mark with GET_RATE_NOCACHE to always read div value from hardware
*/
- hws[IMX8MM_CLK_DRAM_ALT] = __imx8m_clk_hw_composite("dram_alt", imx8mm_dram_alt_sels, base + 0xa000, CLK_GET_RATE_NOCACHE);
- hws[IMX8MM_CLK_DRAM_APB] = __imx8m_clk_hw_composite("dram_apb", imx8mm_dram_apb_sels, base + 0xa080, CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE);
+ hws[IMX8MM_CLK_DRAM_ALT] = imx8m_clk_hw_composite_dram("dram_alt", imx8mm_dram_alt_sels, base + 0xa000);
+ hws[IMX8MM_CLK_DRAM_APB] = imx8m_clk_hw_composite_dram("dram_apb", imx8mm_dram_apb_sels, base + 0xa080);
/* IP */
hws[IMX8MM_CLK_VPU_G1] = imx8m_clk_hw_composite("vpu_g1", imx8mm_vpu_g1_sels, base + 0xa100);
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index 3c21db9..eb90879 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -451,8 +451,8 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
* DRAM clocks are manipulated from TF-A outside clock framework.
* Mark with GET_RATE_NOCACHE to always read div value from hardware
*/
- hws[IMX8MN_CLK_DRAM_ALT] = __imx8m_clk_hw_composite("dram_alt", imx8mn_dram_alt_sels, base + 0xa000, CLK_GET_RATE_NOCACHE);
- hws[IMX8MN_CLK_DRAM_APB] = __imx8m_clk_hw_composite("dram_apb", imx8mn_dram_apb_sels, base + 0xa080, CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE);
+ hws[IMX8MN_CLK_DRAM_ALT] = imx8m_clk_hw_composite_dram("dram_alt", imx8mn_dram_alt_sels, base + 0xa000);
+ hws[IMX8MN_CLK_DRAM_APB] = imx8m_clk_hw_composite_dram("dram_apb", imx8mn_dram_apb_sels, base + 0xa080);
hws[IMX8MN_CLK_DISP_PIXEL] = imx8m_clk_hw_composite("disp_pixel", imx8mn_disp_pixel_sels, base + 0xa500);
hws[IMX8MN_CLK_SAI2] = imx8m_clk_hw_composite("sai2", imx8mn_sai2_sels, base + 0xa600);
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index 2f4e1d6..70d671c 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -579,8 +579,8 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
hws[IMX8MP_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb_root", ccm_base + 0x9080, 0, 1);
hws[IMX8MP_CLK_IPG_AUDIO_ROOT] = imx_clk_hw_divider2("ipg_audio_root", "audio_ahb", ccm_base + 0x9180, 0, 1);
- hws[IMX8MP_CLK_DRAM_ALT] = imx8m_clk_hw_composite("dram_alt", imx8mp_dram_alt_sels, ccm_base + 0xa000);
- hws[IMX8MP_CLK_DRAM_APB] = imx8m_clk_hw_composite_critical("dram_apb", imx8mp_dram_apb_sels, ccm_base + 0xa080);
+ hws[IMX8MP_CLK_DRAM_ALT] = imx8m_clk_hw_composite_dram("dram_alt", imx8mp_dram_alt_sels, ccm_base + 0xa000);
+ hws[IMX8MP_CLK_DRAM_APB] = imx8m_clk_hw_composite_dram("dram_apb", imx8mp_dram_apb_sels, ccm_base + 0xa080);
hws[IMX8MP_CLK_VPU_G1] = imx8m_clk_hw_composite("vpu_g1", imx8mp_vpu_g1_sels, ccm_base + 0xa100);
hws[IMX8MP_CLK_VPU_G2] = imx8m_clk_hw_composite("vpu_g2", imx8mp_vpu_g2_sels, ccm_base + 0xa180);
hws[IMX8MP_CLK_CAN1] = imx8m_clk_hw_composite("can1", imx8mp_can1_sels, ccm_base + 0xa200);
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index 779ea69..a30642f 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -458,8 +458,8 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
* Mark with GET_RATE_NOCACHE to always read div value from hardware
*/
hws[IMX8MQ_CLK_DRAM_CORE] = imx_clk_hw_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mq_dram_core_sels, ARRAY_SIZE(imx8mq_dram_core_sels), CLK_IS_CRITICAL);
- hws[IMX8MQ_CLK_DRAM_ALT] = __imx8m_clk_hw_composite("dram_alt", imx8mq_dram_alt_sels, base + 0xa000, CLK_GET_RATE_NOCACHE);
- hws[IMX8MQ_CLK_DRAM_APB] = __imx8m_clk_hw_composite("dram_apb", imx8mq_dram_apb_sels, base + 0xa080, CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE);
+ hws[IMX8MQ_CLK_DRAM_ALT] = imx8m_clk_hw_composite_dram("dram_alt", imx8mq_dram_alt_sels, base + 0xa000);
+ hws[IMX8MQ_CLK_DRAM_APB] = imx8m_clk_hw_composite_dram("dram_apb", imx8mq_dram_apb_sels, base + 0xa080);
/* IP */
hws[IMX8MQ_CLK_VPU_G1] = imx8m_clk_hw_composite("vpu_g1", imx8mq_vpu_g1_sels, base + 0xa100);
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread