* [PATCH 0/4] arch: riscv: add board and SoC DT file support
@ 2020-12-02 8:03 Yash Shah
2020-12-02 8:03 ` [PATCH 1/4] dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC Yash Shah
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Yash Shah @ 2020-12-02 8:03 UTC (permalink / raw)
To: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, linux-gpio
Cc: broonie, gregkh, aou, lee.jones, u.kleine-koenig, thierry.reding,
andrew, peter, paul.walmsley, palmer, robh+dt, bgolaszewski,
linus.walleij, sachin.ghadi, Yash Shah
Start board support by adding initial support for the SiFive FU740 SoC
and the first development board that uses it, the SiFive HiFive
Unmatched A00.
Boot-tested on Linux 5.10-rc4 on a HiFive Unmatched A00 board using the
U-boot and OpenSBI.
This patch series is dependent on Zong's Patchset[0]. The patchset also
adds two new nodes in dtsi file. The binding documentation patch
for these nodes are already posted on the mailing list[1][2].
[0]: https://lore.kernel.org/linux-riscv/20201130082330.77268-4-zong.li@sifive.com/T/#u
[1]: https://lore.kernel.org/linux-riscv/1606714984-16593-1-git-send-email-yash.shah@sifive.com/T/#t
[2]: https://lore.kernel.org/linux-riscv/20201126030043.67390-1-zong.li@sifive.com/T/#u
Yash Shah (4):
dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC
riscv: dts: add initial support for the SiFive FU740-C000 SoC
dt-bindings: riscv: Update YAML doc to support SiFive HiFive Unmatched
board
riscv: dts: add initial board data for the SiFive HiFive Unmatched
.../devicetree/bindings/gpio/sifive,gpio.yaml | 4 +-
.../devicetree/bindings/i2c/i2c-ocores.txt | 6 +-
.../devicetree/bindings/pwm/pwm-sifive.yaml | 9 +-
Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +
.../devicetree/bindings/riscv/sifive.yaml | 17 +-
.../devicetree/bindings/serial/sifive-serial.yaml | 4 +-
.../devicetree/bindings/spi/spi-sifive.yaml | 10 +-
arch/riscv/boot/dts/sifive/Makefile | 3 +-
arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293 +++++++++++++++++++++
.../riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 253 ++++++++++++++++++
10 files changed, 588 insertions(+), 17 deletions(-)
create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi
create mode 100644 arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
--
2.7.4
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/4] dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC
2020-12-02 8:03 [PATCH 0/4] arch: riscv: add board and SoC DT file support Yash Shah
@ 2020-12-02 8:03 ` Yash Shah
2020-12-02 13:04 ` Mark Brown
2020-12-02 14:58 ` Andrew Lunn
2020-12-02 8:03 ` [PATCH 2/4] riscv: dts: add initial support for the SiFive FU740-C000 SoC Yash Shah
` (2 subsequent siblings)
3 siblings, 2 replies; 9+ messages in thread
From: Yash Shah @ 2020-12-02 8:03 UTC (permalink / raw)
To: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, linux-gpio
Cc: broonie, gregkh, aou, lee.jones, u.kleine-koenig, thierry.reding,
andrew, peter, paul.walmsley, palmer, robh+dt, bgolaszewski,
linus.walleij, sachin.ghadi, Yash Shah
Add new compatible strings to the DT binding documents to support SiFive
FU740-C000. Also, add new compatible strings in cpus.yaml to support the
E71 and U74 CPU cores ("harts") that are present on FU740-C000 SoC.
Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
Documentation/devicetree/bindings/gpio/sifive,gpio.yaml | 4 +++-
Documentation/devicetree/bindings/i2c/i2c-ocores.txt | 6 ++++--
Documentation/devicetree/bindings/pwm/pwm-sifive.yaml | 9 ++++++---
Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++
Documentation/devicetree/bindings/serial/sifive-serial.yaml | 4 +++-
Documentation/devicetree/bindings/spi/spi-sifive.yaml | 10 ++++++----
6 files changed, 28 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml
index a0efd8d..ab22056 100644
--- a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml
+++ b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml
@@ -13,7 +13,9 @@ maintainers:
properties:
compatible:
items:
- - const: sifive,fu540-c000-gpio
+ - enum:
+ - sifive,fu540-c000-gpio
+ - sifive,fu740-c000-gpio
- const: sifive,gpio0
reg:
diff --git a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
index 6b25a80..1966b2c 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
@@ -3,9 +3,11 @@ Device tree configuration for i2c-ocores
Required properties:
- compatible : "opencores,i2c-ocores"
"aeroflexgaisler,i2cmst"
- "sifive,fu540-c000-i2c", "sifive,i2c0"
+ "sifive,<chip>-i2c", "sifive,i2c0"
For Opencore based I2C IP block reimplemented in
- FU540-C000 SoC. Please refer to sifive-blocks-ip-versioning.txt
+ SiFive SoC. Supported compatible strings are:
+ "sifive,fu540-c000-i2c" and "sifive,fu740-c000-i2c"
+ Please refer to sifive-blocks-ip-versioning.txt
for additional details.
- reg : bus address start and address range size of device
- clocks : handle to the controller clock; see the note below.
diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
index 5ac2527..84e6691 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
+++ b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
@@ -25,12 +25,15 @@ description:
properties:
compatible:
items:
- - const: sifive,fu540-c000-pwm
+ - enum:
+ - sifive,fu540-c000-pwm
+ - sifive,fu740-c000-pwm
- const: sifive,pwm0
description:
Should be "sifive,<chip>-pwm" and "sifive,pwm<version>". Supported
- compatible strings are "sifive,fu540-c000-pwm" for the SiFive PWM v0
- as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the
+ compatible strings are "sifive,fu540-c000-pwm" and
+ "sifive,fu740-c000-pwm" for the SiFive PWM v0 as integrated onto the
+ SiFive FU540 and FU740 chip respectively, and "sifive,pwm0" for the
SiFive PWM v0 IP block with no chip integration tweaks.
Please refer to sifive-blocks-ip-versioning.txt for details.
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index c6925e0..eb6843f 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -28,11 +28,17 @@ properties:
- items:
- enum:
- sifive,rocket0
+ - sifive,bullet0
- sifive,e5
+ - sifive,e7
- sifive,e51
+ - sifive,e71
- sifive,u54-mc
+ - sifive,u74-mc
- sifive,u54
+ - sifive,u74
- sifive,u5
+ - sifive,u7
- const: riscv
- const: riscv # Simulator only
description:
diff --git a/Documentation/devicetree/bindings/serial/sifive-serial.yaml b/Documentation/devicetree/bindings/serial/sifive-serial.yaml
index 92283f6..3ac5c7f 100644
--- a/Documentation/devicetree/bindings/serial/sifive-serial.yaml
+++ b/Documentation/devicetree/bindings/serial/sifive-serial.yaml
@@ -17,7 +17,9 @@ allOf:
properties:
compatible:
items:
- - const: sifive,fu540-c000-uart
+ - enum:
+ - sifive,fu540-c000-uart
+ - sifive,fu740-c000-uart
- const: sifive,uart0
description:
diff --git a/Documentation/devicetree/bindings/spi/spi-sifive.yaml b/Documentation/devicetree/bindings/spi/spi-sifive.yaml
index 56dcf1d..6e7e394 100644
--- a/Documentation/devicetree/bindings/spi/spi-sifive.yaml
+++ b/Documentation/devicetree/bindings/spi/spi-sifive.yaml
@@ -17,15 +17,17 @@ allOf:
properties:
compatible:
items:
- - const: sifive,fu540-c000-spi
+ - enum:
+ - sifive,fu540-c000-spi
+ - sifive,fu740-c000-spi
- const: sifive,spi0
description:
Should be "sifive,<chip>-spi" and "sifive,spi<version>".
Supported compatible strings are -
- "sifive,fu540-c000-spi" for the SiFive SPI v0 as integrated
- onto the SiFive FU540 chip, and "sifive,spi0" for the SiFive
- SPI v0 IP block with no chip integration tweaks.
+ "sifive,fu540-c000-spi" and "sifive,fu740-c000-spi" for the SiFive SPI v0
+ as integrated onto the SiFive FU540 and FU740 chip resp, and "sifive,spi0"
+ for the SiFive SPI v0 IP block with no chip integration tweaks.
Please refer to sifive-blocks-ip-versioning.txt for details
SPI RTL that corresponds to the IP block version numbers can be found here -
--
2.7.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/4] riscv: dts: add initial support for the SiFive FU740-C000 SoC
2020-12-02 8:03 [PATCH 0/4] arch: riscv: add board and SoC DT file support Yash Shah
2020-12-02 8:03 ` [PATCH 1/4] dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC Yash Shah
@ 2020-12-02 8:03 ` Yash Shah
2020-12-02 8:03 ` [PATCH 3/4] dt-bindings: riscv: Update YAML doc to support SiFive HiFive Unmatched board Yash Shah
2020-12-02 8:03 ` [PATCH 4/4] riscv: dts: add initial board data for the SiFive HiFive Unmatched Yash Shah
3 siblings, 0 replies; 9+ messages in thread
From: Yash Shah @ 2020-12-02 8:03 UTC (permalink / raw)
To: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, linux-gpio
Cc: broonie, gregkh, aou, lee.jones, u.kleine-koenig, thierry.reding,
andrew, peter, paul.walmsley, palmer, robh+dt, bgolaszewski,
linus.walleij, sachin.ghadi, Yash Shah
Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built
around the SiFIve U7 Core Complex and a TileLink interconnect.
This file is expected to grow as more device drivers are added to the
kernel.
Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293 +++++++++++++++++++++++++++++
1 file changed, 293 insertions(+)
create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi
diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
new file mode 100644
index 0000000..eeb4f8c3
--- /dev/null
+++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
@@ -0,0 +1,293 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020 SiFive, Inc */
+
+/dts-v1/;
+
+#include <dt-bindings/clock/sifive-fu740-prci.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "sifive,fu740-c000", "sifive,fu740";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ ethernet0 = ð0;
+ };
+
+ chosen {
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu0: cpu@0 {
+ compatible = "sifive,bullet0", "riscv";
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <16384>;
+ next-level-cache = <&ccache>;
+ reg = <0x0>;
+ riscv,isa = "rv64imac";
+ status = "disabled";
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu1: cpu@1 {
+ compatible = "sifive,bullet0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ reg = <0x1>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ cpu1_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu2: cpu@2 {
+ compatible = "sifive,bullet0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ reg = <0x2>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ cpu2_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu3: cpu@3 {
+ compatible = "sifive,bullet0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ reg = <0x3>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ cpu3_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu4: cpu@4 {
+ compatible = "sifive,bullet0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ reg = <0x4>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ cpu4_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ };
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+ plic0: interrupt-controller@c000000 {
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
+ reg = <0x0 0xc000000 0x0 0x4000000>;
+ riscv,ndev = <69>;
+ interrupt-controller;
+ interrupts-extended = <
+ &cpu0_intc 0xffffffff
+ &cpu1_intc 0xffffffff &cpu1_intc 9
+ &cpu2_intc 0xffffffff &cpu2_intc 9
+ &cpu3_intc 0xffffffff &cpu3_intc 9
+ &cpu4_intc 0xffffffff &cpu4_intc 9>;
+ };
+ prci: clock-controller@10000000 {
+ compatible = "sifive,fu740-c000-prci";
+ reg = <0x0 0x10000000 0x0 0x1000>;
+ clocks = <&hfclk>, <&rtcclk>;
+ #clock-cells = <1>;
+ };
+ uart0: serial@10010000 {
+ compatible = "sifive,fu740-c000-uart", "sifive,uart0";
+ reg = <0x0 0x10010000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <39>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ status = "disabled";
+ };
+ uart1: serial@10011000 {
+ compatible = "sifive,fu740-c000-uart", "sifive,uart0";
+ reg = <0x0 0x10011000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <40>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ status = "disabled";
+ };
+ i2c0: i2c@10030000 {
+ compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
+ reg = <0x0 0x10030000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <52>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ reg-shift = <2>;
+ reg-io-width = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ i2c1: i2c@10031000 {
+ compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
+ reg = <0x0 0x10031000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <53>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ reg-shift = <2>;
+ reg-io-width = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ qspi0: spi@10040000 {
+ compatible = "sifive,fu740-c000-spi", "sifive,spi0";
+ reg = <0x0 0x10040000 0x0 0x1000>,
+ <0x0 0x20000000 0x0 0x10000000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <41>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ qspi1: spi@10041000 {
+ compatible = "sifive,fu740-c000-spi", "sifive,spi0";
+ reg = <0x0 0x10041000 0x0 0x1000>,
+ <0x0 0x30000000 0x0 0x10000000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <42>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ spi0: spi@10050000 {
+ compatible = "sifive,fu740-c000-spi", "sifive,spi0";
+ reg = <0x0 0x10050000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <43>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ eth0: ethernet@10090000 {
+ compatible = "sifive,fu540-c000-gem";
+ interrupt-parent = <&plic0>;
+ interrupts = <55>;
+ reg = <0x0 0x10090000 0x0 0x2000>,
+ <0x0 0x100a0000 0x0 0x1000>;
+ local-mac-address = [00 00 00 00 00 00];
+ clock-names = "pclk", "hclk";
+ clocks = <&prci PRCI_CLK_GEMGXLPLL>,
+ <&prci PRCI_CLK_GEMGXLPLL>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ pwm0: pwm@10020000 {
+ compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
+ reg = <0x0 0x10020000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <44>, <45>, <46>, <47>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+ pwm1: pwm@10021000 {
+ compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
+ reg = <0x0 0x10021000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <48>, <49>, <50>, <51>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+ ccache: cache-controller@2010000 {
+ compatible = "sifive,fu740-c000-ccache", "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <2048>;
+ cache-size = <2097152>;
+ cache-unified;
+ interrupt-parent = <&plic0>;
+ interrupts = <19 20 21 22>;
+ reg = <0x0 0x2010000 0x0 0x1000>;
+ };
+ gpio: gpio@10060000 {
+ compatible = "sifive,fu740-c000-gpio", "sifive,gpio0";
+ interrupt-parent = <&plic0>;
+ interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
+ <30>, <31>, <32>, <33>, <34>, <35>, <36>,
+ <37>, <38>;
+ reg = <0x0 0x10060000 0x0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ status = "disabled";
+ };
+ };
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/4] dt-bindings: riscv: Update YAML doc to support SiFive HiFive Unmatched board
2020-12-02 8:03 [PATCH 0/4] arch: riscv: add board and SoC DT file support Yash Shah
2020-12-02 8:03 ` [PATCH 1/4] dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC Yash Shah
2020-12-02 8:03 ` [PATCH 2/4] riscv: dts: add initial support for the SiFive FU740-C000 SoC Yash Shah
@ 2020-12-02 8:03 ` Yash Shah
2020-12-02 8:03 ` [PATCH 4/4] riscv: dts: add initial board data for the SiFive HiFive Unmatched Yash Shah
3 siblings, 0 replies; 9+ messages in thread
From: Yash Shah @ 2020-12-02 8:03 UTC (permalink / raw)
To: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, linux-gpio
Cc: broonie, gregkh, aou, lee.jones, u.kleine-koenig, thierry.reding,
andrew, peter, paul.walmsley, palmer, robh+dt, bgolaszewski,
linus.walleij, sachin.ghadi, Yash Shah
Add new compatible strings to the YAML DT binding document to support
SiFive's HiFive Unmatched board
Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
Documentation/devicetree/bindings/riscv/sifive.yaml | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/sifive.yaml b/Documentation/devicetree/bindings/riscv/sifive.yaml
index 3a8647d..ee0a239 100644
--- a/Documentation/devicetree/bindings/riscv/sifive.yaml
+++ b/Documentation/devicetree/bindings/riscv/sifive.yaml
@@ -17,11 +17,18 @@ properties:
$nodename:
const: '/'
compatible:
- items:
- - enum:
- - sifive,hifive-unleashed-a00
- - const: sifive,fu540-c000
- - const: sifive,fu540
+ oneOf:
+ - items:
+ - enum:
+ - sifive,hifive-unleashed-a00
+ - const: sifive,fu540-c000
+ - const: sifive,fu540
+
+ - items:
+ - enum:
+ - sifive,hifive-unmatched-a00
+ - const: sifive,fu740-c000
+ - const: sifive,fu740
additionalProperties: true
--
2.7.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 4/4] riscv: dts: add initial board data for the SiFive HiFive Unmatched
2020-12-02 8:03 [PATCH 0/4] arch: riscv: add board and SoC DT file support Yash Shah
` (2 preceding siblings ...)
2020-12-02 8:03 ` [PATCH 3/4] dt-bindings: riscv: Update YAML doc to support SiFive HiFive Unmatched board Yash Shah
@ 2020-12-02 8:03 ` Yash Shah
2020-12-03 0:43 ` kernel test robot
3 siblings, 1 reply; 9+ messages in thread
From: Yash Shah @ 2020-12-02 8:03 UTC (permalink / raw)
To: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, linux-gpio
Cc: broonie, gregkh, aou, lee.jones, u.kleine-koenig, thierry.reding,
andrew, peter, paul.walmsley, palmer, robh+dt, bgolaszewski,
linus.walleij, sachin.ghadi, Yash Shah
Add initial board data for the SiFive HiFive Unmatched A00
Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
arch/riscv/boot/dts/sifive/Makefile | 3 +-
.../riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 253 +++++++++++++++++++++
2 files changed, 255 insertions(+), 1 deletion(-)
create mode 100644 arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
diff --git a/arch/riscv/boot/dts/sifive/Makefile b/arch/riscv/boot/dts/sifive/Makefile
index 6d6189e..74c47fe 100644
--- a/arch/riscv/boot/dts/sifive/Makefile
+++ b/arch/riscv/boot/dts/sifive/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_SOC_SIFIVE) += hifive-unleashed-a00.dtb
+dtb-$(CONFIG_SOC_SIFIVE) += hifive-unleashed-a00.dtb \
+ hifive-unmatched-a00.dtb
diff --git a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
new file mode 100644
index 0000000..b1c3c59
--- /dev/null
+++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
@@ -0,0 +1,253 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020 SiFive, Inc */
+
+#include "fu740-c000.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
+#define RTCCLK_FREQ 1000000
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "SiFive HiFive Unmatched A00";
+ compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000",
+ "sifive,fu740";
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ cpus {
+ timebase-frequency = <RTCCLK_FREQ>;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x2 0x00000000>;
+ };
+
+ soc {
+ };
+
+ hfclk: hfclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+ clock-output-names = "hfclk";
+ };
+
+ rtcclk: rtcclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <RTCCLK_FREQ>;
+ clock-output-names = "rtcclk";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ temperature-sensor@4c {
+ compatible = "ti,tmp451";
+ reg = <0x4c>;
+ interrupt-parent = <&gpio>;
+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ pmic@58 {
+ compatible = "dlg,da9063";
+ reg = <0x58>;
+ interrupt-parent = <&gpio>;
+ interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+
+ regulators {
+ vdd_bcore1: bcore1 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-min-microamp = <5000000>;
+ regulator-max-microamp = <5000000>;
+ regulator-always-on;
+ };
+
+ vdd_bcore2: bcore2 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-min-microamp = <5000000>;
+ regulator-max-microamp = <5000000>;
+ regulator-always-on;
+ };
+
+ vdd_bpro: bpro {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microamp = <2500000>;
+ regulator-max-microamp = <2500000>;
+ regulator-always-on;
+ };
+
+ vdd_bperi: bperi {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-min-microamp = <1500000>;
+ regulator-max-microamp = <1500000>;
+ regulator-always-on;
+ };
+
+ vdd_bmem: bmem {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-min-microamp = <3000000>;
+ regulator-max-microamp = <3000000>;
+ regulator-always-on;
+ };
+
+ vdd_bio: bio {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-min-microamp = <3000000>;
+ regulator-max-microamp = <3000000>;
+ regulator-always-on;
+ };
+
+ vdd_ldo1: ldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microamp = <100000>;
+ regulator-max-microamp = <100000>;
+ regulator-always-on;
+ };
+
+ vdd_ldo2: ldo2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microamp = <200000>;
+ regulator-max-microamp = <200000>;
+ regulator-always-on;
+ };
+
+ vdd_ldo3: ldo3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microamp = <200000>;
+ regulator-max-microamp = <200000>;
+ regulator-always-on;
+ };
+
+ vdd_ldo4: ldo4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microamp = <200000>;
+ regulator-max-microamp = <200000>;
+ regulator-always-on;
+ };
+
+ vdd_ldo5: ldo5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microamp = <100000>;
+ regulator-max-microamp = <100000>;
+ regulator-always-on;
+ };
+
+ vdd_ldo6: ldo6 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microamp = <200000>;
+ regulator-max-microamp = <200000>;
+ regulator-always-on;
+ };
+
+ vdd_ldo7: ldo7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microamp = <200000>;
+ regulator-max-microamp = <200000>;
+ regulator-always-on;
+ };
+
+ vdd_ldo8: ldo8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microamp = <200000>;
+ regulator-max-microamp = <200000>;
+ regulator-always-on;
+ };
+
+ vdd_ld09: ldo9 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-min-microamp = <200000>;
+ regulator-max-microamp = <200000>;
+ };
+
+ vdd_ldo10: ldo10 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-min-microamp = <300000>;
+ regulator-max-microamp = <300000>;
+ };
+
+ vdd_ldo11: ldo11 {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-min-microamp = <300000>;
+ regulator-max-microamp = <300000>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&qspi0 {
+ status = "okay";
+ flash@0 {
+ compatible = "issi,is25wp256", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ };
+};
+
+&spi0 {
+ status = "okay";
+ mmc@0 {
+ compatible = "mmc-spi-slot";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ voltage-ranges = <3300 3300>;
+ disable-wp;
+ };
+};
+
+ð0 {
+ status = "okay";
+ phy-mode = "gmii";
+ phy-handle = <&phy0>;
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&pwm0 {
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&gpio {
+ status = "okay";
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/4] dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC
2020-12-02 8:03 ` [PATCH 1/4] dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC Yash Shah
@ 2020-12-02 13:04 ` Mark Brown
2020-12-02 14:58 ` Andrew Lunn
1 sibling, 0 replies; 9+ messages in thread
From: Mark Brown @ 2020-12-02 13:04 UTC (permalink / raw)
To: Yash Shah
Cc: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, linux-gpio, gregkh, aou, lee.jones,
u.kleine-koenig, thierry.reding, andrew, peter, paul.walmsley,
palmer, robh+dt, bgolaszewski, linus.walleij, sachin.ghadi
[-- Attachment #1: Type: text/plain, Size: 787 bytes --]
On Wed, Dec 02, 2020 at 01:33:53PM +0530, Yash Shah wrote:
> ---
> Documentation/devicetree/bindings/gpio/sifive,gpio.yaml | 4 +++-
> Documentation/devicetree/bindings/i2c/i2c-ocores.txt | 6 ++++--
> Documentation/devicetree/bindings/pwm/pwm-sifive.yaml | 9 ++++++---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++
> Documentation/devicetree/bindings/serial/sifive-serial.yaml | 4 +++-
> Documentation/devicetree/bindings/spi/spi-sifive.yaml | 10 ++++++----
> 6 files changed, 28 insertions(+), 11 deletions(-)
The driver bindings for the various subsystems would normally be sent as
independent patches to those subsystems. Driver changes mostly get
reviewed by subsystem maintainers rather than architecture maintainers.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/4] dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC
2020-12-02 8:03 ` [PATCH 1/4] dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC Yash Shah
2020-12-02 13:04 ` Mark Brown
@ 2020-12-02 14:58 ` Andrew Lunn
2020-12-03 6:36 ` Yash Shah
1 sibling, 1 reply; 9+ messages in thread
From: Andrew Lunn @ 2020-12-02 14:58 UTC (permalink / raw)
To: Yash Shah
Cc: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, linux-gpio, broonie, gregkh, aou,
lee.jones, u.kleine-koenig, thierry.reding, peter, paul.walmsley,
palmer, robh+dt, bgolaszewski, linus.walleij, sachin.ghadi
> diff --git a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
> index 6b25a80..1966b2c 100644
> --- a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
> +++ b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
> @@ -3,9 +3,11 @@ Device tree configuration for i2c-ocores
> Required properties:
> - compatible : "opencores,i2c-ocores"
> "aeroflexgaisler,i2cmst"
> - "sifive,fu540-c000-i2c", "sifive,i2c0"
> + "sifive,<chip>-i2c", "sifive,i2c0"
Please make this a full list. At some point, this file will get turned
into yaml, at which point substitution like this will need
expanding. It is better to do that now.
Andrew
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 4/4] riscv: dts: add initial board data for the SiFive HiFive Unmatched
2020-12-02 8:03 ` [PATCH 4/4] riscv: dts: add initial board data for the SiFive HiFive Unmatched Yash Shah
@ 2020-12-03 0:43 ` kernel test robot
0 siblings, 0 replies; 9+ messages in thread
From: kernel test robot @ 2020-12-03 0:43 UTC (permalink / raw)
To: Yash Shah, linux-spi, linux-serial, linux-pwm, linux-i2c,
linux-kernel, linux-riscv, devicetree, linux-gpio
Cc: kbuild-all, clang-built-linux, broonie, gregkh
[-- Attachment #1: Type: text/plain, Size: 2354 bytes --]
Hi Yash,
I love your patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on gpio/for-next wsa/i2c/for-next v5.10-rc6 next-20201201]
[cannot apply to pwm/for-next spi/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Yash-Shah/arch-riscv-add-board-and-SoC-DT-file-support/20201202-160811
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: riscv-randconfig-r016-20201202 (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project 2671fccf0381769276ca8246ec0499adcb9b0355)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install riscv cross compiling tool for clang build
# apt-get install binutils-riscv64-linux-gnu
# https://github.com/0day-ci/linux/commit/683dfb5c8d163c4fb3245cad723f8ef4d2305221
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Yash-Shah/arch-riscv-add-board-and-SoC-DT-file-support/20201202-160811
git checkout 683dfb5c8d163c4fb3245cad723f8ef4d2305221
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=riscv
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
In file included from arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts:4:
>> arch/riscv/boot/dts/sifive/fu740-c000.dtsi:6:10: fatal error: 'dt-bindings/clock/sifive-fu740-prci.h' file not found
#include <dt-bindings/clock/sifive-fu740-prci.h>
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1 error generated.
vim +6 arch/riscv/boot/dts/sifive/fu740-c000.dtsi
d3af3c8c2033d2e Yash Shah 2020-12-02 5
d3af3c8c2033d2e Yash Shah 2020-12-02 @6 #include <dt-bindings/clock/sifive-fu740-prci.h>
d3af3c8c2033d2e Yash Shah 2020-12-02 7
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 28663 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* RE: [PATCH 1/4] dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC
2020-12-02 14:58 ` Andrew Lunn
@ 2020-12-03 6:36 ` Yash Shah
0 siblings, 0 replies; 9+ messages in thread
From: Yash Shah @ 2020-12-03 6:36 UTC (permalink / raw)
To: Andrew Lunn
Cc: linux-spi, linux-serial, linux-pwm, linux-i2c, linux-kernel,
linux-riscv, devicetree, linux-gpio, broonie, gregkh, aou,
lee.jones, u.kleine-koenig, thierry.reding, peter,
Paul Walmsley ( Sifive),
palmer, robh+dt, bgolaszewski, linus.walleij, Sachin Ghadi
> -----Original Message-----
> From: Andrew Lunn <andrew@lunn.ch>
> Sent: 02 December 2020 20:28
> To: Yash Shah <yash.shah@openfive.com>
> Cc: linux-spi@vger.kernel.org; linux-serial@vger.kernel.org; linux-
> pwm@vger.kernel.org; linux-i2c@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-riscv@lists.infradead.org;
> devicetree@vger.kernel.org; linux-gpio@vger.kernel.org;
> broonie@kernel.org; gregkh@linuxfoundation.org; aou@eecs.berkeley.edu;
> lee.jones@linaro.org; u.kleine-koenig@pengutronix.de;
> thierry.reding@gmail.com; peter@korsgaard.com; Paul Walmsley ( Sifive)
> <paul.walmsley@sifive.com>; palmer@dabbelt.com; robh+dt@kernel.org;
> bgolaszewski@baylibre.com; linus.walleij@linaro.org; Sachin Ghadi
> <sachin.ghadi@openfive.com>
> Subject: Re: [PATCH 1/4] dt-bindings: riscv: Update DT binding docs to
> support SiFive FU740 SoC
>
> [External Email] Do not click links or attachments unless you recognize the
> sender and know the content is safe
>
> > diff --git a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
> > b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
> > index 6b25a80..1966b2c 100644
> > --- a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
> > +++ b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
> > @@ -3,9 +3,11 @@ Device tree configuration for i2c-ocores Required
> > properties:
> > - compatible : "opencores,i2c-ocores"
> > "aeroflexgaisler,i2cmst"
> > - "sifive,fu540-c000-i2c", "sifive,i2c0"
> > + "sifive,<chip>-i2c", "sifive,i2c0"
>
> Please make this a full list. At some point, this file will get turned into yaml, at
> which point substitution like this will need expanding. It is better to do that
> now.
Ok sure, will do that in patch v2.
- Yash
>
> Andrew
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2020-12-03 6:37 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-12-02 8:03 [PATCH 0/4] arch: riscv: add board and SoC DT file support Yash Shah
2020-12-02 8:03 ` [PATCH 1/4] dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC Yash Shah
2020-12-02 13:04 ` Mark Brown
2020-12-02 14:58 ` Andrew Lunn
2020-12-03 6:36 ` Yash Shah
2020-12-02 8:03 ` [PATCH 2/4] riscv: dts: add initial support for the SiFive FU740-C000 SoC Yash Shah
2020-12-02 8:03 ` [PATCH 3/4] dt-bindings: riscv: Update YAML doc to support SiFive HiFive Unmatched board Yash Shah
2020-12-02 8:03 ` [PATCH 4/4] riscv: dts: add initial board data for the SiFive HiFive Unmatched Yash Shah
2020-12-03 0:43 ` kernel test robot
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