* [PATCH v6 0/3] Add PCIe support for SM8250 SoC
@ 2020-12-08 12:13 Manivannan Sadhasivam
2020-12-08 12:14 ` [PATCH v6 1/3] dt-bindings: pci: qcom: Document PCIe bindings " Manivannan Sadhasivam
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Manivannan Sadhasivam @ 2020-12-08 12:13 UTC (permalink / raw)
To: lorenzo.pieralisi
Cc: agross, bjorn.andersson, svarbanov, bhelgaas, linux-arm-msm,
linux-pci, linux-kernel, mgautam, devicetree, truong,
Manivannan Sadhasivam
Hello,
This series adds PCIe support for Qualcomm SM8250 SoC with relevant PHYs.
There are 3 PCIe instances on this SoC each with different PHYs. The PCIe
controller and PHYs are mostly comaptible with the ones found on SDM845
SoC, hence the old drivers are modified to add the support.
This series has been tested on RB5 board with QCA6391 chipset connected
onboard.
Thanks,
Mani
Changes in v6:
* Dropped phy patches and rebased on top of pci/dwc branch
* Collected reviews from Bjorn
Changes in v5:
* Added Review tags from Rob
* Cleaned up the bdf to sid patch after discussing with Tony
Changes in v4:
* Fixed an issue with tx_tbl_sec in PHY driver
Changes in v3:
* Rebased on top of phy/next
* Renamed ops_sm8250 to ops_1_9_0 to maintain uniformity
Changes in v2:
* Fixed the PHY and PCIe bindings
* Introduced secondary table in PHY driver to abstract out the common configs.
* Used a more generic way of configuring BDF to SID mapping
* Dropped ATU change in favor of a patch spotted by Rob
Manivannan Sadhasivam (3):
dt-bindings: pci: qcom: Document PCIe bindings for SM8250 SoC
PCI: qcom: Add SM8250 SoC support
PCI: qcom: Add support for configuring BDF to SID mapping for SM8250
.../devicetree/bindings/pci/qcom,pcie.txt | 6 +-
drivers/pci/controller/dwc/Kconfig | 1 +
drivers/pci/controller/dwc/pcie-qcom.c | 96 +++++++++++++++++++
3 files changed, 101 insertions(+), 2 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v6 1/3] dt-bindings: pci: qcom: Document PCIe bindings for SM8250 SoC
2020-12-08 12:13 [PATCH v6 0/3] Add PCIe support for SM8250 SoC Manivannan Sadhasivam
@ 2020-12-08 12:14 ` Manivannan Sadhasivam
2020-12-08 12:14 ` [PATCH v6 2/3] PCI: qcom: Add SM8250 SoC support Manivannan Sadhasivam
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Manivannan Sadhasivam @ 2020-12-08 12:14 UTC (permalink / raw)
To: lorenzo.pieralisi
Cc: agross, bjorn.andersson, svarbanov, bhelgaas, linux-arm-msm,
linux-pci, linux-kernel, mgautam, devicetree, truong,
Manivannan Sadhasivam, Rob Herring
From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Document the PCIe DT bindings for SM8250 SoC. The PCIe IP is similar to
the one used on SDM845, hence just add the compatible along with the
optional "atu" register region.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/pci/qcom,pcie.txt | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
index 02bc81bb8b2d..3b55310390a0 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
@@ -13,6 +13,7 @@
- "qcom,pcie-ipq8074" for ipq8074
- "qcom,pcie-qcs404" for qcs404
- "qcom,pcie-sdm845" for sdm845
+ - "qcom,pcie-sm8250" for sm8250
- reg:
Usage: required
@@ -27,6 +28,7 @@
- "dbi" DesignWare PCIe registers
- "elbi" External local bus interface registers
- "config" PCIe configuration space
+ - "atu" ATU address space (optional)
- device_type:
Usage: required
@@ -131,7 +133,7 @@
- "slave_bus" AXI Slave clock
-clock-names:
- Usage: required for sdm845
+ Usage: required for sdm845 and sm8250
Value type: <stringlist>
Definition: Should contain the following entries
- "aux" Auxiliary clock
@@ -206,7 +208,7 @@
- "ahb" AHB reset
- reset-names:
- Usage: required for sdm845
+ Usage: required for sdm845 and sm8250
Value type: <stringlist>
Definition: Should contain the following entries
- "pci" PCIe core reset
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v6 2/3] PCI: qcom: Add SM8250 SoC support
2020-12-08 12:13 [PATCH v6 0/3] Add PCIe support for SM8250 SoC Manivannan Sadhasivam
2020-12-08 12:14 ` [PATCH v6 1/3] dt-bindings: pci: qcom: Document PCIe bindings " Manivannan Sadhasivam
@ 2020-12-08 12:14 ` Manivannan Sadhasivam
2020-12-08 12:14 ` [PATCH v6 3/3] PCI: qcom: Add support for configuring BDF to SID mapping for SM8250 Manivannan Sadhasivam
2020-12-08 14:48 ` [PATCH v6 0/3] Add PCIe support for SM8250 SoC Lorenzo Pieralisi
3 siblings, 0 replies; 5+ messages in thread
From: Manivannan Sadhasivam @ 2020-12-08 12:14 UTC (permalink / raw)
To: lorenzo.pieralisi
Cc: agross, bjorn.andersson, svarbanov, bhelgaas, linux-arm-msm,
linux-pci, linux-kernel, mgautam, devicetree, truong,
Manivannan Sadhasivam, Rob Herring
From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
The PCIe IP (rev 1.9.0) on SM8250 SoC is similar to the one used on
SDM845. Hence the support is added reusing the members of ops_2_7_0.
The key difference between ops_2_7_0 and ops_1_9_0 is the config_sid
callback, which will be added in successive commit.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
drivers/pci/controller/dwc/pcie-qcom.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index e49791c4f846..750ff7378870 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1348,6 +1348,16 @@ static const struct qcom_pcie_ops ops_2_7_0 = {
.post_deinit = qcom_pcie_post_deinit_2_7_0,
};
+/* Qcom IP rev.: 1.9.0 */
+static const struct qcom_pcie_ops ops_1_9_0 = {
+ .get_resources = qcom_pcie_get_resources_2_7_0,
+ .init = qcom_pcie_init_2_7_0,
+ .deinit = qcom_pcie_deinit_2_7_0,
+ .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
+ .post_init = qcom_pcie_post_init_2_7_0,
+ .post_deinit = qcom_pcie_post_deinit_2_7_0,
+};
+
static const struct dw_pcie_ops dw_pcie_ops = {
.link_up = qcom_pcie_link_up,
.start_link = qcom_pcie_start_link,
@@ -1446,6 +1456,7 @@ static const struct of_device_id qcom_pcie_match[] = {
{ .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 },
{ .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 },
{ .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 },
+ { .compatible = "qcom,pcie-sm8250", .data = &ops_1_9_0 },
{ }
};
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v6 3/3] PCI: qcom: Add support for configuring BDF to SID mapping for SM8250
2020-12-08 12:13 [PATCH v6 0/3] Add PCIe support for SM8250 SoC Manivannan Sadhasivam
2020-12-08 12:14 ` [PATCH v6 1/3] dt-bindings: pci: qcom: Document PCIe bindings " Manivannan Sadhasivam
2020-12-08 12:14 ` [PATCH v6 2/3] PCI: qcom: Add SM8250 SoC support Manivannan Sadhasivam
@ 2020-12-08 12:14 ` Manivannan Sadhasivam
2020-12-08 14:48 ` [PATCH v6 0/3] Add PCIe support for SM8250 SoC Lorenzo Pieralisi
3 siblings, 0 replies; 5+ messages in thread
From: Manivannan Sadhasivam @ 2020-12-08 12:14 UTC (permalink / raw)
To: lorenzo.pieralisi
Cc: agross, bjorn.andersson, svarbanov, bhelgaas, linux-arm-msm,
linux-pci, linux-kernel, mgautam, devicetree, truong,
Manivannan Sadhasivam
From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
For SM8250, we need to write the BDF to SID mapping in PCIe controller
register space for proper working. This is accomplished by extracting
the BDF and SID values from "iommu-map" property in DT and writing those
in the register address calculated from the hash value of BDF. In case
of collisions, the index of the next entry will also be written.
For the sake of it, let's introduce a "config_sid" callback and do it
conditionally for SM8250.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
drivers/pci/controller/dwc/Kconfig | 1 +
drivers/pci/controller/dwc/pcie-qcom.c | 85 ++++++++++++++++++++++++++
2 files changed, 86 insertions(+)
diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
index 9ee1e248e744..dd4596bdda49 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -174,6 +174,7 @@ config PCIE_QCOM
depends on OF && (ARCH_QCOM || COMPILE_TEST)
depends on PCI_MSI_IRQ_DOMAIN
select PCIE_DW_HOST
+ select CRC8
help
Say Y here to enable PCIe controller support on Qualcomm SoCs. The
PCIe controller uses the DesignWare core plus Qualcomm-specific
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 750ff7378870..8ba3e6b29196 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -9,6 +9,7 @@
*/
#include <linux/clk.h>
+#include <linux/crc8.h>
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/interrupt.h>
@@ -57,6 +58,7 @@
#define PCIE20_PARF_SID_OFFSET 0x234
#define PCIE20_PARF_BDF_TRANSLATE_CFG 0x24C
#define PCIE20_PARF_DEVICE_TYPE 0x1000
+#define PCIE20_PARF_BDF_TO_SID_TABLE_N 0x2000
#define PCIE20_ELBI_SYS_CTRL 0x04
#define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0)
@@ -97,6 +99,9 @@
#define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
#define QCOM_PCIE_2_1_0_MAX_CLOCKS 5
+
+#define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0))
+
struct qcom_pcie_resources_2_1_0 {
struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS];
struct reset_control *pci_reset;
@@ -179,6 +184,7 @@ struct qcom_pcie_ops {
void (*deinit)(struct qcom_pcie *pcie);
void (*post_deinit)(struct qcom_pcie *pcie);
void (*ltssm_enable)(struct qcom_pcie *pcie);
+ int (*config_sid)(struct qcom_pcie *pcie);
};
struct qcom_pcie {
@@ -1258,6 +1264,74 @@ static int qcom_pcie_link_up(struct dw_pcie *pci)
return !!(val & PCI_EXP_LNKSTA_DLLLA);
}
+static int qcom_pcie_config_sid_sm8250(struct qcom_pcie *pcie)
+{
+ /* iommu map structure */
+ struct {
+ u32 bdf;
+ u32 phandle;
+ u32 smmu_sid;
+ u32 smmu_sid_len;
+ } *map;
+ void __iomem *bdf_to_sid_base = pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N;
+ struct device *dev = pcie->pci->dev;
+ u8 qcom_pcie_crc8_table[CRC8_TABLE_SIZE];
+ int i, nr_map, size = 0;
+ u32 smmu_sid_base;
+
+ of_get_property(dev->of_node, "iommu-map", &size);
+ if (!size)
+ return 0;
+
+ map = kzalloc(size, GFP_KERNEL);
+ if (!map)
+ return -ENOMEM;
+
+ of_property_read_u32_array(dev->of_node,
+ "iommu-map", (u32 *)map, size / sizeof(u32));
+
+ nr_map = size / (sizeof(*map));
+
+ crc8_populate_msb(qcom_pcie_crc8_table, QCOM_PCIE_CRC8_POLYNOMIAL);
+
+ /* Registers need to be zero out first */
+ memset_io(bdf_to_sid_base, 0, CRC8_TABLE_SIZE * sizeof(u32));
+
+ /* Look for an available entry to hold the mapping */
+ for (i = 0; i < nr_map; i++) {
+ u16 bdf_be = cpu_to_be16(map[i].bdf);
+ u32 val;
+ u8 hash;
+
+ hash = crc8(qcom_pcie_crc8_table, (u8 *)&bdf_be, sizeof(bdf_be),
+ 0);
+
+ val = readl(bdf_to_sid_base + hash * sizeof(u32));
+
+ /* If the register is already populated, look for next available entry */
+ while (val) {
+ u8 current_hash = hash++;
+ u8 next_mask = 0xff;
+
+ /* If NEXT field is NULL then update it with next hash */
+ if (!(val & next_mask)) {
+ val |= (u32)hash;
+ writel(val, bdf_to_sid_base + current_hash * sizeof(u32));
+ }
+
+ val = readl(bdf_to_sid_base + hash * sizeof(u32));
+ }
+
+ /* BDF [31:16] | SID [15:8] | NEXT [7:0] */
+ val = map[i].bdf << 16 | (map[i].smmu_sid - smmu_sid_base) << 8 | 0;
+ writel(val, bdf_to_sid_base + hash * sizeof(u32));
+ }
+
+ kfree(map);
+
+ return 0;
+}
+
static int qcom_pcie_host_init(struct pcie_port *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
@@ -1282,8 +1356,18 @@ static int qcom_pcie_host_init(struct pcie_port *pp)
qcom_ep_reset_deassert(pcie);
+ if (pcie->ops->config_sid) {
+ ret = pcie->ops->config_sid(pcie);
+ if (ret)
+ goto err;
+ }
+
return 0;
+err:
+ qcom_ep_reset_assert(pcie);
+ if (pcie->ops->post_deinit)
+ pcie->ops->post_deinit(pcie);
err_disable_phy:
phy_power_off(pcie->phy);
err_deinit:
@@ -1356,6 +1440,7 @@ static const struct qcom_pcie_ops ops_1_9_0 = {
.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
.post_init = qcom_pcie_post_init_2_7_0,
.post_deinit = qcom_pcie_post_deinit_2_7_0,
+ .config_sid = qcom_pcie_config_sid_sm8250,
};
static const struct dw_pcie_ops dw_pcie_ops = {
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v6 0/3] Add PCIe support for SM8250 SoC
2020-12-08 12:13 [PATCH v6 0/3] Add PCIe support for SM8250 SoC Manivannan Sadhasivam
` (2 preceding siblings ...)
2020-12-08 12:14 ` [PATCH v6 3/3] PCI: qcom: Add support for configuring BDF to SID mapping for SM8250 Manivannan Sadhasivam
@ 2020-12-08 14:48 ` Lorenzo Pieralisi
3 siblings, 0 replies; 5+ messages in thread
From: Lorenzo Pieralisi @ 2020-12-08 14:48 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Lorenzo Pieralisi, svarbanov, devicetree, Manivannan Sadhasivam,
linux-pci, linux-arm-msm, linux-kernel, mgautam, truong,
bjorn.andersson, bhelgaas, agross
On Tue, 8 Dec 2020 17:43:59 +0530, Manivannan Sadhasivam wrote:
> This series adds PCIe support for Qualcomm SM8250 SoC with relevant PHYs.
> There are 3 PCIe instances on this SoC each with different PHYs. The PCIe
> controller and PHYs are mostly comaptible with the ones found on SDM845
> SoC, hence the old drivers are modified to add the support.
>
> This series has been tested on RB5 board with QCA6391 chipset connected
> onboard.
>
> [...]
Applied to pci/dwc, thanks!
[1/3] dt-bindings: pci: qcom: Document PCIe bindings for SM8250 SoC
https://git.kernel.org/lpieralisi/pci/c/458168247c
[2/3] PCI: qcom: Add SM8250 SoC support
https://git.kernel.org/lpieralisi/pci/c/e1dd639e37
[3/3] PCI: qcom: Add support for configuring BDF to SID mapping for SM8250
https://git.kernel.org/lpieralisi/pci/c/1c6072c743
Thanks,
Lorenzo
^ permalink raw reply [flat|nested] 5+ messages in thread
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2020-12-08 12:13 [PATCH v6 0/3] Add PCIe support for SM8250 SoC Manivannan Sadhasivam
2020-12-08 12:14 ` [PATCH v6 1/3] dt-bindings: pci: qcom: Document PCIe bindings " Manivannan Sadhasivam
2020-12-08 12:14 ` [PATCH v6 2/3] PCI: qcom: Add SM8250 SoC support Manivannan Sadhasivam
2020-12-08 12:14 ` [PATCH v6 3/3] PCI: qcom: Add support for configuring BDF to SID mapping for SM8250 Manivannan Sadhasivam
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