* [PATCH 0/3] power: reset: at91-sama5d2_shdwc: add support for SAMA7G5 @ 2020-12-16 12:57 Claudiu Beznea 2020-12-16 12:57 ` [PATCH 1/3] power: reset: at91-sama5d2_shdwc: fix wkupdbc mask Claudiu Beznea ` (3 more replies) 0 siblings, 4 replies; 12+ messages in thread From: Claudiu Beznea @ 2020-12-16 12:57 UTC (permalink / raw) To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni, ludovic.desroches, sre Cc: devicetree, linux-arm-kernel, linux-kernel, linux-pm, Claudiu Beznea Hi, This series adds support for SAMA7G5 shutdown controller. Thank you, Claudiu Beznea Claudiu Beznea (3): power: reset: at91-sama5d2_shdwc: fix wkupdbc mask dt-bindings: atmel-sysreg: add microchip,sama7g5-shdwc power: reset: at91-sama5d2_shdwc: add support for sama7g5 .../devicetree/bindings/arm/atmel-sysregs.txt | 5 +- drivers/power/reset/at91-sama5d2_shdwc.c | 74 ++++++++++++++++------ 2 files changed, 58 insertions(+), 21 deletions(-) -- 2.7.4 ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/3] power: reset: at91-sama5d2_shdwc: fix wkupdbc mask 2020-12-16 12:57 [PATCH 0/3] power: reset: at91-sama5d2_shdwc: add support for SAMA7G5 Claudiu Beznea @ 2020-12-16 12:57 ` Claudiu Beznea 2020-12-16 13:40 ` Alexandre Belloni 2020-12-16 12:57 ` [PATCH 2/3] dt-bindings: atmel-sysreg: add microchip,sama7g5-shdwc Claudiu Beznea ` (2 subsequent siblings) 3 siblings, 1 reply; 12+ messages in thread From: Claudiu Beznea @ 2020-12-16 12:57 UTC (permalink / raw) To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni, ludovic.desroches, sre Cc: devicetree, linux-arm-kernel, linux-kernel, linux-pm, Claudiu Beznea According to datasheet WKUPDBC mask is b/w bits 26..24. Fixes: f80cb48843987 ("power: reset: at91-shdwc: add new shutdown controller driver") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> --- drivers/power/reset/at91-sama5d2_shdwc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/reset/at91-sama5d2_shdwc.c b/drivers/power/reset/at91-sama5d2_shdwc.c index e90368ed6f71..3996167f676f 100644 --- a/drivers/power/reset/at91-sama5d2_shdwc.c +++ b/drivers/power/reset/at91-sama5d2_shdwc.c @@ -37,7 +37,7 @@ #define AT91_SHDW_MR 0x04 /* Shut Down Mode Register */ #define AT91_SHDW_WKUPDBC_SHIFT 24 -#define AT91_SHDW_WKUPDBC_MASK GENMASK(31, 16) +#define AT91_SHDW_WKUPDBC_MASK GENMASK(26, 24) #define AT91_SHDW_WKUPDBC(x) (((x) << AT91_SHDW_WKUPDBC_SHIFT) \ & AT91_SHDW_WKUPDBC_MASK) -- 2.7.4 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 1/3] power: reset: at91-sama5d2_shdwc: fix wkupdbc mask 2020-12-16 12:57 ` [PATCH 1/3] power: reset: at91-sama5d2_shdwc: fix wkupdbc mask Claudiu Beznea @ 2020-12-16 13:40 ` Alexandre Belloni 0 siblings, 0 replies; 12+ messages in thread From: Alexandre Belloni @ 2020-12-16 13:40 UTC (permalink / raw) To: Claudiu Beznea Cc: robh+dt, mark.rutland, nicolas.ferre, ludovic.desroches, sre, devicetree, linux-arm-kernel, linux-kernel, linux-pm On 16/12/2020 14:57:31+0200, Claudiu Beznea wrote: > According to datasheet WKUPDBC mask is b/w bits 26..24. > > Fixes: f80cb48843987 ("power: reset: at91-shdwc: add new shutdown controller driver") > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> > --- > drivers/power/reset/at91-sama5d2_shdwc.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/power/reset/at91-sama5d2_shdwc.c b/drivers/power/reset/at91-sama5d2_shdwc.c > index e90368ed6f71..3996167f676f 100644 > --- a/drivers/power/reset/at91-sama5d2_shdwc.c > +++ b/drivers/power/reset/at91-sama5d2_shdwc.c > @@ -37,7 +37,7 @@ > > #define AT91_SHDW_MR 0x04 /* Shut Down Mode Register */ > #define AT91_SHDW_WKUPDBC_SHIFT 24 > -#define AT91_SHDW_WKUPDBC_MASK GENMASK(31, 16) > +#define AT91_SHDW_WKUPDBC_MASK GENMASK(26, 24) > #define AT91_SHDW_WKUPDBC(x) (((x) << AT91_SHDW_WKUPDBC_SHIFT) \ > & AT91_SHDW_WKUPDBC_MASK) > Maybe you would switch to FIELD_PREP to remove the need for 2 of those 3 macros and would have made the issue apparent right away. -- Alexandre Belloni, Bootlin Embedded Linux and Kernel engineering https://bootlin.com ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 2/3] dt-bindings: atmel-sysreg: add microchip,sama7g5-shdwc 2020-12-16 12:57 [PATCH 0/3] power: reset: at91-sama5d2_shdwc: add support for SAMA7G5 Claudiu Beznea 2020-12-16 12:57 ` [PATCH 1/3] power: reset: at91-sama5d2_shdwc: fix wkupdbc mask Claudiu Beznea @ 2020-12-16 12:57 ` Claudiu Beznea 2020-12-16 13:41 ` Alexandre Belloni 2020-12-21 19:37 ` Rob Herring 2020-12-16 12:57 ` [PATCH 3/3] power: reset: at91-sama5d2_shdwc: add support for sama7g5 Claudiu Beznea 2021-01-16 13:58 ` [PATCH 0/3] power: reset: at91-sama5d2_shdwc: add support for SAMA7G5 Sebastian Reichel 3 siblings, 2 replies; 12+ messages in thread From: Claudiu Beznea @ 2020-12-16 12:57 UTC (permalink / raw) To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni, ludovic.desroches, sre Cc: devicetree, linux-arm-kernel, linux-kernel, linux-pm, Claudiu Beznea Add compatible for Microchip SAMA7G5's shutdown controller. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> --- Documentation/devicetree/bindings/arm/atmel-sysregs.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt index 62cd4e89817c..7990358ac06e 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -91,7 +91,8 @@ SHDWC SAMA5D2-Compatible Shutdown Controller 1) shdwc node required properties: -- compatible: should be "atmel,sama5d2-shdwc" or "microchip,sam9x60-shdwc". +- compatible: should be "atmel,sama5d2-shdwc", "microchip,sam9x60-shdwc" or + "microchip,sama7g5-shdwc" - reg: should contain registers location and length - clocks: phandle to input clock. - #address-cells: should be one. The cell is the wake-up input index. @@ -103,7 +104,7 @@ optional properties: microseconds. It's usually a board-related property. - atmel,wakeup-rtc-timer: boolean to enable Real-Time Clock wake-up. -optional microchip,sam9x60-shdwc properties: +optional microchip,sam9x60-shdwc or microchip,sama7g5-shdwc properties: - atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up. The node contains child nodes for each wake-up input that the platform uses. -- 2.7.4 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 2/3] dt-bindings: atmel-sysreg: add microchip,sama7g5-shdwc 2020-12-16 12:57 ` [PATCH 2/3] dt-bindings: atmel-sysreg: add microchip,sama7g5-shdwc Claudiu Beznea @ 2020-12-16 13:41 ` Alexandre Belloni 2020-12-21 19:37 ` Rob Herring 2020-12-21 19:37 ` Rob Herring 1 sibling, 1 reply; 12+ messages in thread From: Alexandre Belloni @ 2020-12-16 13:41 UTC (permalink / raw) To: Claudiu Beznea Cc: robh+dt, mark.rutland, nicolas.ferre, ludovic.desroches, sre, devicetree, linux-arm-kernel, linux-kernel, linux-pm On 16/12/2020 14:57:32+0200, Claudiu Beznea wrote: > Add compatible for Microchip SAMA7G5's shutdown controller. > > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> > --- > Documentation/devicetree/bindings/arm/atmel-sysregs.txt | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) I'm pretty sure the first comment you'll get is to convert this file to yaml ;) > > diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt > index 62cd4e89817c..7990358ac06e 100644 > --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt > +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt > @@ -91,7 +91,8 @@ SHDWC SAMA5D2-Compatible Shutdown Controller > 1) shdwc node > > required properties: > -- compatible: should be "atmel,sama5d2-shdwc" or "microchip,sam9x60-shdwc". > +- compatible: should be "atmel,sama5d2-shdwc", "microchip,sam9x60-shdwc" or > + "microchip,sama7g5-shdwc" > - reg: should contain registers location and length > - clocks: phandle to input clock. > - #address-cells: should be one. The cell is the wake-up input index. > @@ -103,7 +104,7 @@ optional properties: > microseconds. It's usually a board-related property. > - atmel,wakeup-rtc-timer: boolean to enable Real-Time Clock wake-up. > > -optional microchip,sam9x60-shdwc properties: > +optional microchip,sam9x60-shdwc or microchip,sama7g5-shdwc properties: > - atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up. > > The node contains child nodes for each wake-up input that the platform uses. > -- > 2.7.4 > -- Alexandre Belloni, Bootlin Embedded Linux and Kernel engineering https://bootlin.com ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/3] dt-bindings: atmel-sysreg: add microchip,sama7g5-shdwc 2020-12-16 13:41 ` Alexandre Belloni @ 2020-12-21 19:37 ` Rob Herring 0 siblings, 0 replies; 12+ messages in thread From: Rob Herring @ 2020-12-21 19:37 UTC (permalink / raw) To: Alexandre Belloni Cc: Claudiu Beznea, mark.rutland, nicolas.ferre, ludovic.desroches, sre, devicetree, linux-arm-kernel, linux-kernel, linux-pm On Wed, Dec 16, 2020 at 02:41:00PM +0100, Alexandre Belloni wrote: > On 16/12/2020 14:57:32+0200, Claudiu Beznea wrote: > > Add compatible for Microchip SAMA7G5's shutdown controller. > > > > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> > > --- > > Documentation/devicetree/bindings/arm/atmel-sysregs.txt | 5 +++-- > > 1 file changed, 3 insertions(+), 2 deletions(-) > > I'm pretty sure the first comment you'll get is to convert this file to > yaml ;) I certainly wouldn't object, but just for a new compatible not requiring that (yet). > > diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt > > index 62cd4e89817c..7990358ac06e 100644 > > --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt > > +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt > > @@ -91,7 +91,8 @@ SHDWC SAMA5D2-Compatible Shutdown Controller > > 1) shdwc node > > > > required properties: > > -- compatible: should be "atmel,sama5d2-shdwc" or "microchip,sam9x60-shdwc". > > +- compatible: should be "atmel,sama5d2-shdwc", "microchip,sam9x60-shdwc" or > > + "microchip,sama7g5-shdwc" > > - reg: should contain registers location and length > > - clocks: phandle to input clock. > > - #address-cells: should be one. The cell is the wake-up input index. > > @@ -103,7 +104,7 @@ optional properties: > > microseconds. It's usually a board-related property. > > - atmel,wakeup-rtc-timer: boolean to enable Real-Time Clock wake-up. > > > > -optional microchip,sam9x60-shdwc properties: > > +optional microchip,sam9x60-shdwc or microchip,sama7g5-shdwc properties: > > - atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up. > > > > The node contains child nodes for each wake-up input that the platform uses. > > -- > > 2.7.4 > > > > -- > Alexandre Belloni, Bootlin > Embedded Linux and Kernel engineering > https://bootlin.com ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/3] dt-bindings: atmel-sysreg: add microchip,sama7g5-shdwc 2020-12-16 12:57 ` [PATCH 2/3] dt-bindings: atmel-sysreg: add microchip,sama7g5-shdwc Claudiu Beznea 2020-12-16 13:41 ` Alexandre Belloni @ 2020-12-21 19:37 ` Rob Herring 1 sibling, 0 replies; 12+ messages in thread From: Rob Herring @ 2020-12-21 19:37 UTC (permalink / raw) To: Claudiu Beznea Cc: ludovic.desroches, alexandre.belloni, sre, nicolas.ferre, mark.rutland, devicetree, linux-arm-kernel, robh+dt, linux-pm, linux-kernel On Wed, 16 Dec 2020 14:57:32 +0200, Claudiu Beznea wrote: > Add compatible for Microchip SAMA7G5's shutdown controller. > > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> > --- > Documentation/devicetree/bindings/arm/atmel-sysregs.txt | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 3/3] power: reset: at91-sama5d2_shdwc: add support for sama7g5 2020-12-16 12:57 [PATCH 0/3] power: reset: at91-sama5d2_shdwc: add support for SAMA7G5 Claudiu Beznea 2020-12-16 12:57 ` [PATCH 1/3] power: reset: at91-sama5d2_shdwc: fix wkupdbc mask Claudiu Beznea 2020-12-16 12:57 ` [PATCH 2/3] dt-bindings: atmel-sysreg: add microchip,sama7g5-shdwc Claudiu Beznea @ 2020-12-16 12:57 ` Claudiu Beznea 2020-12-16 13:45 ` Alexandre Belloni 2021-01-16 13:58 ` [PATCH 0/3] power: reset: at91-sama5d2_shdwc: add support for SAMA7G5 Sebastian Reichel 3 siblings, 1 reply; 12+ messages in thread From: Claudiu Beznea @ 2020-12-16 12:57 UTC (permalink / raw) To: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni, ludovic.desroches, sre Cc: devicetree, linux-arm-kernel, linux-kernel, linux-pm, Claudiu Beznea Add support for SAMA7G5 by adding proper struct reg_config structure and since SAMA7G5 is not currently on LPDDR setups the commit also avoid the mapping of DDR controller. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> --- drivers/power/reset/at91-sama5d2_shdwc.c | 72 ++++++++++++++++++++++++-------- 1 file changed, 54 insertions(+), 18 deletions(-) diff --git a/drivers/power/reset/at91-sama5d2_shdwc.c b/drivers/power/reset/at91-sama5d2_shdwc.c index 3996167f676f..a3342c8c3728 100644 --- a/drivers/power/reset/at91-sama5d2_shdwc.c +++ b/drivers/power/reset/at91-sama5d2_shdwc.c @@ -78,9 +78,15 @@ struct pmc_reg_config { u8 mckr; }; +struct ddrc_reg_config { + u32 type_offset; + u32 type_mask; +}; + struct reg_config { struct shdwc_reg_config shdwc; struct pmc_reg_config pmc; + struct ddrc_reg_config ddrc; }; struct shdwc { @@ -262,6 +268,10 @@ static const struct reg_config sama5d2_reg_config = { .pmc = { .mckr = 0x30, }, + .ddrc = { + .type_offset = AT91_DDRSDRC_MDR, + .type_mask = AT91_DDRSDRC_MD + }, }; static const struct reg_config sam9x60_reg_config = { @@ -275,6 +285,23 @@ static const struct reg_config sam9x60_reg_config = { .pmc = { .mckr = 0x28, }, + .ddrc = { + .type_offset = AT91_DDRSDRC_MDR, + .type_mask = AT91_DDRSDRC_MD + }, +}; + +static const struct reg_config sama7g5_reg_config = { + .shdwc = { + .wkup_pin_input = 0, + .mr_rtcwk_shift = 17, + .mr_rttwk_shift = 16, + .sr_rtcwk_shift = 5, + .sr_rttwk_shift = 4, + }, + .pmc = { + .mckr = 0x28, + }, }; static const struct of_device_id at91_shdwc_of_match[] = { @@ -285,6 +312,10 @@ static const struct of_device_id at91_shdwc_of_match[] = { { .compatible = "microchip,sam9x60-shdwc", .data = &sam9x60_reg_config, + }, + { + .compatible = "microchip,sama7g5-shdwc", + .data = &sama7g5_reg_config, }, { /*sentinel*/ } @@ -294,6 +325,7 @@ MODULE_DEVICE_TABLE(of, at91_shdwc_of_match); static const struct of_device_id at91_pmc_ids[] = { { .compatible = "atmel,sama5d2-pmc" }, { .compatible = "microchip,sam9x60-pmc" }, + { .compatible = "microchip,sama7g5-pmc" }, { /* Sentinel. */ } }; @@ -355,30 +387,34 @@ static int __init at91_shdwc_probe(struct platform_device *pdev) goto clk_disable; } - np = of_find_compatible_node(NULL, NULL, "atmel,sama5d3-ddramc"); - if (!np) { - ret = -ENODEV; - goto unmap; - } + if (at91_shdwc->rcfg->ddrc.type_mask) { + np = of_find_compatible_node(NULL, NULL, + "atmel,sama5d3-ddramc"); + if (!np) { + ret = -ENODEV; + goto unmap; + } - at91_shdwc->mpddrc_base = of_iomap(np, 0); - of_node_put(np); + at91_shdwc->mpddrc_base = of_iomap(np, 0); + of_node_put(np); - if (!at91_shdwc->mpddrc_base) { - ret = -ENOMEM; - goto unmap; + if (!at91_shdwc->mpddrc_base) { + ret = -ENOMEM; + goto unmap; + } + + ddr_type = readl(at91_shdwc->mpddrc_base + + at91_shdwc->rcfg->ddrc.type_offset) & + at91_shdwc->rcfg->ddrc.type_mask; + if (ddr_type != AT91_DDRSDRC_MD_LPDDR2 && + ddr_type != AT91_DDRSDRC_MD_LPDDR3) { + iounmap(at91_shdwc->mpddrc_base); + at91_shdwc->mpddrc_base = NULL; + } } pm_power_off = at91_poweroff; - ddr_type = readl(at91_shdwc->mpddrc_base + AT91_DDRSDRC_MDR) & - AT91_DDRSDRC_MD; - if (ddr_type != AT91_DDRSDRC_MD_LPDDR2 && - ddr_type != AT91_DDRSDRC_MD_LPDDR3) { - iounmap(at91_shdwc->mpddrc_base); - at91_shdwc->mpddrc_base = NULL; - } - return 0; unmap: -- 2.7.4 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 3/3] power: reset: at91-sama5d2_shdwc: add support for sama7g5 2020-12-16 12:57 ` [PATCH 3/3] power: reset: at91-sama5d2_shdwc: add support for sama7g5 Claudiu Beznea @ 2020-12-16 13:45 ` Alexandre Belloni 2020-12-16 14:11 ` Claudiu.Beznea 2020-12-16 14:12 ` Claudiu.Beznea 0 siblings, 2 replies; 12+ messages in thread From: Alexandre Belloni @ 2020-12-16 13:45 UTC (permalink / raw) To: Claudiu Beznea Cc: robh+dt, mark.rutland, nicolas.ferre, ludovic.desroches, sre, devicetree, linux-arm-kernel, linux-kernel, linux-pm On 16/12/2020 14:57:33+0200, Claudiu Beznea wrote: > Add support for SAMA7G5 by adding proper struct reg_config structure > and since SAMA7G5 is not currently on LPDDR setups the commit also > avoid the mapping of DDR controller. > Honestly, I wouldn't leave the LPDDR part out because there is no guarantee anyone will think about it when they have a design with LPDDR and as a consequence, their device will behave properly but will be very short lived. > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> > --- > drivers/power/reset/at91-sama5d2_shdwc.c | 72 ++++++++++++++++++++++++-------- > 1 file changed, 54 insertions(+), 18 deletions(-) > > diff --git a/drivers/power/reset/at91-sama5d2_shdwc.c b/drivers/power/reset/at91-sama5d2_shdwc.c > index 3996167f676f..a3342c8c3728 100644 > --- a/drivers/power/reset/at91-sama5d2_shdwc.c > +++ b/drivers/power/reset/at91-sama5d2_shdwc.c > @@ -78,9 +78,15 @@ struct pmc_reg_config { > u8 mckr; > }; > > +struct ddrc_reg_config { > + u32 type_offset; > + u32 type_mask; > +}; > + > struct reg_config { > struct shdwc_reg_config shdwc; > struct pmc_reg_config pmc; > + struct ddrc_reg_config ddrc; > }; > > struct shdwc { > @@ -262,6 +268,10 @@ static const struct reg_config sama5d2_reg_config = { > .pmc = { > .mckr = 0x30, > }, > + .ddrc = { > + .type_offset = AT91_DDRSDRC_MDR, > + .type_mask = AT91_DDRSDRC_MD > + }, > }; > > static const struct reg_config sam9x60_reg_config = { > @@ -275,6 +285,23 @@ static const struct reg_config sam9x60_reg_config = { > .pmc = { > .mckr = 0x28, > }, > + .ddrc = { > + .type_offset = AT91_DDRSDRC_MDR, > + .type_mask = AT91_DDRSDRC_MD > + }, > +}; > + > +static const struct reg_config sama7g5_reg_config = { > + .shdwc = { > + .wkup_pin_input = 0, > + .mr_rtcwk_shift = 17, > + .mr_rttwk_shift = 16, > + .sr_rtcwk_shift = 5, > + .sr_rttwk_shift = 4, > + }, > + .pmc = { > + .mckr = 0x28, > + }, > }; > > static const struct of_device_id at91_shdwc_of_match[] = { > @@ -285,6 +312,10 @@ static const struct of_device_id at91_shdwc_of_match[] = { > { > .compatible = "microchip,sam9x60-shdwc", > .data = &sam9x60_reg_config, > + }, > + { > + .compatible = "microchip,sama7g5-shdwc", > + .data = &sama7g5_reg_config, > }, { > /*sentinel*/ > } > @@ -294,6 +325,7 @@ MODULE_DEVICE_TABLE(of, at91_shdwc_of_match); > static const struct of_device_id at91_pmc_ids[] = { > { .compatible = "atmel,sama5d2-pmc" }, > { .compatible = "microchip,sam9x60-pmc" }, > + { .compatible = "microchip,sama7g5-pmc" }, > { /* Sentinel. */ } > }; > > @@ -355,30 +387,34 @@ static int __init at91_shdwc_probe(struct platform_device *pdev) > goto clk_disable; > } > > - np = of_find_compatible_node(NULL, NULL, "atmel,sama5d3-ddramc"); > - if (!np) { > - ret = -ENODEV; > - goto unmap; > - } > + if (at91_shdwc->rcfg->ddrc.type_mask) { > + np = of_find_compatible_node(NULL, NULL, > + "atmel,sama5d3-ddramc"); > + if (!np) { > + ret = -ENODEV; > + goto unmap; > + } > > - at91_shdwc->mpddrc_base = of_iomap(np, 0); > - of_node_put(np); > + at91_shdwc->mpddrc_base = of_iomap(np, 0); > + of_node_put(np); > > - if (!at91_shdwc->mpddrc_base) { > - ret = -ENOMEM; > - goto unmap; > + if (!at91_shdwc->mpddrc_base) { > + ret = -ENOMEM; > + goto unmap; > + } > + > + ddr_type = readl(at91_shdwc->mpddrc_base + > + at91_shdwc->rcfg->ddrc.type_offset) & > + at91_shdwc->rcfg->ddrc.type_mask; > + if (ddr_type != AT91_DDRSDRC_MD_LPDDR2 && > + ddr_type != AT91_DDRSDRC_MD_LPDDR3) { > + iounmap(at91_shdwc->mpddrc_base); > + at91_shdwc->mpddrc_base = NULL; > + } > } > > pm_power_off = at91_poweroff; > > - ddr_type = readl(at91_shdwc->mpddrc_base + AT91_DDRSDRC_MDR) & > - AT91_DDRSDRC_MD; > - if (ddr_type != AT91_DDRSDRC_MD_LPDDR2 && > - ddr_type != AT91_DDRSDRC_MD_LPDDR3) { > - iounmap(at91_shdwc->mpddrc_base); > - at91_shdwc->mpddrc_base = NULL; > - } > - > return 0; > > unmap: > -- > 2.7.4 > -- Alexandre Belloni, Bootlin Embedded Linux and Kernel engineering https://bootlin.com ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 3/3] power: reset: at91-sama5d2_shdwc: add support for sama7g5 2020-12-16 13:45 ` Alexandre Belloni @ 2020-12-16 14:11 ` Claudiu.Beznea 2020-12-16 14:12 ` Claudiu.Beznea 1 sibling, 0 replies; 12+ messages in thread From: Claudiu.Beznea @ 2020-12-16 14:11 UTC (permalink / raw) To: alexandre.belloni Cc: robh+dt, mark.rutland, Nicolas.Ferre, Ludovic.Desroches, sre, devicetree, linux-arm-kernel, linux-kernel, linux-pm On 16.12.2020 15:45, Alexandre Belloni wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > On 16/12/2020 14:57:33+0200, Claudiu Beznea wrote: >> Add support for SAMA7G5 by adding proper struct reg_config structure >> and since SAMA7G5 is not currently on LPDDR setups the commit also >> avoid the mapping of DDR controller. >> > > Honestly, I wouldn't leave the LPDDR part out because there is no > guarantee anyone will think about it when they have a design with LPDDR > and as a consequence, their device will behave properly but will be > very short lived. The idea wasn't to leave it out. It has to be handled differently on SAMA7G5 as it embeds a different DDR controller. Thank you, Claudiu > >> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> >> --- >> drivers/power/reset/at91-sama5d2_shdwc.c | 72 ++++++++++++++++++++++++-------- >> 1 file changed, 54 insertions(+), 18 deletions(-) >> >> diff --git a/drivers/power/reset/at91-sama5d2_shdwc.c b/drivers/power/reset/at91-sama5d2_shdwc.c >> index 3996167f676f..a3342c8c3728 100644 >> --- a/drivers/power/reset/at91-sama5d2_shdwc.c >> +++ b/drivers/power/reset/at91-sama5d2_shdwc.c >> @@ -78,9 +78,15 @@ struct pmc_reg_config { >> u8 mckr; >> }; >> >> +struct ddrc_reg_config { >> + u32 type_offset; >> + u32 type_mask; >> +}; >> + >> struct reg_config { >> struct shdwc_reg_config shdwc; >> struct pmc_reg_config pmc; >> + struct ddrc_reg_config ddrc; >> }; >> >> struct shdwc { >> @@ -262,6 +268,10 @@ static const struct reg_config sama5d2_reg_config = { >> .pmc = { >> .mckr = 0x30, >> }, >> + .ddrc = { >> + .type_offset = AT91_DDRSDRC_MDR, >> + .type_mask = AT91_DDRSDRC_MD >> + }, >> }; >> >> static const struct reg_config sam9x60_reg_config = { >> @@ -275,6 +285,23 @@ static const struct reg_config sam9x60_reg_config = { >> .pmc = { >> .mckr = 0x28, >> }, >> + .ddrc = { >> + .type_offset = AT91_DDRSDRC_MDR, >> + .type_mask = AT91_DDRSDRC_MD >> + }, >> +}; >> + >> +static const struct reg_config sama7g5_reg_config = { >> + .shdwc = { >> + .wkup_pin_input = 0, >> + .mr_rtcwk_shift = 17, >> + .mr_rttwk_shift = 16, >> + .sr_rtcwk_shift = 5, >> + .sr_rttwk_shift = 4, >> + }, >> + .pmc = { >> + .mckr = 0x28, >> + }, >> }; >> >> static const struct of_device_id at91_shdwc_of_match[] = { >> @@ -285,6 +312,10 @@ static const struct of_device_id at91_shdwc_of_match[] = { >> { >> .compatible = "microchip,sam9x60-shdwc", >> .data = &sam9x60_reg_config, >> + }, >> + { >> + .compatible = "microchip,sama7g5-shdwc", >> + .data = &sama7g5_reg_config, >> }, { >> /*sentinel*/ >> } >> @@ -294,6 +325,7 @@ MODULE_DEVICE_TABLE(of, at91_shdwc_of_match); >> static const struct of_device_id at91_pmc_ids[] = { >> { .compatible = "atmel,sama5d2-pmc" }, >> { .compatible = "microchip,sam9x60-pmc" }, >> + { .compatible = "microchip,sama7g5-pmc" }, >> { /* Sentinel. */ } >> }; >> >> @@ -355,30 +387,34 @@ static int __init at91_shdwc_probe(struct platform_device *pdev) >> goto clk_disable; >> } >> >> - np = of_find_compatible_node(NULL, NULL, "atmel,sama5d3-ddramc"); >> - if (!np) { >> - ret = -ENODEV; >> - goto unmap; >> - } >> + if (at91_shdwc->rcfg->ddrc.type_mask) { >> + np = of_find_compatible_node(NULL, NULL, >> + "atmel,sama5d3-ddramc"); >> + if (!np) { >> + ret = -ENODEV; >> + goto unmap; >> + } >> >> - at91_shdwc->mpddrc_base = of_iomap(np, 0); >> - of_node_put(np); >> + at91_shdwc->mpddrc_base = of_iomap(np, 0); >> + of_node_put(np); >> >> - if (!at91_shdwc->mpddrc_base) { >> - ret = -ENOMEM; >> - goto unmap; >> + if (!at91_shdwc->mpddrc_base) { >> + ret = -ENOMEM; >> + goto unmap; >> + } >> + >> + ddr_type = readl(at91_shdwc->mpddrc_base + >> + at91_shdwc->rcfg->ddrc.type_offset) & >> + at91_shdwc->rcfg->ddrc.type_mask; >> + if (ddr_type != AT91_DDRSDRC_MD_LPDDR2 && >> + ddr_type != AT91_DDRSDRC_MD_LPDDR3) { >> + iounmap(at91_shdwc->mpddrc_base); >> + at91_shdwc->mpddrc_base = NULL; >> + } >> } >> >> pm_power_off = at91_poweroff; >> >> - ddr_type = readl(at91_shdwc->mpddrc_base + AT91_DDRSDRC_MDR) & >> - AT91_DDRSDRC_MD; >> - if (ddr_type != AT91_DDRSDRC_MD_LPDDR2 && >> - ddr_type != AT91_DDRSDRC_MD_LPDDR3) { >> - iounmap(at91_shdwc->mpddrc_base); >> - at91_shdwc->mpddrc_base = NULL; >> - } >> - >> return 0; >> >> unmap: >> -- >> 2.7.4 >> > > -- > Alexandre Belloni, Bootlin > Embedded Linux and Kernel engineering > https://bootlin.com > ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 3/3] power: reset: at91-sama5d2_shdwc: add support for sama7g5 2020-12-16 13:45 ` Alexandre Belloni 2020-12-16 14:11 ` Claudiu.Beznea @ 2020-12-16 14:12 ` Claudiu.Beznea 1 sibling, 0 replies; 12+ messages in thread From: Claudiu.Beznea @ 2020-12-16 14:12 UTC (permalink / raw) To: alexandre.belloni Cc: robh+dt, mark.rutland, Nicolas.Ferre, Ludovic.Desroches, sre, devicetree, linux-arm-kernel, linux-kernel, linux-pm On 16.12.2020 15:45, Alexandre Belloni wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > On 16/12/2020 14:57:33+0200, Claudiu Beznea wrote: >> Add support for SAMA7G5 by adding proper struct reg_config structure >> and since SAMA7G5 is not currently on LPDDR setups the commit also >> avoid the mapping of DDR controller. >> > > Honestly, I wouldn't leave the LPDDR part out because there is no > guarantee anyone will think about it when they have a design with LPDDR > and as a consequence, their device will behave properly but will be > very short lived. The idea wasn't to leave it out. It has to be handled differently on SAMA7G5 as it embeds a different DDR controller and at the moment we have no setup with LPDDR. Thank you, Claudiu > >> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> >> --- >> drivers/power/reset/at91-sama5d2_shdwc.c | 72 ++++++++++++++++++++++++-------- >> 1 file changed, 54 insertions(+), 18 deletions(-) >> >> diff --git a/drivers/power/reset/at91-sama5d2_shdwc.c b/drivers/power/reset/at91-sama5d2_shdwc.c >> index 3996167f676f..a3342c8c3728 100644 >> --- a/drivers/power/reset/at91-sama5d2_shdwc.c >> +++ b/drivers/power/reset/at91-sama5d2_shdwc.c >> @@ -78,9 +78,15 @@ struct pmc_reg_config { >> u8 mckr; >> }; >> >> +struct ddrc_reg_config { >> + u32 type_offset; >> + u32 type_mask; >> +}; >> + >> struct reg_config { >> struct shdwc_reg_config shdwc; >> struct pmc_reg_config pmc; >> + struct ddrc_reg_config ddrc; >> }; >> >> struct shdwc { >> @@ -262,6 +268,10 @@ static const struct reg_config sama5d2_reg_config = { >> .pmc = { >> .mckr = 0x30, >> }, >> + .ddrc = { >> + .type_offset = AT91_DDRSDRC_MDR, >> + .type_mask = AT91_DDRSDRC_MD >> + }, >> }; >> >> static const struct reg_config sam9x60_reg_config = { >> @@ -275,6 +285,23 @@ static const struct reg_config sam9x60_reg_config = { >> .pmc = { >> .mckr = 0x28, >> }, >> + .ddrc = { >> + .type_offset = AT91_DDRSDRC_MDR, >> + .type_mask = AT91_DDRSDRC_MD >> + }, >> +}; >> + >> +static const struct reg_config sama7g5_reg_config = { >> + .shdwc = { >> + .wkup_pin_input = 0, >> + .mr_rtcwk_shift = 17, >> + .mr_rttwk_shift = 16, >> + .sr_rtcwk_shift = 5, >> + .sr_rttwk_shift = 4, >> + }, >> + .pmc = { >> + .mckr = 0x28, >> + }, >> }; >> >> static const struct of_device_id at91_shdwc_of_match[] = { >> @@ -285,6 +312,10 @@ static const struct of_device_id at91_shdwc_of_match[] = { >> { >> .compatible = "microchip,sam9x60-shdwc", >> .data = &sam9x60_reg_config, >> + }, >> + { >> + .compatible = "microchip,sama7g5-shdwc", >> + .data = &sama7g5_reg_config, >> }, { >> /*sentinel*/ >> } >> @@ -294,6 +325,7 @@ MODULE_DEVICE_TABLE(of, at91_shdwc_of_match); >> static const struct of_device_id at91_pmc_ids[] = { >> { .compatible = "atmel,sama5d2-pmc" }, >> { .compatible = "microchip,sam9x60-pmc" }, >> + { .compatible = "microchip,sama7g5-pmc" }, >> { /* Sentinel. */ } >> }; >> >> @@ -355,30 +387,34 @@ static int __init at91_shdwc_probe(struct platform_device *pdev) >> goto clk_disable; >> } >> >> - np = of_find_compatible_node(NULL, NULL, "atmel,sama5d3-ddramc"); >> - if (!np) { >> - ret = -ENODEV; >> - goto unmap; >> - } >> + if (at91_shdwc->rcfg->ddrc.type_mask) { >> + np = of_find_compatible_node(NULL, NULL, >> + "atmel,sama5d3-ddramc"); >> + if (!np) { >> + ret = -ENODEV; >> + goto unmap; >> + } >> >> - at91_shdwc->mpddrc_base = of_iomap(np, 0); >> - of_node_put(np); >> + at91_shdwc->mpddrc_base = of_iomap(np, 0); >> + of_node_put(np); >> >> - if (!at91_shdwc->mpddrc_base) { >> - ret = -ENOMEM; >> - goto unmap; >> + if (!at91_shdwc->mpddrc_base) { >> + ret = -ENOMEM; >> + goto unmap; >> + } >> + >> + ddr_type = readl(at91_shdwc->mpddrc_base + >> + at91_shdwc->rcfg->ddrc.type_offset) & >> + at91_shdwc->rcfg->ddrc.type_mask; >> + if (ddr_type != AT91_DDRSDRC_MD_LPDDR2 && >> + ddr_type != AT91_DDRSDRC_MD_LPDDR3) { >> + iounmap(at91_shdwc->mpddrc_base); >> + at91_shdwc->mpddrc_base = NULL; >> + } >> } >> >> pm_power_off = at91_poweroff; >> >> - ddr_type = readl(at91_shdwc->mpddrc_base + AT91_DDRSDRC_MDR) & >> - AT91_DDRSDRC_MD; >> - if (ddr_type != AT91_DDRSDRC_MD_LPDDR2 && >> - ddr_type != AT91_DDRSDRC_MD_LPDDR3) { >> - iounmap(at91_shdwc->mpddrc_base); >> - at91_shdwc->mpddrc_base = NULL; >> - } >> - >> return 0; >> >> unmap: >> -- >> 2.7.4 >> > > -- > Alexandre Belloni, Bootlin > Embedded Linux and Kernel engineering > https://bootlin.com > ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 0/3] power: reset: at91-sama5d2_shdwc: add support for SAMA7G5 2020-12-16 12:57 [PATCH 0/3] power: reset: at91-sama5d2_shdwc: add support for SAMA7G5 Claudiu Beznea ` (2 preceding siblings ...) 2020-12-16 12:57 ` [PATCH 3/3] power: reset: at91-sama5d2_shdwc: add support for sama7g5 Claudiu Beznea @ 2021-01-16 13:58 ` Sebastian Reichel 3 siblings, 0 replies; 12+ messages in thread From: Sebastian Reichel @ 2021-01-16 13:58 UTC (permalink / raw) To: Claudiu Beznea Cc: robh+dt, mark.rutland, nicolas.ferre, alexandre.belloni, ludovic.desroches, devicetree, linux-arm-kernel, linux-kernel, linux-pm [-- Attachment #1: Type: text/plain, Size: 615 bytes --] Hi, On Wed, Dec 16, 2020 at 02:57:30PM +0200, Claudiu Beznea wrote: > This series adds support for SAMA7G5 shutdown controller. > > Thank you, > Claudiu Beznea > > Claudiu Beznea (3): > power: reset: at91-sama5d2_shdwc: fix wkupdbc mask > dt-bindings: atmel-sysreg: add microchip,sama7g5-shdwc > power: reset: at91-sama5d2_shdwc: add support for sama7g5 > > .../devicetree/bindings/arm/atmel-sysregs.txt | 5 +- > drivers/power/reset/at91-sama5d2_shdwc.c | 74 ++++++++++++++++------ > 2 files changed, 58 insertions(+), 21 deletions(-) Thanks, queued. -- Sebastian [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 833 bytes --] ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2021-01-16 17:13 UTC | newest] Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-12-16 12:57 [PATCH 0/3] power: reset: at91-sama5d2_shdwc: add support for SAMA7G5 Claudiu Beznea 2020-12-16 12:57 ` [PATCH 1/3] power: reset: at91-sama5d2_shdwc: fix wkupdbc mask Claudiu Beznea 2020-12-16 13:40 ` Alexandre Belloni 2020-12-16 12:57 ` [PATCH 2/3] dt-bindings: atmel-sysreg: add microchip,sama7g5-shdwc Claudiu Beznea 2020-12-16 13:41 ` Alexandre Belloni 2020-12-21 19:37 ` Rob Herring 2020-12-21 19:37 ` Rob Herring 2020-12-16 12:57 ` [PATCH 3/3] power: reset: at91-sama5d2_shdwc: add support for sama7g5 Claudiu Beznea 2020-12-16 13:45 ` Alexandre Belloni 2020-12-16 14:11 ` Claudiu.Beznea 2020-12-16 14:12 ` Claudiu.Beznea 2021-01-16 13:58 ` [PATCH 0/3] power: reset: at91-sama5d2_shdwc: add support for SAMA7G5 Sebastian Reichel
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