* [PATCH] clk: ingenic: Fix divider calculation with div tables
@ 2020-12-12 13:57 Paul Cercueil
2020-12-20 0:05 ` Stephen Boyd
0 siblings, 1 reply; 2+ messages in thread
From: Paul Cercueil @ 2020-12-12 13:57 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: od, linux-clk, linux-kernel, Paul Cercueil, stable
The previous code assumed that a higher hardware value always resulted
in a bigger divider, which is correct for the regular clocks, but is
an invalid assumption when a divider table is provided for the clock.
Perfect example of this is the PLL0_HALF clock, which applies a /2
divider with the hardware value 0, and a /1 divider otherwise.
Fixes: a9fa2893fcc6 ("clk: ingenic: Add support for divider tables")
Cc: <stable@vger.kernel.org> # 5.2
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
drivers/clk/ingenic/cgu.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c
index dac6edc670cc..c8e9cb6c8e39 100644
--- a/drivers/clk/ingenic/cgu.c
+++ b/drivers/clk/ingenic/cgu.c
@@ -392,15 +392,21 @@ static unsigned int
ingenic_clk_calc_hw_div(const struct ingenic_cgu_clk_info *clk_info,
unsigned int div)
{
- unsigned int i;
+ unsigned int i, best_i = 0, best = (unsigned int)-1;
for (i = 0; i < (1 << clk_info->div.bits)
&& clk_info->div.div_table[i]; i++) {
- if (clk_info->div.div_table[i] >= div)
- return i;
+ if (clk_info->div.div_table[i] >= div &&
+ clk_info->div.div_table[i] < best) {
+ best = clk_info->div.div_table[i];
+ best_i = i;
+
+ if (div == best)
+ break;
+ }
}
- return i - 1;
+ return best_i;
}
static unsigned
--
2.29.2
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] clk: ingenic: Fix divider calculation with div tables
2020-12-12 13:57 [PATCH] clk: ingenic: Fix divider calculation with div tables Paul Cercueil
@ 2020-12-20 0:05 ` Stephen Boyd
0 siblings, 0 replies; 2+ messages in thread
From: Stephen Boyd @ 2020-12-20 0:05 UTC (permalink / raw)
To: Michael Turquette, Paul Cercueil
Cc: od, linux-clk, linux-kernel, Paul Cercueil, stable
Quoting Paul Cercueil (2020-12-12 05:57:33)
> The previous code assumed that a higher hardware value always resulted
> in a bigger divider, which is correct for the regular clocks, but is
> an invalid assumption when a divider table is provided for the clock.
>
> Perfect example of this is the PLL0_HALF clock, which applies a /2
> divider with the hardware value 0, and a /1 divider otherwise.
>
> Fixes: a9fa2893fcc6 ("clk: ingenic: Add support for divider tables")
> Cc: <stable@vger.kernel.org> # 5.2
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 2+ messages in thread
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