* [PATCH 1/1] iommu/arm-smmu-v3: add bit field SFM into GERROR_ERR_MASK
@ 2021-03-24 8:16 Zhen Lei
2021-03-25 18:09 ` Will Deacon
0 siblings, 1 reply; 2+ messages in thread
From: Zhen Lei @ 2021-03-24 8:16 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Joerg Roedel, linux-arm-kernel, iommu,
linux-kernel
Cc: Zhen Lei, Rui Zhu
In arm_smmu_gerror_handler(), the value of the SMMU_GERROR register is
filtered by GERROR_ERR_MASK. However, the GERROR_ERR_MASK does not contain
the SFM bit. As a result, the subsequent error processing is not performed
when only the SFM error occurs.
Fixes: 48ec83bcbcf5 ("iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices")
Reported-by: Rui Zhu <zhurui3@huawei.com>
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
index f985817c967a257..230b6f6b39016cd 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
@@ -115,7 +115,7 @@
#define GERROR_PRIQ_ABT_ERR (1 << 3)
#define GERROR_EVTQ_ABT_ERR (1 << 2)
#define GERROR_CMDQ_ERR (1 << 0)
-#define GERROR_ERR_MASK 0xfd
+#define GERROR_ERR_MASK 0x1fd
#define ARM_SMMU_GERRORN 0x64
--
2.26.0.106.g9fadedd
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH 1/1] iommu/arm-smmu-v3: add bit field SFM into GERROR_ERR_MASK
2021-03-24 8:16 [PATCH 1/1] iommu/arm-smmu-v3: add bit field SFM into GERROR_ERR_MASK Zhen Lei
@ 2021-03-25 18:09 ` Will Deacon
0 siblings, 0 replies; 2+ messages in thread
From: Will Deacon @ 2021-03-25 18:09 UTC (permalink / raw)
To: Joerg Roedel, Zhen Lei, iommu, linux-kernel, Robin Murphy,
linux-arm-kernel
Cc: catalin.marinas, kernel-team, Will Deacon, Rui Zhu
On Wed, 24 Mar 2021 16:16:03 +0800, Zhen Lei wrote:
> In arm_smmu_gerror_handler(), the value of the SMMU_GERROR register is
> filtered by GERROR_ERR_MASK. However, the GERROR_ERR_MASK does not contain
> the SFM bit. As a result, the subsequent error processing is not performed
> when only the SFM error occurs.
Applied to will (for-joerg/arm-smmu/updates), thanks!
[1/1] iommu/arm-smmu-v3: add bit field SFM into GERROR_ERR_MASK
https://git.kernel.org/will/c/655c447c97d7
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
^ permalink raw reply [flat|nested] 2+ messages in thread
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