[RFC PATCH 0/2] Add SDPM clock monitor driver

[RFC PATCH 0/2] Add SDPM clock monitor driver

[Manaf Meethalavalappu Pallikunhi]

RDPM (Rail digital power meter) hardware for a shared rail will
monitor for peak current management. It allocates one simple digital
power monitor(SDPM) for each major consumer of that rail. Each SDPM
estimates the power consumption of the consumer based on operating
frequency for that consumer. The RDPM hardware then aggregates all
SDPMs power estimation and recommends different mitigation levels
based on aggregated power estimation is above or below rail power
consumption specification.

This patch series adds SDPM clock monitor driver which
tracks frequency of different consumers and writes the frequency
into respective SDPM registers. The driver gets the clock source
to monitor and the corresponding SDPM register for a consumer from
devicetree. The SDPM clock monitor driver registers for the clock
change notification for these clock sources and writes the new
frequency value into the SDPM register.

Changes:
* Add dt-binding documentation for sdpm clock monitor driver
* Add SDPM clock monitor driver

Manaf Meethalavalappu Pallikunhi (2):
  dt-bindings: soc: qcom: Add SDPM clock monitor driver documentation in
    yaml
  drivers: soc: qcom: Add SDPM clock monitor driver

 .../devicetree/bindings/soc/qcom/qcom-sdpm.yaml    |  68 +++++++
 drivers/soc/qcom/Kconfig                           |   8 +
 drivers/soc/qcom/Makefile                          |   1 +
 drivers/soc/qcom/sdpm_clk_monitor.c                | 217 +++++++++++++++++++++
 4 files changed, 294 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom-sdpm.yaml
 create mode 100644 drivers/soc/qcom/sdpm_clk_monitor.c

Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[RFC PATCH 1/2] dt-bindings: soc: qcom: Add SDPM clock monitor driver documentation in yaml

[Manaf Meethalavalappu Pallikunhi]

Add yaml documentation for SDPM clock monitor driver which will
register for clock rate change notification and writes the clock rate
into SDPM CSR register.

Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
---
 .../devicetree/bindings/soc/qcom/qcom-sdpm.yaml    | 68 ++++++++++++++++++++++
 1 file changed, 68 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom-sdpm.yaml

diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom-sdpm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom-sdpm.yaml
new file mode 100644
index 00000000..20df362
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom-sdpm.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom-sdpm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Simple Digital Power Meter(SDPM) clock monitoring
+
+maintainers:
+  - Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
+  - Ram Chandrasekar <rkumbako@codeaurora.org>
+
+description: |
+
+  SDPM is used to monitor the operating frequency of different clocks and based
+  on operating levels of different clients, RDPM (Rail Digital Power Meter)
+  hardware estimates total power consumption of a shared railway. The SDPM
+  clock monitor driver will register with the clock framework for rate change
+  notification of different clocks. These clock rate will be updated to SDPM.
+
+properties:
+  compatible:
+    enum:
+      - qcom,sdpm
+
+  reg:
+    items:
+      - description: RDPM hardware base address
+
+  clocks:
+    items:
+    minItems: 1
+    maxItems: 8
+    description: Different clock source
+
+  clock-names:
+    items:
+    minItems: 1
+    maxItems: 8
+    description: Different clock source name
+
+  csr-id:
+    $ref: '/schemas/types.yaml#/definitions/uint32-array'
+    description: SDPM CSR IDs matching the clock order mentioned in the
+                 clocks property.
+    minItems: 1
+    maxItems: 8
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - csr-id
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,camcc-sc7280.h>
+    #include <dt-bindings/clock/qcom,gcc-sc7280.h>
+    cx_sdpm@634000 {
+        compatible = "qcom,sdpm";
+        reg = <0x634000 0x1000>;
+        clocks = <&clock_camcc CAM_CC_IPE_0_CLK_SRC>,
+                <&clock_gcc GCC_GP1_CLK_SRC>;
+        clock-names = "cam_cc_ipe", "gcc_gp1";
+        csr-id = <5 7>;
+    };
+...
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [RFC PATCH 1/2] dt-bindings: soc: qcom: Add SDPM clock monitor driver documentation in yaml

[Rob Herring]

On Fri, 02 Apr 2021 12:29:06 +0530, Manaf Meethalavalappu Pallikunhi wrote:
> Add yaml documentation for SDPM clock monitor driver which will
> register for clock rate change notification and writes the clock rate
> into SDPM CSR register.
> 
> Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
> Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
> ---
>  .../devicetree/bindings/soc/qcom/qcom-sdpm.yaml    | 68 ++++++++++++++++++++++
>  1 file changed, 68 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom-sdpm.yaml
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:
./Documentation/devicetree/bindings/soc/qcom/qcom-sdpm.yaml:31:11: [error] empty value in block mapping (empty-values)
./Documentation/devicetree/bindings/soc/qcom/qcom-sdpm.yaml:37:11: [error] empty value in block mapping (empty-values)

dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/qcom/qcom-sdpm.yaml: properties:clock-names:items: 'anyOf' conditional failed, one must be fixed:
	None is not of type 'object', 'boolean'
	None is not of type 'array'
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/qcom/qcom-sdpm.yaml: properties:clocks:items: 'anyOf' conditional failed, one must be fixed:
	None is not of type 'object', 'boolean'
	None is not of type 'array'
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/qcom/qcom-sdpm.yaml: properties:clock-names:items: 'oneOf' conditional failed, one must be fixed:
	None is not of type 'object'
	None is not of type 'array'
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/qcom/qcom-sdpm.yaml: properties:clocks:items: 'oneOf' conditional failed, one must be fixed:
	None is not of type 'object'
	None is not of type 'array'
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/qcom/qcom-sdpm.yaml: 'additionalProperties' is a required property
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/qcom/qcom-sdpm.yaml: properties:clock-names:items: 'oneOf' conditional failed, one must be fixed:
	None is not of type 'object'
	None is not of type 'array'
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/qcom/qcom-sdpm.yaml: properties:clocks: 'oneOf' conditional failed, one must be fixed:
	/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/qcom/qcom-sdpm.yaml: properties:clocks: 'anyOf' conditional failed, one must be fixed:
		'items' is not one of ['maxItems', 'description', 'deprecated']
		'minItems' is not one of ['maxItems', 'description', 'deprecated']
		'items' is not one of ['description', 'deprecated', 'const', 'enum', 'minimum', 'maximum', 'multipleOf', 'default', '$ref']
		'minItems' is not one of ['description', 'deprecated', 'const', 'enum', 'minimum', 'maximum', 'multipleOf', 'default', '$ref']
		'maxItems' is not one of ['description', 'deprecated', 'const', 'enum', 'minimum', 'maximum', 'multipleOf', 'default', '$ref']
		/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/qcom/qcom-sdpm.yaml: properties:clocks:items: 'oneOf' conditional failed, one must be fixed:
			None is not of type 'object'
			None is not of type 'array'
		1 was expected
	'items' is not one of ['type', 'description', 'dependencies', 'properties', 'patternProperties', 'additionalProperties', 'unevaluatedProperties', 'deprecated', 'required', 'allOf', 'anyOf', 'oneOf', '$ref']
	'minItems' is not one of ['type', 'description', 'dependencies', 'properties', 'patternProperties', 'additionalProperties', 'unevaluatedProperties', 'deprecated', 'required', 'allOf', 'anyOf', 'oneOf', '$ref']
	'maxItems' is not one of ['type', 'description', 'dependencies', 'properties', 'patternProperties', 'additionalProperties', 'unevaluatedProperties', 'deprecated', 'required', 'allOf', 'anyOf', 'oneOf', '$ref']
	'type' is a required property
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/qcom/qcom-sdpm.yaml: ignoring, error in schema: properties: clocks: items
warning: no schema found in file: ./Documentation/devicetree/bindings/soc/qcom/qcom-sdpm.yaml
Documentation/devicetree/bindings/soc/qcom/qcom-sdpm.example.dts:19:18: fatal error: dt-bindings/clock/qcom,camcc-sc7280.h: No such file or directory
   19 |         #include <dt-bindings/clock/qcom,camcc-sc7280.h>
      |                  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:377: Documentation/devicetree/bindings/soc/qcom/qcom-sdpm.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1414: dt_binding_check] Error 2

See https://patchwork.ozlabs.org/patch/1461582

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.

[RFC PATCH 2/2] drivers: soc: qcom: Add SDPM clock monitor driver

[Manaf Meethalavalappu Pallikunhi]

Add SDPM clock monitor driver, which will register for clock rate
change notification and write the clock rate into SDPM CSR register.

Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
---
 drivers/soc/qcom/Kconfig            |   8 ++
 drivers/soc/qcom/Makefile           |   1 +
 drivers/soc/qcom/sdpm_clk_monitor.c | 217 ++++++++++++++++++++++++++++++++++++
 3 files changed, 226 insertions(+)
 create mode 100644 drivers/soc/qcom/sdpm_clk_monitor.c

diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index 9464ff4..1f04d69 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -237,4 +237,12 @@ config QCOM_APR
 	  used by audio driver to configure QDSP6
 	  ASM, ADM and AFE modules.
 
+config QCOM_SDPM_CLOCK_MONITOR
+	tristate "Qualcomm SDPM Clock Monitor"
+	depends on COMMON_CLK
+	help
+	    This enables the Qualcomm SDPM Clock Monitor. This driver can register
+	    for different clock rate change notifications and write the clock
+	    rate into the SDPM CSR register. This driver will receive the clock
+	    list and the CSR details from devicetree.
 endmenu
diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
index d658a10..4eef767 100644
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -29,3 +29,4 @@ obj-$(CONFIG_QCOM_RPMPD) += rpmpd.o
 obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) +=	kryo-l2-accessors.o
 obj-$(CONFIG_QCOM_LLCC_PERFMON) += llcc_perfmon.o
 obj-$(CONFIG_QCOM_MEMORY_DUMP_V2) += memory_dump_v2.o
+obj-$(CONFIG_QCOM_SDPM_CLOCK_MONITOR) += sdpm_clk_monitor.o
diff --git a/drivers/soc/qcom/sdpm_clk_monitor.c b/drivers/soc/qcom/sdpm_clk_monitor.c
new file mode 100644
index 00000000..1aee119
--- /dev/null
+++ b/drivers/soc/qcom/sdpm_clk_monitor.c
@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ */
+
+#define pr_fmt(fmt) "%s " fmt, KBUILD_MODNAME
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#define SDPM_DRIVER		"sdpm-clk-monitor"
+#define CSR_MAX_VAL		7
+#define CSR_OFFSET		0xF00
+#define FREQ_HZ_TO_MHZ(f)	DIV_ROUND_UP((f), 1000000)
+#define SDPM_CSR_OFFSET(id)	(CSR_OFFSET + (id * 4))
+
+struct sdpm_clk_instance;
+struct sdpm_clk_data {
+	struct list_head		sdpm_node;
+	struct notifier_block		clk_rate_nb;
+	struct clk			*clk;
+	const char			*clock_name;
+	uint32_t			csr_id;
+	struct sdpm_clk_instance	*sdpm_inst;
+};
+
+struct sdpm_clk_instance {
+	struct device			*dev;
+	void __iomem			*regmap;
+	struct list_head		sdpm_instances;
+};
+
+static void sdpm_csr_write(struct sdpm_clk_data *sdpm_data,
+				unsigned long clk_rate)
+{
+	struct sdpm_clk_instance *sdpm_inst = sdpm_data->sdpm_inst;
+
+	writel_relaxed(clk_rate, sdpm_inst->regmap +
+			SDPM_CSR_OFFSET(sdpm_data->csr_id));
+	dev_dbg(sdpm_inst->dev, "clock:%s offset:0x%x frequency:%u\n",
+			sdpm_data->clock_name,
+			SDPM_CSR_OFFSET(sdpm_data->csr_id),
+			clk_rate);
+}
+
+static int sdpm_clock_notifier(struct notifier_block *nb,
+					unsigned long event, void *data)
+{
+	struct clk_notifier_data *ndata = data;
+	struct sdpm_clk_data *sdpm_data = container_of(nb,
+				struct sdpm_clk_data, clk_rate_nb);
+
+	dev_dbg(sdpm_data->sdpm_inst->dev, "clock:%s event:%lu\n",
+			sdpm_data->clock_name, event);
+	switch (event) {
+	case PRE_RATE_CHANGE:
+		if (ndata->new_rate > ndata->old_rate)
+			sdpm_csr_write(sdpm_data,
+					FREQ_HZ_TO_MHZ(ndata->new_rate));
+		return NOTIFY_DONE;
+	case POST_RATE_CHANGE:
+		if (ndata->new_rate < ndata->old_rate)
+			sdpm_csr_write(sdpm_data,
+					FREQ_HZ_TO_MHZ(ndata->new_rate));
+		return NOTIFY_DONE;
+	case ABORT_RATE_CHANGE:
+		if (ndata->new_rate > ndata->old_rate)
+			sdpm_csr_write(sdpm_data,
+					FREQ_HZ_TO_MHZ(ndata->old_rate));
+		return NOTIFY_DONE;
+	default:
+		return NOTIFY_DONE;
+	}
+}
+
+static int sdpm_clk_device_remove(struct platform_device *pdev)
+{
+	struct sdpm_clk_instance *sdpm_inst =
+		(struct sdpm_clk_instance *)dev_get_drvdata(&pdev->dev);
+	struct sdpm_clk_data *sdpm_data = NULL, *next = NULL;
+
+	list_for_each_entry_safe(sdpm_data, next,
+			&sdpm_inst->sdpm_instances, sdpm_node) {
+		clk_notifier_unregister(sdpm_data->clk,
+					&sdpm_data->clk_rate_nb);
+		list_del(&sdpm_data->sdpm_node);
+	}
+
+	return 0;
+}
+
+static int sdpm_clk_device_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *dev_node = dev->of_node;
+	int ret = 0, idx = 0, clk_ct = 0, csr = 0, csr_ct = 0;
+	struct sdpm_clk_instance *sdpm_inst = NULL;
+	struct sdpm_clk_data *sdpm_data = NULL;
+	struct resource *res;
+
+	sdpm_inst = devm_kzalloc(dev, sizeof(*sdpm_inst), GFP_KERNEL);
+	if (!sdpm_inst)
+		return -ENOMEM;
+	sdpm_inst->dev = dev;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(dev, "Couldn't get MEM resource\n");
+		return -EINVAL;
+	}
+	dev_dbg(dev, "sdpm@0x%x size:%d\n", res->start,
+			resource_size(res));
+	dev_set_drvdata(dev, sdpm_inst);
+
+	sdpm_inst->regmap = devm_ioremap_resource(dev, res);
+	if (!sdpm_inst->regmap) {
+		dev_err(dev, "Couldn't get regmap\n");
+		return -EINVAL;
+	}
+
+	ret = of_property_count_strings(dev_node, "clock-names");
+	if (ret <= 0) {
+		dev_err(dev, "Couldn't get clock names. %d\n", ret);
+		return ret;
+	}
+	clk_ct = ret;
+	ret = of_property_count_u32_elems(dev_node, "csr-id");
+	if (ret <= 0) {
+		dev_err(dev, "Couldn't get csr ID array. %d\n", ret);
+		return ret;
+	}
+	csr_ct = ret;
+
+	if (csr_ct != clk_ct) {
+		dev_err(dev, "Invalid csr:%d and clk:%d count.\n", csr_ct,
+				clk_ct);
+		return -EINVAL;
+	}
+
+	INIT_LIST_HEAD(&sdpm_inst->sdpm_instances);
+
+	for (idx = 0; idx < clk_ct; idx++) {
+
+		sdpm_data = devm_kzalloc(dev, sizeof(*sdpm_data), GFP_KERNEL);
+		if (!sdpm_data) {
+			ret = -ENOMEM;
+			goto clk_err_exit;
+		}
+
+		ret = of_property_read_string_index(dev_node, "clock-names",
+				idx, &sdpm_data->clock_name);
+		if (ret < 0) {
+			dev_err(dev, "Couldn't get clk name index:%d. %d\n",
+					idx, ret);
+			goto clk_err_exit;
+		}
+
+		sdpm_data->clk = devm_clk_get(dev, sdpm_data->clock_name);
+		if (IS_ERR(sdpm_data->clk)) {
+			ret = PTR_ERR(sdpm_data->clk);
+			goto clk_err_exit;
+		}
+
+		ret = of_property_read_u32_index(dev_node, "csr-id", idx, &csr);
+		if (ret < 0) {
+			dev_err(dev, "Couldn't get CSR for index:%d. %d\n",
+					idx, ret);
+			goto clk_err_exit;
+		}
+
+		if (ret > CSR_MAX_VAL) {
+			dev_err(dev, "Invalid CSR %d\n", csr);
+			ret = -EINVAL;
+			goto clk_err_exit;
+		}
+
+		dev_dbg(dev, "SDPM clock:%s csr:%d initialized\n",
+				sdpm_data->clock_name, csr);
+		sdpm_data->csr_id = csr;
+		sdpm_data->sdpm_inst = sdpm_inst;
+		sdpm_data->clk_rate_nb.notifier_call = sdpm_clock_notifier;
+		sdpm_csr_write(sdpm_data,
+			FREQ_HZ_TO_MHZ(clk_get_rate(sdpm_data->clk)));
+		clk_notifier_register(sdpm_data->clk, &sdpm_data->clk_rate_nb);
+		list_add(&sdpm_data->sdpm_node, &sdpm_inst->sdpm_instances);
+	}
+
+	return 0;
+
+clk_err_exit:
+	sdpm_clk_device_remove(pdev);
+
+	return ret;
+}
+
+static const struct of_device_id sdpm_clk_device_match[] = {
+	{.compatible = "qcom,sdpm"},
+	{}
+};
+
+static struct platform_driver sdpm_clk_device_driver = {
+	.probe          = sdpm_clk_device_probe,
+	.remove         = sdpm_clk_device_remove,
+	.driver         = {
+		.name   = SDPM_DRIVER,
+		.of_match_table = sdpm_clk_device_match,
+	},
+};
+module_platform_driver(sdpm_clk_device_driver);
+
+MODULE_DESCRIPTION("Qualcomm Technologies, Inc. SDPM Clock Monitor Driver");
+MODULE_LICENSE("GPL v2");
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [RFC PATCH 2/2] drivers: soc: qcom: Add SDPM clock monitor driver

[AngeloGioacchino Del Regno]

Il 02/04/21 08:59, Manaf Meethalavalappu Pallikunhi ha scritto:
> Add SDPM clock monitor driver, which will register for clock rate
> change notification and write the clock rate into SDPM CSR register.
> 
> Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
> Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
> ---
>   drivers/soc/qcom/Kconfig            |   8 ++
>   drivers/soc/qcom/Makefile           |   1 +
>   drivers/soc/qcom/sdpm_clk_monitor.c | 217 ++++++++++++++++++++++++++++++++++++
>   3 files changed, 226 insertions(+)
>   create mode 100644 drivers/soc/qcom/sdpm_clk_monitor.c
> 
> diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
> index 9464ff4..1f04d69 100644
> --- a/drivers/soc/qcom/Kconfig
> +++ b/drivers/soc/qcom/Kconfig
> @@ -237,4 +237,12 @@ config QCOM_APR
>   	  used by audio driver to configure QDSP6
>   	  ASM, ADM and AFE modules.
>   
> +config QCOM_SDPM_CLOCK_MONITOR
> +	tristate "Qualcomm SDPM Clock Monitor"
> +	depends on COMMON_CLK
> +	help
> +	    This enables the Qualcomm SDPM Clock Monitor. This driver can register
> +	    for different clock rate change notifications and write the clock
> +	    rate into the SDPM CSR register. This driver will receive the clock
> +	    list and the CSR details from devicetree.
>   endmenu
> diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
> index d658a10..4eef767 100644
> --- a/drivers/soc/qcom/Makefile
> +++ b/drivers/soc/qcom/Makefile
> @@ -29,3 +29,4 @@ obj-$(CONFIG_QCOM_RPMPD) += rpmpd.o
>   obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) +=	kryo-l2-accessors.o
>   obj-$(CONFIG_QCOM_LLCC_PERFMON) += llcc_perfmon.o
>   obj-$(CONFIG_QCOM_MEMORY_DUMP_V2) += memory_dump_v2.o
> +obj-$(CONFIG_QCOM_SDPM_CLOCK_MONITOR) += sdpm_clk_monitor.o
> diff --git a/drivers/soc/qcom/sdpm_clk_monitor.c b/drivers/soc/qcom/sdpm_clk_monitor.c
> new file mode 100644
> index 00000000..1aee119
> --- /dev/null
> +++ b/drivers/soc/qcom/sdpm_clk_monitor.c
> @@ -0,0 +1,217 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
> + */
> +
> +#define pr_fmt(fmt) "%s " fmt, KBUILD_MODNAME
> +
> +#include <linux/clk.h>
> +#include <linux/err.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +
> +#define SDPM_DRIVER		"sdpm-clk-monitor"
> +#define CSR_MAX_VAL		7
> +#define CSR_OFFSET		0xF00
> +#define FREQ_HZ_TO_MHZ(f)	DIV_ROUND_UP((f), 1000000)
> +#define SDPM_CSR_OFFSET(id)	(CSR_OFFSET + (id * 4))
> +
> +struct sdpm_clk_instance;
> +struct sdpm_clk_data {
> +	struct list_head		sdpm_node;
> +	struct notifier_block		clk_rate_nb;
> +	struct clk			*clk;
> +	const char			*clock_name;
> +	uint32_t			csr_id;
> +	struct sdpm_clk_instance	*sdpm_inst;
> +};
> +
> +struct sdpm_clk_instance {
> +	struct device			*dev;
> +	void __iomem			*regmap;
> +	struct list_head		sdpm_instances;
> +};
> +
> +static void sdpm_csr_write(struct sdpm_clk_data *sdpm_data,
> +				unsigned long clk_rate)
> +{
> +	struct sdpm_clk_instance *sdpm_inst = sdpm_data->sdpm_inst;
> +
> +	writel_relaxed(clk_rate, sdpm_inst->regmap +
> +			SDPM_CSR_OFFSET(sdpm_data->csr_id));
> +	dev_dbg(sdpm_inst->dev, "clock:%s offset:0x%x frequency:%u\n",
> +			sdpm_data->clock_name,
> +			SDPM_CSR_OFFSET(sdpm_data->csr_id),
> +			clk_rate);
> +}
> +
> +static int sdpm_clock_notifier(struct notifier_block *nb,
> +					unsigned long event, void *data)
> +{
> +	struct clk_notifier_data *ndata = data;
> +	struct sdpm_clk_data *sdpm_data = container_of(nb,
> +				struct sdpm_clk_data, clk_rate_nb);
> +
> +	dev_dbg(sdpm_data->sdpm_inst->dev, "clock:%s event:%lu\n",
> +			sdpm_data->clock_name, event);
> +	switch (event) {
> +	case PRE_RATE_CHANGE:
> +		if (ndata->new_rate > ndata->old_rate)
> +			sdpm_csr_write(sdpm_data,
> +					FREQ_HZ_TO_MHZ(ndata->new_rate));
> +		return NOTIFY_DONE;
> +	case POST_RATE_CHANGE:
> +		if (ndata->new_rate < ndata->old_rate)
> +			sdpm_csr_write(sdpm_data,
> +					FREQ_HZ_TO_MHZ(ndata->new_rate));
> +		return NOTIFY_DONE;
> +	case ABORT_RATE_CHANGE:
> +		if (ndata->new_rate > ndata->old_rate)
> +			sdpm_csr_write(sdpm_data,
> +					FREQ_HZ_TO_MHZ(ndata->old_rate));
> +		return NOTIFY_DONE;
> +	default:
> +		return NOTIFY_DONE;
> +	}
> +}
> +
> +static int sdpm_clk_device_remove(struct platform_device *pdev)
> +{
> +	struct sdpm_clk_instance *sdpm_inst =
> +		(struct sdpm_clk_instance *)dev_get_drvdata(&pdev->dev);
> +	struct sdpm_clk_data *sdpm_data = NULL, *next = NULL;
> +
> +	list_for_each_entry_safe(sdpm_data, next,
> +			&sdpm_inst->sdpm_instances, sdpm_node) {
> +		clk_notifier_unregister(sdpm_data->clk,
> +					&sdpm_data->clk_rate_nb);
> +		list_del(&sdpm_data->sdpm_node);
> +	}
> +
> +	return 0;
> +}
> +
> +static int sdpm_clk_device_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct device_node *dev_node = dev->of_node;
> +	int ret = 0, idx = 0, clk_ct = 0, csr = 0, csr_ct = 0;
> +	struct sdpm_clk_instance *sdpm_inst = NULL;
> +	struct sdpm_clk_data *sdpm_data = NULL;
> +	struct resource *res;
> +
> +	sdpm_inst = devm_kzalloc(dev, sizeof(*sdpm_inst), GFP_KERNEL);
> +	if (!sdpm_inst)
> +		return -ENOMEM;
> +	sdpm_inst->dev = dev;
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	if (!res) {
> +		dev_err(dev, "Couldn't get MEM resource\n");
> +		return -EINVAL;
> +	}
> +	dev_dbg(dev, "sdpm@0x%x size:%d\n", res->start,
> +			resource_size(res));
> +	dev_set_drvdata(dev, sdpm_inst);
> +
> +	sdpm_inst->regmap = devm_ioremap_resource(dev, res);
> +	if (!sdpm_inst->regmap) {
> +		dev_err(dev, "Couldn't get regmap\n");
> +		return -EINVAL;
> +	}
> +
> +	ret = of_property_count_strings(dev_node, "clock-names");
> +	if (ret <= 0) {
> +		dev_err(dev, "Couldn't get clock names. %d\n", ret);
> +		return ret;
> +	}
> +	clk_ct = ret;
> +	ret = of_property_count_u32_elems(dev_node, "csr-id");
> +	if (ret <= 0) {
> +		dev_err(dev, "Couldn't get csr ID array. %d\n", ret);
> +		return ret;
> +	}
> +	csr_ct = ret;
> +
> +	if (csr_ct != clk_ct) {
> +		dev_err(dev, "Invalid csr:%d and clk:%d count.\n", csr_ct,
> +				clk_ct);
> +		return -EINVAL;
> +	}
> +
> +	INIT_LIST_HEAD(&sdpm_inst->sdpm_instances);
> +
> +	for (idx = 0; idx < clk_ct; idx++) {
> +
> +		sdpm_data = devm_kzalloc(dev, sizeof(*sdpm_data), GFP_KERNEL);
> +		if (!sdpm_data) {
> +			ret = -ENOMEM;
> +			goto clk_err_exit;
> +		}
> +
> +		ret = of_property_read_string_index(dev_node, "clock-names",
> +				idx, &sdpm_data->clock_name);
> +		if (ret < 0) {
> +			dev_err(dev, "Couldn't get clk name index:%d. %d\n",
> +					idx, ret);
> +			goto clk_err_exit;
> +		}
> +
> +		sdpm_data->clk = devm_clk_get(dev, sdpm_data->clock_name);
> +		if (IS_ERR(sdpm_data->clk)) {
> +			ret = PTR_ERR(sdpm_data->clk);
> +			goto clk_err_exit;
> +		}
> +
> +		ret = of_property_read_u32_index(dev_node, "csr-id", idx, &csr);
> +		if (ret < 0) {
> +			dev_err(dev, "Couldn't get CSR for index:%d. %d\n",
> +					idx, ret);
> +			goto clk_err_exit;
> +		}
> +
> +		if (ret > CSR_MAX_VAL) {
> +			dev_err(dev, "Invalid CSR %d\n", csr);
> +			ret = -EINVAL;
> +			goto clk_err_exit;
> +		}
> +
> +		dev_dbg(dev, "SDPM clock:%s csr:%d initialized\n",
> +				sdpm_data->clock_name, csr);
> +		sdpm_data->csr_id = csr;
> +		sdpm_data->sdpm_inst = sdpm_inst;
> +		sdpm_data->clk_rate_nb.notifier_call = sdpm_clock_notifier;
> +		sdpm_csr_write(sdpm_data,
> +			FREQ_HZ_TO_MHZ(clk_get_rate(sdpm_data->clk)));
> +		clk_notifier_register(sdpm_data->clk, &sdpm_data->clk_rate_nb);
> +		list_add(&sdpm_data->sdpm_node, &sdpm_inst->sdpm_instances);
> +	}
> +
> +	return 0;
> +
> +clk_err_exit:
> +	sdpm_clk_device_remove(pdev);
> +
> +	return ret;
> +}
> +
> +static const struct of_device_id sdpm_clk_device_match[] = {
> +	{.compatible = "qcom,sdpm"},
> +	{}
> +};
> +
> +static struct platform_driver sdpm_clk_device_driver = {
> +	.probe          = sdpm_clk_device_probe,
> +	.remove         = sdpm_clk_device_remove,
> +	.driver         = {
> +		.name   = SDPM_DRIVER,
> +		.of_match_table = sdpm_clk_device_match,
> +	},
> +};
> +module_platform_driver(sdpm_clk_device_driver);
> +
> +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. SDPM Clock Monitor Driver");
> +MODULE_LICENSE("GPL v2");
> 
Hello!

Thanks for the patch. A few things to point out:

Before getting into a big lack of time situation, I have written a 
functional driver for the Qualcomm System Performance Dynamic Monitoring 
(SPDM), which has to yet be cleaned up before sending.
This driver appears to be "SDPM" instead, but the finalities of this new 
block seem to be very similar - if not the same - as the SPDM.

My SPDM implementation was done as an interconnect driver, as that is 
actually controlling the bandwidth of the CCI on the SoC.


Is this block doing the same and/or anything similar?
In case it does, I suggest to look at my *still a bit dirty* (sorry!) 
driver for the SPDM-TZ.

Please, look at the last three commits from this branch:
https://github.com/SoMainline/linux/commits/angelo/v5.12-rc4-feat-spdmtz

Yours,
- Angelo

Re: [RFC PATCH 2/2] drivers: soc: qcom: Add SDPM clock monitor driver

[manafm]

On 2021-04-02 15:49, AngeloGioacchino Del Regno wrote:
> Il 02/04/21 08:59, Manaf Meethalavalappu Pallikunhi ha scritto:
>> Add SDPM clock monitor driver, which will register for clock rate
>> change notification and write the clock rate into SDPM CSR register.
>> 
>> Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
>> Signed-off-by: Manaf Meethalavalappu Pallikunhi 
>> <manafm@codeaurora.org>
>> ---
>>   drivers/soc/qcom/Kconfig            |   8 ++
>>   drivers/soc/qcom/Makefile           |   1 +
>>   drivers/soc/qcom/sdpm_clk_monitor.c | 217 
>> ++++++++++++++++++++++++++++++++++++
>>   3 files changed, 226 insertions(+)
>>   create mode 100644 drivers/soc/qcom/sdpm_clk_monitor.c
>> 
>> diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
>> index 9464ff4..1f04d69 100644
>> --- a/drivers/soc/qcom/Kconfig
>> +++ b/drivers/soc/qcom/Kconfig
>> @@ -237,4 +237,12 @@ config QCOM_APR
>>   	  used by audio driver to configure QDSP6
>>   	  ASM, ADM and AFE modules.
>>   +config QCOM_SDPM_CLOCK_MONITOR
>> +	tristate "Qualcomm SDPM Clock Monitor"
>> +	depends on COMMON_CLK
>> +	help
>> +	    This enables the Qualcomm SDPM Clock Monitor. This driver can 
>> register
>> +	    for different clock rate change notifications and write the 
>> clock
>> +	    rate into the SDPM CSR register. This driver will receive the 
>> clock
>> +	    list and the CSR details from devicetree.
>>   endmenu
>> diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
>> index d658a10..4eef767 100644
>> --- a/drivers/soc/qcom/Makefile
>> +++ b/drivers/soc/qcom/Makefile
>> @@ -29,3 +29,4 @@ obj-$(CONFIG_QCOM_RPMPD) += rpmpd.o
>>   obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) +=	kryo-l2-accessors.o
>>   obj-$(CONFIG_QCOM_LLCC_PERFMON) += llcc_perfmon.o
>>   obj-$(CONFIG_QCOM_MEMORY_DUMP_V2) += memory_dump_v2.o
>> +obj-$(CONFIG_QCOM_SDPM_CLOCK_MONITOR) += sdpm_clk_monitor.o
>> diff --git a/drivers/soc/qcom/sdpm_clk_monitor.c 
>> b/drivers/soc/qcom/sdpm_clk_monitor.c
>> new file mode 100644
>> index 00000000..1aee119
>> --- /dev/null
>> +++ b/drivers/soc/qcom/sdpm_clk_monitor.c
>> @@ -0,0 +1,217 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#define pr_fmt(fmt) "%s " fmt, KBUILD_MODNAME
>> +
>> +#include <linux/clk.h>
>> +#include <linux/err.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/slab.h>
>> +
>> +#define SDPM_DRIVER		"sdpm-clk-monitor"
>> +#define CSR_MAX_VAL		7
>> +#define CSR_OFFSET		0xF00
>> +#define FREQ_HZ_TO_MHZ(f)	DIV_ROUND_UP((f), 1000000)
>> +#define SDPM_CSR_OFFSET(id)	(CSR_OFFSET + (id * 4))
>> +
>> +struct sdpm_clk_instance;
>> +struct sdpm_clk_data {
>> +	struct list_head		sdpm_node;
>> +	struct notifier_block		clk_rate_nb;
>> +	struct clk			*clk;
>> +	const char			*clock_name;
>> +	uint32_t			csr_id;
>> +	struct sdpm_clk_instance	*sdpm_inst;
>> +};
>> +
>> +struct sdpm_clk_instance {
>> +	struct device			*dev;
>> +	void __iomem			*regmap;
>> +	struct list_head		sdpm_instances;
>> +};
>> +
>> +static void sdpm_csr_write(struct sdpm_clk_data *sdpm_data,
>> +				unsigned long clk_rate)
>> +{
>> +	struct sdpm_clk_instance *sdpm_inst = sdpm_data->sdpm_inst;
>> +
>> +	writel_relaxed(clk_rate, sdpm_inst->regmap +
>> +			SDPM_CSR_OFFSET(sdpm_data->csr_id));
>> +	dev_dbg(sdpm_inst->dev, "clock:%s offset:0x%x frequency:%u\n",
>> +			sdpm_data->clock_name,
>> +			SDPM_CSR_OFFSET(sdpm_data->csr_id),
>> +			clk_rate);
>> +}
>> +
>> +static int sdpm_clock_notifier(struct notifier_block *nb,
>> +					unsigned long event, void *data)
>> +{
>> +	struct clk_notifier_data *ndata = data;
>> +	struct sdpm_clk_data *sdpm_data = container_of(nb,
>> +				struct sdpm_clk_data, clk_rate_nb);
>> +
>> +	dev_dbg(sdpm_data->sdpm_inst->dev, "clock:%s event:%lu\n",
>> +			sdpm_data->clock_name, event);
>> +	switch (event) {
>> +	case PRE_RATE_CHANGE:
>> +		if (ndata->new_rate > ndata->old_rate)
>> +			sdpm_csr_write(sdpm_data,
>> +					FREQ_HZ_TO_MHZ(ndata->new_rate));
>> +		return NOTIFY_DONE;
>> +	case POST_RATE_CHANGE:
>> +		if (ndata->new_rate < ndata->old_rate)
>> +			sdpm_csr_write(sdpm_data,
>> +					FREQ_HZ_TO_MHZ(ndata->new_rate));
>> +		return NOTIFY_DONE;
>> +	case ABORT_RATE_CHANGE:
>> +		if (ndata->new_rate > ndata->old_rate)
>> +			sdpm_csr_write(sdpm_data,
>> +					FREQ_HZ_TO_MHZ(ndata->old_rate));
>> +		return NOTIFY_DONE;
>> +	default:
>> +		return NOTIFY_DONE;
>> +	}
>> +}
>> +
>> +static int sdpm_clk_device_remove(struct platform_device *pdev)
>> +{
>> +	struct sdpm_clk_instance *sdpm_inst =
>> +		(struct sdpm_clk_instance *)dev_get_drvdata(&pdev->dev);
>> +	struct sdpm_clk_data *sdpm_data = NULL, *next = NULL;
>> +
>> +	list_for_each_entry_safe(sdpm_data, next,
>> +			&sdpm_inst->sdpm_instances, sdpm_node) {
>> +		clk_notifier_unregister(sdpm_data->clk,
>> +					&sdpm_data->clk_rate_nb);
>> +		list_del(&sdpm_data->sdpm_node);
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>> +static int sdpm_clk_device_probe(struct platform_device *pdev)
>> +{
>> +	struct device *dev = &pdev->dev;
>> +	struct device_node *dev_node = dev->of_node;
>> +	int ret = 0, idx = 0, clk_ct = 0, csr = 0, csr_ct = 0;
>> +	struct sdpm_clk_instance *sdpm_inst = NULL;
>> +	struct sdpm_clk_data *sdpm_data = NULL;
>> +	struct resource *res;
>> +
>> +	sdpm_inst = devm_kzalloc(dev, sizeof(*sdpm_inst), GFP_KERNEL);
>> +	if (!sdpm_inst)
>> +		return -ENOMEM;
>> +	sdpm_inst->dev = dev;
>> +
>> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +	if (!res) {
>> +		dev_err(dev, "Couldn't get MEM resource\n");
>> +		return -EINVAL;
>> +	}
>> +	dev_dbg(dev, "sdpm@0x%x size:%d\n", res->start,
>> +			resource_size(res));
>> +	dev_set_drvdata(dev, sdpm_inst);
>> +
>> +	sdpm_inst->regmap = devm_ioremap_resource(dev, res);
>> +	if (!sdpm_inst->regmap) {
>> +		dev_err(dev, "Couldn't get regmap\n");
>> +		return -EINVAL;
>> +	}
>> +
>> +	ret = of_property_count_strings(dev_node, "clock-names");
>> +	if (ret <= 0) {
>> +		dev_err(dev, "Couldn't get clock names. %d\n", ret);
>> +		return ret;
>> +	}
>> +	clk_ct = ret;
>> +	ret = of_property_count_u32_elems(dev_node, "csr-id");
>> +	if (ret <= 0) {
>> +		dev_err(dev, "Couldn't get csr ID array. %d\n", ret);
>> +		return ret;
>> +	}
>> +	csr_ct = ret;
>> +
>> +	if (csr_ct != clk_ct) {
>> +		dev_err(dev, "Invalid csr:%d and clk:%d count.\n", csr_ct,
>> +				clk_ct);
>> +		return -EINVAL;
>> +	}
>> +
>> +	INIT_LIST_HEAD(&sdpm_inst->sdpm_instances);
>> +
>> +	for (idx = 0; idx < clk_ct; idx++) {
>> +
>> +		sdpm_data = devm_kzalloc(dev, sizeof(*sdpm_data), GFP_KERNEL);
>> +		if (!sdpm_data) {
>> +			ret = -ENOMEM;
>> +			goto clk_err_exit;
>> +		}
>> +
>> +		ret = of_property_read_string_index(dev_node, "clock-names",
>> +				idx, &sdpm_data->clock_name);
>> +		if (ret < 0) {
>> +			dev_err(dev, "Couldn't get clk name index:%d. %d\n",
>> +					idx, ret);
>> +			goto clk_err_exit;
>> +		}
>> +
>> +		sdpm_data->clk = devm_clk_get(dev, sdpm_data->clock_name);
>> +		if (IS_ERR(sdpm_data->clk)) {
>> +			ret = PTR_ERR(sdpm_data->clk);
>> +			goto clk_err_exit;
>> +		}
>> +
>> +		ret = of_property_read_u32_index(dev_node, "csr-id", idx, &csr);
>> +		if (ret < 0) {
>> +			dev_err(dev, "Couldn't get CSR for index:%d. %d\n",
>> +					idx, ret);
>> +			goto clk_err_exit;
>> +		}
>> +
>> +		if (ret > CSR_MAX_VAL) {
>> +			dev_err(dev, "Invalid CSR %d\n", csr);
>> +			ret = -EINVAL;
>> +			goto clk_err_exit;
>> +		}
>> +
>> +		dev_dbg(dev, "SDPM clock:%s csr:%d initialized\n",
>> +				sdpm_data->clock_name, csr);
>> +		sdpm_data->csr_id = csr;
>> +		sdpm_data->sdpm_inst = sdpm_inst;
>> +		sdpm_data->clk_rate_nb.notifier_call = sdpm_clock_notifier;
>> +		sdpm_csr_write(sdpm_data,
>> +			FREQ_HZ_TO_MHZ(clk_get_rate(sdpm_data->clk)));
>> +		clk_notifier_register(sdpm_data->clk, &sdpm_data->clk_rate_nb);
>> +		list_add(&sdpm_data->sdpm_node, &sdpm_inst->sdpm_instances);
>> +	}
>> +
>> +	return 0;
>> +
>> +clk_err_exit:
>> +	sdpm_clk_device_remove(pdev);
>> +
>> +	return ret;
>> +}
>> +
>> +static const struct of_device_id sdpm_clk_device_match[] = {
>> +	{.compatible = "qcom,sdpm"},
>> +	{}
>> +};
>> +
>> +static struct platform_driver sdpm_clk_device_driver = {
>> +	.probe          = sdpm_clk_device_probe,
>> +	.remove         = sdpm_clk_device_remove,
>> +	.driver         = {
>> +		.name   = SDPM_DRIVER,
>> +		.of_match_table = sdpm_clk_device_match,
>> +	},
>> +};
>> +module_platform_driver(sdpm_clk_device_driver);
>> +
>> +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. SDPM Clock Monitor 
>> Driver");
>> +MODULE_LICENSE("GPL v2");
>> 
> Hello!
> 
> Thanks for the patch. A few things to point out:
> 
> Before getting into a big lack of time situation, I have written a
> functional driver for the Qualcomm System Performance Dynamic
> Monitoring (SPDM), which has to yet be cleaned up before sending.
> This driver appears to be "SDPM" instead, but the finalities of this
> new block seem to be very similar - if not the same - as the SPDM.
> 
> My SPDM implementation was done as an interconnect driver, as that is
> actually controlling the bandwidth of the CCI on the SoC.
> 
> 
> Is this block doing the same and/or anything similar?
> In case it does, I suggest to look at my *still a bit dirty* (sorry!)
> driver for the SPDM-TZ.
> 
> Please, look at the last three commits from this branch:
> https://github.com/SoMainline/linux/commits/angelo/v5.12-rc4-feat-spdmtz
> 
> Yours,
> - Angelo

Hi Angelo,

I have gone through above commit and description. I don't see any 
relation with
this SDPM (Simple Digital power meter) clock monitor driver. The SPDM 
(System
Performance Dynamic Monitoring) is trying to control CCI bandwidth.
But this driver monitors different IPs operating clock those are handled
by linux clock framework and informs the same to Qualcomm RDPM hardware.

Thank You,
Manaf