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From: Liu Ying <victor.liu@nxp.com>
To: dri-devel@lists.freedesktop.org
Cc: linux-kernel@vger.kernel.org, a.hajda@samsung.com,
	narmstrong@baylibre.com, robert.foss@linaro.org,
	Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se,
	jernej.skrabec@siol.net, airlied@linux.ie, daniel@ffwll.ch,
	agx@sigxcpu.org, robert.chiras@nxp.com, linux-imx@nxp.com
Subject: [PATCH v3 2/3] drm/bridge: nwl-dsi: Remove a check on unchanged HS clock rate from ->mode_set()
Date: Fri, 23 Apr 2021 17:26:42 +0800	[thread overview]
Message-ID: <1619170003-4817-3-git-send-email-victor.liu@nxp.com> (raw)
In-Reply-To: <1619170003-4817-1-git-send-email-victor.liu@nxp.com>

The check on unchanged HS clock rate in ->mode_set() improves
the callback's performance a bit by early return.  However,
the up-coming patch would get MIPI DSI controller and PHY ready
in ->mode_set() after that check, thus likely skipped.
So, this patch removes that check to make sure MIPI DSI controller
and PHY will be brought up and taken down from ->mode_set() and
->atomic_disable() respectively in pairs.

Cc: Andrzej Hajda <a.hajda@samsung.com>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Robert Foss <robert.foss@linaro.org>
Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Cc: Jonas Karlman <jonas@kwiboo.se>
Cc: Jernej Skrabec <jernej.skrabec@siol.net>
Cc: David Airlie <airlied@linux.ie>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: Guido Günther <agx@sigxcpu.org>
Cc: Robert Chiras <robert.chiras@nxp.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v2->v3:
* Split from the single patch in v2 to clarify changes. (Neil)

 drivers/gpu/drm/bridge/nwl-dsi.c | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-dsi.c
index c65ca860712d2..601ccc4a7cdc7 100644
--- a/drivers/gpu/drm/bridge/nwl-dsi.c
+++ b/drivers/gpu/drm/bridge/nwl-dsi.c
@@ -856,13 +856,6 @@ nwl_dsi_bridge_mode_set(struct drm_bridge *bridge,
 	if (ret < 0)
 		return;
 
-	/*
-	 * If hs clock is unchanged, we're all good - all parameters are
-	 * derived from it atm.
-	 */
-	if (new_cfg.mipi_dphy.hs_clk_rate == dsi->phy_cfg.mipi_dphy.hs_clk_rate)
-		return;
-
 	phy_ref_rate = clk_get_rate(dsi->phy_ref_clk);
 	DRM_DEV_DEBUG_DRIVER(dev, "PHY at ref rate: %lu\n", phy_ref_rate);
 	/* Save the new desired phy config */
-- 
2.25.1


  parent reply	other threads:[~2021-04-23  9:42 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-23  9:26 [PATCH v3 0/3] drm/bridge: nwl-dsi: Get MIPI DSI controller and PHY ready in ->mode_set() Liu Ying
2021-04-23  9:26 ` [PATCH v3 1/3] drm/bridge: nwl-dsi: Force a full modeset when crtc_state->active is changed to be true Liu Ying
2021-04-30  8:35   ` Neil Armstrong
     [not found]   ` <CAG3jFytcPzo81t8hubAf4Gb1zrVzZVB5D6qP-Dnchef6Zus25Q@mail.gmail.com>
2021-04-30 11:45     ` Liu Ying
2021-04-23  9:26 ` Liu Ying [this message]
2021-04-30  8:35   ` [PATCH v3 2/3] drm/bridge: nwl-dsi: Remove a check on unchanged HS clock rate from ->mode_set() Neil Armstrong
2021-04-23  9:26 ` [PATCH v3 3/3] drm/bridge: nwl-dsi: Get MIPI DSI controller and PHY ready in ->mode_set() Liu Ying
2021-04-30  8:35   ` Neil Armstrong
2021-04-30  8:35 ` [PATCH v3 0/3] " Neil Armstrong
2021-04-30  9:17 ` Guido Günther

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