* [PATCH] mtd: rawnand: qcom: avoid write to obsolete register
@ 2021-04-23 19:21 Md Sadre Alam
2021-05-03 14:54 ` mdalam
2021-05-03 16:46 ` Manivannan Sadhasivam
0 siblings, 2 replies; 5+ messages in thread
From: Md Sadre Alam @ 2021-04-23 19:21 UTC (permalink / raw)
To: miquel.raynal, mani, boris.brezillon, linux-mtd, linux-kernel
Cc: mdalam, sricharan
QPIC_EBI2_ECC_BUF_CFG register got obsolete from QPIC V2.0 onwards.
Avoid writing this register if QPIC version is V2.0 or newer.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
---
drivers/mtd/nand/raw/qcom_nandc.c | 17 +++++++++++------
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
index fd4c318..8c5205c 100644
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -714,7 +714,8 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
nandc_set_reg(nandc, NAND_DEV0_CFG0, cfg0);
nandc_set_reg(nandc, NAND_DEV0_CFG1, cfg1);
nandc_set_reg(nandc, NAND_DEV0_ECC_CFG, ecc_bch_cfg);
- nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg);
+ if (!nandc->props->qpic_v2)
+ nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg);
nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus);
nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
@@ -1083,7 +1084,8 @@ static void config_nand_page_read(struct qcom_nand_controller *nandc)
{
write_reg_dma(nandc, NAND_ADDR0, 2, 0);
write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
- write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
+ if (!nandc->props->qpic_v2)
+ write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
@@ -1132,8 +1134,9 @@ static void config_nand_page_write(struct qcom_nand_controller *nandc)
{
write_reg_dma(nandc, NAND_ADDR0, 2, 0);
write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
- write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
- NAND_BAM_NEXT_SGL);
+ if (!nandc->props->qpic_v2)
+ write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
+ NAND_BAM_NEXT_SGL);
}
/*
@@ -1187,7 +1190,8 @@ static int nandc_param(struct qcom_nand_host *host)
| 2 << WR_RD_BSY_GAP
| 0 << WIDE_FLASH
| 1 << DEV0_CFG1_ECC_DISABLE);
- nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, 1 << ECC_CFG_ECC_DISABLE);
+ if (!nandc->props->qpic_v2)
+ nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, 1 << ECC_CFG_ECC_DISABLE);
/* configure CMD1 and VLD for ONFI param probing in QPIC v1 */
if (!nandc->props->qpic_v2) {
@@ -2628,7 +2632,8 @@ static int qcom_nand_attach_chip(struct nand_chip *chip)
| ecc_mode << ECC_MODE
| host->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_BCH;
- host->ecc_buf_cfg = 0x203 << NUM_STEPS;
+ if (!nandc->props->qpic_v2)
+ host->ecc_buf_cfg = 0x203 << NUM_STEPS;
host->clrflashstatus = FS_READY_BSY_N;
host->clrreadstatus = 0xc0;
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] mtd: rawnand: qcom: avoid write to obsolete register
2021-04-23 19:21 [PATCH] mtd: rawnand: qcom: avoid write to obsolete register Md Sadre Alam
@ 2021-05-03 14:54 ` mdalam
2021-05-04 6:58 ` Miquel Raynal
2021-05-03 16:46 ` Manivannan Sadhasivam
1 sibling, 1 reply; 5+ messages in thread
From: mdalam @ 2021-05-03 14:54 UTC (permalink / raw)
To: miquel.raynal, mani, boris.brezillon, linux-mtd, linux-kernel; +Cc: sricharan
On 2021-04-24 00:51, Md Sadre Alam wrote:
> QPIC_EBI2_ECC_BUF_CFG register got obsolete from QPIC V2.0 onwards.
> Avoid writing this register if QPIC version is V2.0 or newer.
>
> Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
> ---
> drivers/mtd/nand/raw/qcom_nandc.c | 17 +++++++++++------
> 1 file changed, 11 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/qcom_nandc.c
> b/drivers/mtd/nand/raw/qcom_nandc.c
> index fd4c318..8c5205c 100644
> --- a/drivers/mtd/nand/raw/qcom_nandc.c
> +++ b/drivers/mtd/nand/raw/qcom_nandc.c
> @@ -714,7 +714,8 @@ static void update_rw_regs(struct qcom_nand_host
> *host, int num_cw, bool read)
> nandc_set_reg(nandc, NAND_DEV0_CFG0, cfg0);
> nandc_set_reg(nandc, NAND_DEV0_CFG1, cfg1);
> nandc_set_reg(nandc, NAND_DEV0_ECC_CFG, ecc_bch_cfg);
> - nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg);
> + if (!nandc->props->qpic_v2)
> + nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg);
> nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus);
> nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
> nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
> @@ -1083,7 +1084,8 @@ static void config_nand_page_read(struct
> qcom_nand_controller *nandc)
> {
> write_reg_dma(nandc, NAND_ADDR0, 2, 0);
> write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
> - write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
> + if (!nandc->props->qpic_v2)
> + write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
> write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
> write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
> NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
> @@ -1132,8 +1134,9 @@ static void config_nand_page_write(struct
> qcom_nand_controller *nandc)
> {
> write_reg_dma(nandc, NAND_ADDR0, 2, 0);
> write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
> - write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
> - NAND_BAM_NEXT_SGL);
> + if (!nandc->props->qpic_v2)
> + write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
> + NAND_BAM_NEXT_SGL);
> }
>
> /*
> @@ -1187,7 +1190,8 @@ static int nandc_param(struct qcom_nand_host
> *host)
> | 2 << WR_RD_BSY_GAP
> | 0 << WIDE_FLASH
> | 1 << DEV0_CFG1_ECC_DISABLE);
> - nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, 1 <<
> ECC_CFG_ECC_DISABLE);
> + if (!nandc->props->qpic_v2)
> + nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, 1 <<
> ECC_CFG_ECC_DISABLE);
>
> /* configure CMD1 and VLD for ONFI param probing in QPIC v1 */
> if (!nandc->props->qpic_v2) {
> @@ -2628,7 +2632,8 @@ static int qcom_nand_attach_chip(struct nand_chip
> *chip)
> | ecc_mode << ECC_MODE
> | host->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_BCH;
>
> - host->ecc_buf_cfg = 0x203 << NUM_STEPS;
> + if (!nandc->props->qpic_v2)
> + host->ecc_buf_cfg = 0x203 << NUM_STEPS;
>
> host->clrflashstatus = FS_READY_BSY_N;
> host->clrreadstatus = 0xc0;
ping! Hi Miquel could you review this change and let me know if more
info needed.
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] mtd: rawnand: qcom: avoid write to obsolete register
2021-04-23 19:21 [PATCH] mtd: rawnand: qcom: avoid write to obsolete register Md Sadre Alam
2021-05-03 14:54 ` mdalam
@ 2021-05-03 16:46 ` Manivannan Sadhasivam
1 sibling, 0 replies; 5+ messages in thread
From: Manivannan Sadhasivam @ 2021-05-03 16:46 UTC (permalink / raw)
To: Md Sadre Alam
Cc: miquel.raynal, boris.brezillon, linux-mtd, linux-kernel, sricharan
On Sat, Apr 24, 2021 at 12:51:34AM +0530, Md Sadre Alam wrote:
> QPIC_EBI2_ECC_BUF_CFG register got obsolete from QPIC V2.0 onwards.
> Avoid writing this register if QPIC version is V2.0 or newer.
>
> Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Thanks,
Mani
> ---
> drivers/mtd/nand/raw/qcom_nandc.c | 17 +++++++++++------
> 1 file changed, 11 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
> index fd4c318..8c5205c 100644
> --- a/drivers/mtd/nand/raw/qcom_nandc.c
> +++ b/drivers/mtd/nand/raw/qcom_nandc.c
> @@ -714,7 +714,8 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
> nandc_set_reg(nandc, NAND_DEV0_CFG0, cfg0);
> nandc_set_reg(nandc, NAND_DEV0_CFG1, cfg1);
> nandc_set_reg(nandc, NAND_DEV0_ECC_CFG, ecc_bch_cfg);
> - nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg);
> + if (!nandc->props->qpic_v2)
> + nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg);
> nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus);
> nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
> nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
> @@ -1083,7 +1084,8 @@ static void config_nand_page_read(struct qcom_nand_controller *nandc)
> {
> write_reg_dma(nandc, NAND_ADDR0, 2, 0);
> write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
> - write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
> + if (!nandc->props->qpic_v2)
> + write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
> write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
> write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
> NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
> @@ -1132,8 +1134,9 @@ static void config_nand_page_write(struct qcom_nand_controller *nandc)
> {
> write_reg_dma(nandc, NAND_ADDR0, 2, 0);
> write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
> - write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
> - NAND_BAM_NEXT_SGL);
> + if (!nandc->props->qpic_v2)
> + write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
> + NAND_BAM_NEXT_SGL);
> }
>
> /*
> @@ -1187,7 +1190,8 @@ static int nandc_param(struct qcom_nand_host *host)
> | 2 << WR_RD_BSY_GAP
> | 0 << WIDE_FLASH
> | 1 << DEV0_CFG1_ECC_DISABLE);
> - nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, 1 << ECC_CFG_ECC_DISABLE);
> + if (!nandc->props->qpic_v2)
> + nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, 1 << ECC_CFG_ECC_DISABLE);
>
> /* configure CMD1 and VLD for ONFI param probing in QPIC v1 */
> if (!nandc->props->qpic_v2) {
> @@ -2628,7 +2632,8 @@ static int qcom_nand_attach_chip(struct nand_chip *chip)
> | ecc_mode << ECC_MODE
> | host->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_BCH;
>
> - host->ecc_buf_cfg = 0x203 << NUM_STEPS;
> + if (!nandc->props->qpic_v2)
> + host->ecc_buf_cfg = 0x203 << NUM_STEPS;
>
> host->clrflashstatus = FS_READY_BSY_N;
> host->clrreadstatus = 0xc0;
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] mtd: rawnand: qcom: avoid write to obsolete register
2021-05-03 14:54 ` mdalam
@ 2021-05-04 6:58 ` Miquel Raynal
2021-05-10 10:58 ` mdalam
0 siblings, 1 reply; 5+ messages in thread
From: Miquel Raynal @ 2021-05-04 6:58 UTC (permalink / raw)
To: mdalam; +Cc: mani, boris.brezillon, linux-mtd, linux-kernel, sricharan
Hello,
mdalam@codeaurora.org wrote on Mon, 03 May 2021 20:24:54 +0530:
> On 2021-04-24 00:51, Md Sadre Alam wrote:
> > QPIC_EBI2_ECC_BUF_CFG register got obsolete from QPIC V2.0 onwards.
> > Avoid writing this register if QPIC version is V2.0 or newer.
> >
> > Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
> > ---
> > drivers/mtd/nand/raw/qcom_nandc.c | 17 +++++++++++------
> > 1 file changed, 11 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/mtd/nand/raw/qcom_nandc.c
> > b/drivers/mtd/nand/raw/qcom_nandc.c
> > index fd4c318..8c5205c 100644
> > --- a/drivers/mtd/nand/raw/qcom_nandc.c
> > +++ b/drivers/mtd/nand/raw/qcom_nandc.c
> > @@ -714,7 +714,8 @@ static void update_rw_regs(struct qcom_nand_host
> > *host, int num_cw, bool read)
> > nandc_set_reg(nandc, NAND_DEV0_CFG0, cfg0);
> > nandc_set_reg(nandc, NAND_DEV0_CFG1, cfg1);
> > nandc_set_reg(nandc, NAND_DEV0_ECC_CFG, ecc_bch_cfg);
> > - nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg);
> > + if (!nandc->props->qpic_v2)
> > + nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg);
> > nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus);
> > nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
> > nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
> > @@ -1083,7 +1084,8 @@ static void config_nand_page_read(struct
> > qcom_nand_controller *nandc)
> > {
> > write_reg_dma(nandc, NAND_ADDR0, 2, 0);
> > write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
> > - write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
> > + if (!nandc->props->qpic_v2)
> > + write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
> > write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
> > write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
> > NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
> > @@ -1132,8 +1134,9 @@ static void config_nand_page_write(struct
> > qcom_nand_controller *nandc)
> > {
> > write_reg_dma(nandc, NAND_ADDR0, 2, 0);
> > write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
> > - write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
> > - NAND_BAM_NEXT_SGL);
> > + if (!nandc->props->qpic_v2)
> > + write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
> > + NAND_BAM_NEXT_SGL);
> > }
> >
> > /*
> > @@ -1187,7 +1190,8 @@ static int nandc_param(struct qcom_nand_host > *host)
> > | 2 << WR_RD_BSY_GAP
> > | 0 << WIDE_FLASH
> > | 1 << DEV0_CFG1_ECC_DISABLE);
> > - nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, 1 << > ECC_CFG_ECC_DISABLE);
> > + if (!nandc->props->qpic_v2)
> > + nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, 1 << > ECC_CFG_ECC_DISABLE);
> >
> > /* configure CMD1 and VLD for ONFI param probing in QPIC v1 */
> > if (!nandc->props->qpic_v2) {
> > @@ -2628,7 +2632,8 @@ static int qcom_nand_attach_chip(struct nand_chip > *chip)
> > | ecc_mode << ECC_MODE
> > | host->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_BCH;
> >
> > - host->ecc_buf_cfg = 0x203 << NUM_STEPS;
> > + if (!nandc->props->qpic_v2)
> > + host->ecc_buf_cfg = 0x203 << NUM_STEPS;
> >
> > host->clrflashstatus = FS_READY_BSY_N;
> > host->clrreadstatus = 0xc0;
>
>
> ping! Hi Miquel could you review this change and let me know if more info needed.
Come on, that's only 6 days of work and we are in the middle of the
merge window...
BTW "avoid write to" in the title is incorrect "writing to" would be
nicer.
Thanks,
Miquèl
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] mtd: rawnand: qcom: avoid write to obsolete register
2021-05-04 6:58 ` Miquel Raynal
@ 2021-05-10 10:58 ` mdalam
0 siblings, 0 replies; 5+ messages in thread
From: mdalam @ 2021-05-10 10:58 UTC (permalink / raw)
To: Miquel Raynal; +Cc: mani, boris.brezillon, linux-mtd, linux-kernel, sricharan
On 2021-05-04 12:28, Miquel Raynal wrote:
> Hello,
>
> mdalam@codeaurora.org wrote on Mon, 03 May 2021 20:24:54 +0530:
>
>> On 2021-04-24 00:51, Md Sadre Alam wrote:
>> > QPIC_EBI2_ECC_BUF_CFG register got obsolete from QPIC V2.0 onwards.
>> > Avoid writing this register if QPIC version is V2.0 or newer.
>> >
>> > Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
>> > ---
>> > drivers/mtd/nand/raw/qcom_nandc.c | 17 +++++++++++------
>> > 1 file changed, 11 insertions(+), 6 deletions(-)
>> >
>> > diff --git a/drivers/mtd/nand/raw/qcom_nandc.c
>> > b/drivers/mtd/nand/raw/qcom_nandc.c
>> > index fd4c318..8c5205c 100644
>> > --- a/drivers/mtd/nand/raw/qcom_nandc.c
>> > +++ b/drivers/mtd/nand/raw/qcom_nandc.c
>> > @@ -714,7 +714,8 @@ static void update_rw_regs(struct qcom_nand_host
>> > *host, int num_cw, bool read)
>> > nandc_set_reg(nandc, NAND_DEV0_CFG0, cfg0);
>> > nandc_set_reg(nandc, NAND_DEV0_CFG1, cfg1);
>> > nandc_set_reg(nandc, NAND_DEV0_ECC_CFG, ecc_bch_cfg);
>> > - nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg);
>> > + if (!nandc->props->qpic_v2)
>> > + nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg);
>> > nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus);
>> > nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
>> > nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
>> > @@ -1083,7 +1084,8 @@ static void config_nand_page_read(struct
>> > qcom_nand_controller *nandc)
>> > {
>> > write_reg_dma(nandc, NAND_ADDR0, 2, 0);
>> > write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
>> > - write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
>> > + if (!nandc->props->qpic_v2)
>> > + write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
>> > write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
>> > write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
>> > NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
>> > @@ -1132,8 +1134,9 @@ static void config_nand_page_write(struct
>> > qcom_nand_controller *nandc)
>> > {
>> > write_reg_dma(nandc, NAND_ADDR0, 2, 0);
>> > write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
>> > - write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
>> > - NAND_BAM_NEXT_SGL);
>> > + if (!nandc->props->qpic_v2)
>> > + write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
>> > + NAND_BAM_NEXT_SGL);
>> > }
>> >
>> > /*
>> > @@ -1187,7 +1190,8 @@ static int nandc_param(struct qcom_nand_host > *host)
>> > | 2 << WR_RD_BSY_GAP
>> > | 0 << WIDE_FLASH
>> > | 1 << DEV0_CFG1_ECC_DISABLE);
>> > - nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, 1 << > ECC_CFG_ECC_DISABLE);
>> > + if (!nandc->props->qpic_v2)
>> > + nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, 1 << > ECC_CFG_ECC_DISABLE);
>> >
>> > /* configure CMD1 and VLD for ONFI param probing in QPIC v1 */
>> > if (!nandc->props->qpic_v2) {
>> > @@ -2628,7 +2632,8 @@ static int qcom_nand_attach_chip(struct nand_chip > *chip)
>> > | ecc_mode << ECC_MODE
>> > | host->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_BCH;
>> >
>> > - host->ecc_buf_cfg = 0x203 << NUM_STEPS;
>> > + if (!nandc->props->qpic_v2)
>> > + host->ecc_buf_cfg = 0x203 << NUM_STEPS;
>> >
>> > host->clrflashstatus = FS_READY_BSY_N;
>> > host->clrreadstatus = 0xc0;
>>
>>
>> ping! Hi Miquel could you review this change and let me know if more
>> info needed.
>
> Come on, that's only 6 days of work and we are in the middle of the
> merge window...
>
> BTW "avoid write to" in the title is incorrect "writing to" would be
> nicer.
Updated commit message in V2 patch.
>
> Thanks,
> Miquèl
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2021-05-10 11:48 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2021-04-23 19:21 [PATCH] mtd: rawnand: qcom: avoid write to obsolete register Md Sadre Alam
2021-05-03 14:54 ` mdalam
2021-05-04 6:58 ` Miquel Raynal
2021-05-10 10:58 ` mdalam
2021-05-03 16:46 ` Manivannan Sadhasivam
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