* [PATCH v3 0/4] Misc Ingenic patches.
@ 2021-06-24 15:06 周琰杰 (Zhou Yanjie)
2021-06-24 15:06 ` [PATCH v3 1/4] MIPS: X1830: Respect cell count of common properties 周琰杰 (Zhou Yanjie)
` (3 more replies)
0 siblings, 4 replies; 11+ messages in thread
From: 周琰杰 (Zhou Yanjie) @ 2021-06-24 15:06 UTC (permalink / raw)
To: tsbogend, mturquette, sboyd, paul, robh+dt
Cc: linux-mips, devicetree, linux-clk, linux-kernel, dongsheng.qiu,
aric.pzqi, rick.tyliu, sihui.liu, jun.jiang, sernia.zhou
Some misc patches that don't really have any relation
between themselves.
周琰杰 (Zhou Yanjie) (4):
MIPS: X1830: Respect cell count of common properties.
dt-bindings: clock: Add documentation for MAC PHY control bindings.
MIPS: Ingenic: Add MAC syscon nodes for Ingenic SoCs.
MIPS: CI20: Add second percpu timer for SMP.
.../devicetree/bindings/clock/ingenic,cgu.yaml | 2 ++
arch/mips/boot/dts/ingenic/ci20.dts | 21 +++++++++++----------
arch/mips/boot/dts/ingenic/x1000.dtsi | 7 +++++++
arch/mips/boot/dts/ingenic/x1830.dtsi | 16 +++++++++++-----
4 files changed, 31 insertions(+), 15 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH v3 1/4] MIPS: X1830: Respect cell count of common properties. 2021-06-24 15:06 [PATCH v3 0/4] Misc Ingenic patches 周琰杰 (Zhou Yanjie) @ 2021-06-24 15:06 ` 周琰杰 (Zhou Yanjie) 2021-06-24 15:06 ` [PATCH v3 2/4] dt-bindings: clock: Add documentation for MAC PHY control bindings 周琰杰 (Zhou Yanjie) ` (2 subsequent siblings) 3 siblings, 0 replies; 11+ messages in thread From: 周琰杰 (Zhou Yanjie) @ 2021-06-24 15:06 UTC (permalink / raw) To: tsbogend, mturquette, sboyd, paul, robh+dt Cc: linux-mips, devicetree, linux-clk, linux-kernel, dongsheng.qiu, aric.pzqi, rick.tyliu, sihui.liu, jun.jiang, sernia.zhou If N fields of X cells should be provided, then that's what the devicetree should represent, instead of having one single field of (N * X) cells. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Acked-by: Paul Cercueil <paul@crapouillou.net> --- Notes: v1->v2: No change. v2->v3: No change. arch/mips/boot/dts/ingenic/x1830.dtsi | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi b/arch/mips/boot/dts/ingenic/x1830.dtsi index b21c930..59ca3a8 100644 --- a/arch/mips/boot/dts/ingenic/x1830.dtsi +++ b/arch/mips/boot/dts/ingenic/x1830.dtsi @@ -97,9 +97,9 @@ #clock-cells = <1>; - clocks = <&cgu X1830_CLK_RTCLK - &cgu X1830_CLK_EXCLK - &cgu X1830_CLK_PCLK>; + clocks = <&cgu X1830_CLK_RTCLK>, + <&cgu X1830_CLK_EXCLK>, + <&cgu X1830_CLK_PCLK>; clock-names = "rtc", "ext", "pclk"; interrupt-controller; @@ -274,8 +274,7 @@ pdma: dma-controller@13420000 { compatible = "ingenic,x1830-dma"; - reg = <0x13420000 0x400 - 0x13421000 0x40>; + reg = <0x13420000 0x400>, <0x13421000 0x40>; #dma-cells = <2>; interrupt-parent = <&intc>; -- 2.7.4 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v3 2/4] dt-bindings: clock: Add documentation for MAC PHY control bindings. 2021-06-24 15:06 [PATCH v3 0/4] Misc Ingenic patches 周琰杰 (Zhou Yanjie) 2021-06-24 15:06 ` [PATCH v3 1/4] MIPS: X1830: Respect cell count of common properties 周琰杰 (Zhou Yanjie) @ 2021-06-24 15:06 ` 周琰杰 (Zhou Yanjie) 2021-06-25 11:18 ` Paul Cercueil 2021-06-24 15:06 ` [PATCH v3 3/4] MIPS: Ingenic: Add MAC syscon nodes for Ingenic SoCs 周琰杰 (Zhou Yanjie) 2021-06-24 15:06 ` [PATCH v3 4/4] MIPS: CI20: Add second percpu timer for SMP 周琰杰 (Zhou Yanjie) 3 siblings, 1 reply; 11+ messages in thread From: 周琰杰 (Zhou Yanjie) @ 2021-06-24 15:06 UTC (permalink / raw) To: tsbogend, mturquette, sboyd, paul, robh+dt Cc: linux-mips, devicetree, linux-clk, linux-kernel, dongsheng.qiu, aric.pzqi, rick.tyliu, sihui.liu, jun.jiang, sernia.zhou Update the CGU binding documentation, add mac-phy-ctrl as a pattern property. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> --- Notes: v3: New patch. Documentation/devicetree/bindings/clock/ingenic,cgu.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml index c65b945..ee9b5fb 100644 --- a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml +++ b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml @@ -93,6 +93,8 @@ required: patternProperties: "^usb-phy@[a-f0-9]+$": allOf: [ $ref: "../phy/ingenic,phy-usb.yaml#" ] + "^mac-phy-ctrl@[a-f0-9]+$": + allOf: [ $ref: "../net/ingenic,mac.yaml#" ] additionalProperties: false -- 2.7.4 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v3 2/4] dt-bindings: clock: Add documentation for MAC PHY control bindings. 2021-06-24 15:06 ` [PATCH v3 2/4] dt-bindings: clock: Add documentation for MAC PHY control bindings 周琰杰 (Zhou Yanjie) @ 2021-06-25 11:18 ` Paul Cercueil 0 siblings, 0 replies; 11+ messages in thread From: Paul Cercueil @ 2021-06-25 11:18 UTC (permalink / raw) To: 周琰杰 Cc: tsbogend, mturquette, sboyd, robh+dt, linux-mips, devicetree, linux-clk, linux-kernel, dongsheng.qiu, aric.pzqi, rick.tyliu, sihui.liu, jun.jiang, sernia.zhou Hi Zhou, Le jeu., juin 24 2021 at 23:06:27 +0800, 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> a écrit : > Update the CGU binding documentation, add mac-phy-ctrl as a > pattern property. > > Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Acked-by: Paul Cercueil <paul@crapouillou.net> Cheers, -Paul > --- > > Notes: > v3: > New patch. > > Documentation/devicetree/bindings/clock/ingenic,cgu.yaml | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml > b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml > index c65b945..ee9b5fb 100644 > --- a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml > +++ b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml > @@ -93,6 +93,8 @@ required: > patternProperties: > "^usb-phy@[a-f0-9]+$": > allOf: [ $ref: "../phy/ingenic,phy-usb.yaml#" ] > + "^mac-phy-ctrl@[a-f0-9]+$": > + allOf: [ $ref: "../net/ingenic,mac.yaml#" ] > > additionalProperties: false > > -- > 2.7.4 > ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v3 3/4] MIPS: Ingenic: Add MAC syscon nodes for Ingenic SoCs. 2021-06-24 15:06 [PATCH v3 0/4] Misc Ingenic patches 周琰杰 (Zhou Yanjie) 2021-06-24 15:06 ` [PATCH v3 1/4] MIPS: X1830: Respect cell count of common properties 周琰杰 (Zhou Yanjie) 2021-06-24 15:06 ` [PATCH v3 2/4] dt-bindings: clock: Add documentation for MAC PHY control bindings 周琰杰 (Zhou Yanjie) @ 2021-06-24 15:06 ` 周琰杰 (Zhou Yanjie) 2021-06-24 15:06 ` [PATCH v3 4/4] MIPS: CI20: Add second percpu timer for SMP 周琰杰 (Zhou Yanjie) 3 siblings, 0 replies; 11+ messages in thread From: 周琰杰 (Zhou Yanjie) @ 2021-06-24 15:06 UTC (permalink / raw) To: tsbogend, mturquette, sboyd, paul, robh+dt Cc: linux-mips, devicetree, linux-clk, linux-kernel, dongsheng.qiu, aric.pzqi, rick.tyliu, sihui.liu, jun.jiang, sernia.zhou Add MAC syscon nodes for X1000 SoC and X1830 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Acked-by: Paul Cercueil <paul@crapouillou.net> --- Notes: v1->v2: No change. v2->v3: No change. arch/mips/boot/dts/ingenic/x1000.dtsi | 7 +++++++ arch/mips/boot/dts/ingenic/x1830.dtsi | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi b/arch/mips/boot/dts/ingenic/x1000.dtsi index aac9ded..dec7909 100644 --- a/arch/mips/boot/dts/ingenic/x1000.dtsi +++ b/arch/mips/boot/dts/ingenic/x1000.dtsi @@ -80,6 +80,11 @@ status = "disabled"; }; + + mac_phy_ctrl: mac-phy-ctrl@e8 { + compatible = "syscon"; + reg = <0xe8 0x4>; + }; }; ost: timer@12000000 { @@ -347,6 +352,8 @@ clocks = <&cgu X1000_CLK_MAC>; clock-names = "stmmaceth"; + mode-reg = <&mac_phy_ctrl>; + status = "disabled"; mdio: mdio { diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi b/arch/mips/boot/dts/ingenic/x1830.dtsi index 59ca3a8..215257f 100644 --- a/arch/mips/boot/dts/ingenic/x1830.dtsi +++ b/arch/mips/boot/dts/ingenic/x1830.dtsi @@ -73,6 +73,11 @@ status = "disabled"; }; + + mac_phy_ctrl: mac-phy-ctrl@e8 { + compatible = "syscon"; + reg = <0xe8 0x4>; + }; }; ost: timer@12000000 { @@ -336,6 +341,8 @@ clocks = <&cgu X1830_CLK_MAC>; clock-names = "stmmaceth"; + mode-reg = <&mac_phy_ctrl>; + status = "disabled"; mdio: mdio { -- 2.7.4 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v3 4/4] MIPS: CI20: Add second percpu timer for SMP. 2021-06-24 15:06 [PATCH v3 0/4] Misc Ingenic patches 周琰杰 (Zhou Yanjie) ` (2 preceding siblings ...) 2021-06-24 15:06 ` [PATCH v3 3/4] MIPS: Ingenic: Add MAC syscon nodes for Ingenic SoCs 周琰杰 (Zhou Yanjie) @ 2021-06-24 15:06 ` 周琰杰 (Zhou Yanjie) 2021-06-25 11:31 ` Paul Cercueil 3 siblings, 1 reply; 11+ messages in thread From: 周琰杰 (Zhou Yanjie) @ 2021-06-24 15:06 UTC (permalink / raw) To: tsbogend, mturquette, sboyd, paul, robh+dt Cc: linux-mips, devicetree, linux-clk, linux-kernel, dongsheng.qiu, aric.pzqi, rick.tyliu, sihui.liu, jun.jiang, sernia.zhou 1.Add a new TCU channel as the percpu timer of core1, this is to prepare for the subsequent SMP support. The newly added channel will not adversely affect the current single-core state. 2.Adjust the position of TCU node to make it consistent with the order in jz4780.dtsi file. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> --- Notes: v2: New patch. v2->v3: No change. arch/mips/boot/dts/ingenic/ci20.dts | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts index 8877c62..70005cc 100644 --- a/arch/mips/boot/dts/ingenic/ci20.dts +++ b/arch/mips/boot/dts/ingenic/ci20.dts @@ -118,6 +118,17 @@ assigned-clock-rates = <48000000>; }; +&tcu { + /* + * 750 kHz for the system timers and 3 MHz for the clocksources, + * use channel #0 and #1 for the per cpu system timers, and use + * channel #2 for the clocksource. + */ + assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, + <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_OST>; + assigned-clock-rates = <750000>, <750000>, <3000000>, <3000000>; +}; + &mmc0 { status = "okay"; @@ -522,13 +533,3 @@ bias-disable; }; }; - -&tcu { - /* - * 750 kHz for the system timer and 3 MHz for the clocksource, - * use channel #0 for the system timer, #1 for the clocksource. - */ - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, - <&tcu TCU_CLK_OST>; - assigned-clock-rates = <750000>, <3000000>, <3000000>; -}; -- 2.7.4 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v3 4/4] MIPS: CI20: Add second percpu timer for SMP. 2021-06-24 15:06 ` [PATCH v3 4/4] MIPS: CI20: Add second percpu timer for SMP 周琰杰 (Zhou Yanjie) @ 2021-06-25 11:31 ` Paul Cercueil 2021-06-25 12:14 ` 周琰杰 2021-06-25 15:19 ` 周琰杰 0 siblings, 2 replies; 11+ messages in thread From: Paul Cercueil @ 2021-06-25 11:31 UTC (permalink / raw) To: 周琰杰 Cc: tsbogend, mturquette, sboyd, robh+dt, linux-mips, devicetree, linux-clk, linux-kernel, dongsheng.qiu, aric.pzqi, rick.tyliu, sihui.liu, jun.jiang, sernia.zhou Hi Zhou, Le jeu., juin 24 2021 at 23:06:29 +0800, 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> a écrit : > 1.Add a new TCU channel as the percpu timer of core1, this is to > prepare for the subsequent SMP support. The newly added channel > will not adversely affect the current single-core state. > 2.Adjust the position of TCU node to make it consistent with the > order in jz4780.dtsi file. That's a bit superfluous, the order matters when adding new nodes, but once they are added, moving them around only cause annoyance. > > Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> > --- > > Notes: > v2: > New patch. > > v2->v3: > No change. > > arch/mips/boot/dts/ingenic/ci20.dts | 21 +++++++++++---------- > 1 file changed, 11 insertions(+), 10 deletions(-) > > diff --git a/arch/mips/boot/dts/ingenic/ci20.dts > b/arch/mips/boot/dts/ingenic/ci20.dts > index 8877c62..70005cc 100644 > --- a/arch/mips/boot/dts/ingenic/ci20.dts > +++ b/arch/mips/boot/dts/ingenic/ci20.dts > @@ -118,6 +118,17 @@ > assigned-clock-rates = <48000000>; > }; > > +&tcu { > + /* > + * 750 kHz for the system timers and 3 MHz for the clocksources, > + * use channel #0 and #1 for the per cpu system timers, and use > + * channel #2 for the clocksource. > + */ > + assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, > + <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_OST>; > + assigned-clock-rates = <750000>, <750000>, <3000000>, <3000000>; Ideally you'd set TIMER1 to 3 MHz and TIMER2 to 750 kHz, otherwise it kind of breaks support for older kernels (they would still boot, but with a very slow clocksource). So in the new DTS you could use the timer0 clock for CPU #0, timer1 for the clocksource, and timer2+ for cpus > 0. Cheers, -Paul > +}; > + > &mmc0 { > status = "okay"; > > @@ -522,13 +533,3 @@ > bias-disable; > }; > }; > - > -&tcu { > - /* > - * 750 kHz for the system timer and 3 MHz for the clocksource, > - * use channel #0 for the system timer, #1 for the clocksource. > - */ > - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, > - <&tcu TCU_CLK_OST>; > - assigned-clock-rates = <750000>, <3000000>, <3000000>; > -}; > -- > 2.7.4 > ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 4/4] MIPS: CI20: Add second percpu timer for SMP. 2021-06-25 11:31 ` Paul Cercueil @ 2021-06-25 12:14 ` 周琰杰 2021-06-25 15:19 ` 周琰杰 1 sibling, 0 replies; 11+ messages in thread From: 周琰杰 @ 2021-06-25 12:14 UTC (permalink / raw) To: Paul Cercueil Cc: tsbogend, mturquette, sboyd, robh+dt, linux-mips, devicetree, linux-clk, linux-kernel, dongsheng.qiu, aric.pzqi, rick.tyliu, sihui.liu, jun.jiang, sernia.zhou 于 Fri, 25 Jun 2021 12:31:17 +0100 Paul Cercueil <paul@crapouillou.net> 写道: > Hi Zhou, > > Le jeu., juin 24 2021 at 23:06:29 +0800, 周琰杰 (Zhou Yanjie) > <zhouyanjie@wanyeetech.com> a écrit : > > 1.Add a new TCU channel as the percpu timer of core1, this is to > > prepare for the subsequent SMP support. The newly added channel > > will not adversely affect the current single-core state. > > 2.Adjust the position of TCU node to make it consistent with the > > order in jz4780.dtsi file. > > That's a bit superfluous, the order matters when adding new nodes, > but once they are added, moving them around only cause annoyance. > > > > > Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> > > --- > > > > Notes: > > v2: > > New patch. > > > > v2->v3: > > No change. > > > > arch/mips/boot/dts/ingenic/ci20.dts | 21 +++++++++++---------- > > 1 file changed, 11 insertions(+), 10 deletions(-) > > > > diff --git a/arch/mips/boot/dts/ingenic/ci20.dts > > b/arch/mips/boot/dts/ingenic/ci20.dts > > index 8877c62..70005cc 100644 > > --- a/arch/mips/boot/dts/ingenic/ci20.dts > > +++ b/arch/mips/boot/dts/ingenic/ci20.dts > > @@ -118,6 +118,17 @@ > > assigned-clock-rates = <48000000>; > > }; > > > > +&tcu { > > + /* > > + * 750 kHz for the system timers and 3 MHz for the > > clocksources, > > + * use channel #0 and #1 for the per cpu system timers, > > and use > > + * channel #2 for the clocksource. > > + */ > > + assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu > > TCU_CLK_TIMER1>, > > + <&tcu TCU_CLK_TIMER2>, > > <&tcu TCU_CLK_OST>; > > + assigned-clock-rates = <750000>, <750000>, <3000000>, > > <3000000>; > > Ideally you'd set TIMER1 to 3 MHz and TIMER2 to 750 kHz, otherwise it > kind of breaks support for older kernels (they would still boot, but > with a very slow clocksource). So in the new DTS you could use the > timer0 clock for CPU #0, timer1 for the clocksource, and timer2+ for > cpus > 0. Sure, I will change it in v4. Thanks and best regards! > > Cheers, > -Paul > > > +}; > > + > > &mmc0 { > > status = "okay"; > > > > @@ -522,13 +533,3 @@ > > bias-disable; > > }; > > }; > > - > > -&tcu { > > - /* > > - * 750 kHz for the system timer and 3 MHz for the > > clocksource, > > - * use channel #0 for the system timer, #1 for the > > clocksource. > > - */ > > - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu > > TCU_CLK_TIMER1>, > > - <&tcu TCU_CLK_OST>; > > - assigned-clock-rates = <750000>, <3000000>, <3000000>; > > -}; > > -- > > 2.7.4 > > > ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 4/4] MIPS: CI20: Add second percpu timer for SMP. 2021-06-25 11:31 ` Paul Cercueil 2021-06-25 12:14 ` 周琰杰 @ 2021-06-25 15:19 ` 周琰杰 2021-06-25 15:47 ` Paul Cercueil 1 sibling, 1 reply; 11+ messages in thread From: 周琰杰 @ 2021-06-25 15:19 UTC (permalink / raw) To: Paul Cercueil Cc: tsbogend, mturquette, sboyd, robh+dt, linux-mips, devicetree, linux-clk, linux-kernel, dongsheng.qiu, aric.pzqi, rick.tyliu, sihui.liu, jun.jiang, sernia.zhou Hi Paul, 于 Fri, 25 Jun 2021 12:31:17 +0100 Paul Cercueil <paul@crapouillou.net> 写道: > Hi Zhou, > > Le jeu., juin 24 2021 at 23:06:29 +0800, 周琰杰 (Zhou Yanjie) > <zhouyanjie@wanyeetech.com> a écrit : > > 1.Add a new TCU channel as the percpu timer of core1, this is to > > prepare for the subsequent SMP support. The newly added channel > > will not adversely affect the current single-core state. > > 2.Adjust the position of TCU node to make it consistent with the > > order in jz4780.dtsi file. > > That's a bit superfluous, the order matters when adding new nodes, > but once they are added, moving them around only cause annoyance. > > > > > Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> > > --- > > > > Notes: > > v2: > > New patch. > > > > v2->v3: > > No change. > > > > arch/mips/boot/dts/ingenic/ci20.dts | 21 +++++++++++---------- > > 1 file changed, 11 insertions(+), 10 deletions(-) > > > > diff --git a/arch/mips/boot/dts/ingenic/ci20.dts > > b/arch/mips/boot/dts/ingenic/ci20.dts > > index 8877c62..70005cc 100644 > > --- a/arch/mips/boot/dts/ingenic/ci20.dts > > +++ b/arch/mips/boot/dts/ingenic/ci20.dts > > @@ -118,6 +118,17 @@ > > assigned-clock-rates = <48000000>; > > }; > > > > +&tcu { > > + /* > > + * 750 kHz for the system timers and 3 MHz for the > > clocksources, > > + * use channel #0 and #1 for the per cpu system timers, > > and use > > + * channel #2 for the clocksource. > > + */ > > + assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu > > TCU_CLK_TIMER1>, > > + <&tcu TCU_CLK_TIMER2>, > > <&tcu TCU_CLK_OST>; > > + assigned-clock-rates = <750000>, <750000>, <3000000>, > > <3000000>; > > Ideally you'd set TIMER1 to 3 MHz and TIMER2 to 750 kHz, otherwise it > kind of breaks support for older kernels (they would still boot, but > with a very slow clocksource). So in the new DTS you could use the > timer0 clock for CPU #0, timer1 for the clocksource, and timer2+ for > cpus > 0. I checked the ingenic-timer driver, and it seems that the last TCU channel is always used as the clocksource in the driver, so it seems that we can only use timer2 as the clocksource in smp mode. Maybe we should add a note for smp is closed in the comment. And I found that I missed a problem, Nikolaus Schaller once reported that because the frequency of the tcu timer (only 16bit) used to provide the clocksource is too high, there will be a chance that the system will get stuck before the clocksource is switched to ost. And reducing the clocksource to 750kz can prevent it from happening. I will add this part to v4. When this part is added, both clockevent and clocksource will be 750kHz, but the 750kHz clocksource is only temporary, because it will then switch to the clocksource provided by ost, and ost works at 3MHz. Thanks and best regards! > > Cheers, > -Paul > > > +}; > > + > > &mmc0 { > > status = "okay"; > > > > @@ -522,13 +533,3 @@ > > bias-disable; > > }; > > }; > > - > > -&tcu { > > - /* > > - * 750 kHz for the system timer and 3 MHz for the > > clocksource, > > - * use channel #0 for the system timer, #1 for the > > clocksource. > > - */ > > - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu > > TCU_CLK_TIMER1>, > > - <&tcu TCU_CLK_OST>; > > - assigned-clock-rates = <750000>, <3000000>, <3000000>; > > -}; > > -- > > 2.7.4 > > > ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 4/4] MIPS: CI20: Add second percpu timer for SMP. 2021-06-25 15:19 ` 周琰杰 @ 2021-06-25 15:47 ` Paul Cercueil 2021-06-25 16:32 ` 周琰杰 0 siblings, 1 reply; 11+ messages in thread From: Paul Cercueil @ 2021-06-25 15:47 UTC (permalink / raw) To: 周琰杰 Cc: tsbogend, mturquette, sboyd, robh+dt, linux-mips, devicetree, linux-clk, linux-kernel, dongsheng.qiu, aric.pzqi, rick.tyliu, sihui.liu, jun.jiang, sernia.zhou Hi Zhou, Le ven., juin 25 2021 at 23:19:42 +0800, 周琰杰 <zhouyanjie@wanyeetech.com> a écrit : > Hi Paul, > > 于 Fri, 25 Jun 2021 12:31:17 +0100 > Paul Cercueil <paul@crapouillou.net> 写道: > >> Hi Zhou, >> >> Le jeu., juin 24 2021 at 23:06:29 +0800, 周琰杰 (Zhou Yanjie) >> <zhouyanjie@wanyeetech.com> a écrit : >> > 1.Add a new TCU channel as the percpu timer of core1, this is to >> > prepare for the subsequent SMP support. The newly added channel >> > will not adversely affect the current single-core state. >> > 2.Adjust the position of TCU node to make it consistent with the >> > order in jz4780.dtsi file. >> >> That's a bit superfluous, the order matters when adding new nodes, >> but once they are added, moving them around only cause annoyance. >> >> > >> > Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> >> > --- >> > >> > Notes: >> > v2: >> > New patch. >> > >> > v2->v3: >> > No change. >> > >> > arch/mips/boot/dts/ingenic/ci20.dts | 21 +++++++++++---------- >> > 1 file changed, 11 insertions(+), 10 deletions(-) >> > >> > diff --git a/arch/mips/boot/dts/ingenic/ci20.dts >> > b/arch/mips/boot/dts/ingenic/ci20.dts >> > index 8877c62..70005cc 100644 >> > --- a/arch/mips/boot/dts/ingenic/ci20.dts >> > +++ b/arch/mips/boot/dts/ingenic/ci20.dts >> > @@ -118,6 +118,17 @@ >> > assigned-clock-rates = <48000000>; >> > }; >> > >> > +&tcu { >> > + /* >> > + * 750 kHz for the system timers and 3 MHz for the >> > clocksources, >> > + * use channel #0 and #1 for the per cpu system timers, >> > and use >> > + * channel #2 for the clocksource. >> > + */ >> > + assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu >> > TCU_CLK_TIMER1>, >> > + <&tcu TCU_CLK_TIMER2>, >> > <&tcu TCU_CLK_OST>; >> > + assigned-clock-rates = <750000>, <750000>, <3000000>, >> > <3000000>; >> >> Ideally you'd set TIMER1 to 3 MHz and TIMER2 to 750 kHz, otherwise >> it >> kind of breaks support for older kernels (they would still boot, but >> with a very slow clocksource). So in the new DTS you could use the >> timer0 clock for CPU #0, timer1 for the clocksource, and timer2+ for >> cpus > 0. > > I checked the ingenic-timer driver, and it seems that the last TCU > channel is always used as the clocksource in the driver, so it seems > that we can only use timer2 as the clocksource in smp mode. Maybe we > should add a note for smp is closed in the comment. And I found that I > missed a problem, Nikolaus Schaller once reported that because the > frequency of the tcu timer (only 16bit) used to provide the > clocksource > is too high, there will be a chance that the system will get stuck > before the clocksource is switched to ost. And reducing the > clocksource > to 750kz can prevent it from happening. I will add this part to v4. > When this part is added, both clockevent and clocksource will be > 750kHz, but the 750kHz clocksource is only temporary, because it will > then switch to the clocksource provided by ost, and ost works at 3MHz. Ok, then first change the clocksource to 750 kHz, then update it with timer2. Cheers, -Paul > > Thanks and best regards! > >> >> Cheers, >> -Paul >> >> > +}; >> > + >> > &mmc0 { >> > status = "okay"; >> > >> > @@ -522,13 +533,3 @@ >> > bias-disable; >> > }; >> > }; >> > - >> > -&tcu { >> > - /* >> > - * 750 kHz for the system timer and 3 MHz for the >> > clocksource, >> > - * use channel #0 for the system timer, #1 for the >> > clocksource. >> > - */ >> > - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu >> > TCU_CLK_TIMER1>, >> > - <&tcu TCU_CLK_OST>; >> > - assigned-clock-rates = <750000>, <3000000>, <3000000>; >> > -}; >> > -- >> > 2.7.4 >> > >> > ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 4/4] MIPS: CI20: Add second percpu timer for SMP. 2021-06-25 15:47 ` Paul Cercueil @ 2021-06-25 16:32 ` 周琰杰 0 siblings, 0 replies; 11+ messages in thread From: 周琰杰 @ 2021-06-25 16:32 UTC (permalink / raw) To: Paul Cercueil Cc: tsbogend, mturquette, sboyd, robh+dt, linux-mips, devicetree, linux-clk, linux-kernel, dongsheng.qiu, aric.pzqi, rick.tyliu, sihui.liu, jun.jiang, sernia.zhou Hi Paul, 于 Fri, 25 Jun 2021 16:47:30 +0100 Paul Cercueil <paul@crapouillou.net> 写道: > Hi Zhou, > > Le ven., juin 25 2021 at 23:19:42 +0800, 周琰杰 > <zhouyanjie@wanyeetech.com> a écrit : > > Hi Paul, > > > > 于 Fri, 25 Jun 2021 12:31:17 +0100 > > Paul Cercueil <paul@crapouillou.net> 写道: > > > >> Hi Zhou, > >> > >> Le jeu., juin 24 2021 at 23:06:29 +0800, 周琰杰 (Zhou Yanjie) > >> <zhouyanjie@wanyeetech.com> a écrit : > >> > 1.Add a new TCU channel as the percpu timer of core1, this is to > >> > prepare for the subsequent SMP support. The newly added > >> > channel will not adversely affect the current single-core state. > >> > 2.Adjust the position of TCU node to make it consistent with the > >> > order in jz4780.dtsi file. > >> > >> That's a bit superfluous, the order matters when adding new nodes, > >> but once they are added, moving them around only cause annoyance. > >> > >> > > >> > Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> > >> > --- > >> > > >> > Notes: > >> > v2: > >> > New patch. > >> > > >> > v2->v3: > >> > No change. > >> > > >> > arch/mips/boot/dts/ingenic/ci20.dts | 21 +++++++++++---------- > >> > 1 file changed, 11 insertions(+), 10 deletions(-) > >> > > >> > diff --git a/arch/mips/boot/dts/ingenic/ci20.dts > >> > b/arch/mips/boot/dts/ingenic/ci20.dts > >> > index 8877c62..70005cc 100644 > >> > --- a/arch/mips/boot/dts/ingenic/ci20.dts > >> > +++ b/arch/mips/boot/dts/ingenic/ci20.dts > >> > @@ -118,6 +118,17 @@ > >> > assigned-clock-rates = <48000000>; > >> > }; > >> > > >> > +&tcu { > >> > + /* > >> > + * 750 kHz for the system timers and 3 MHz for the > >> > clocksources, > >> > + * use channel #0 and #1 for the per cpu system timers, > >> > and use > >> > + * channel #2 for the clocksource. > >> > + */ > >> > + assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu > >> > TCU_CLK_TIMER1>, > >> > + <&tcu > >> > TCU_CLK_TIMER2>, <&tcu TCU_CLK_OST>; > >> > + assigned-clock-rates = <750000>, <750000>, <3000000>, > >> > <3000000>; > >> > >> Ideally you'd set TIMER1 to 3 MHz and TIMER2 to 750 kHz, > >> otherwise it > >> kind of breaks support for older kernels (they would still boot, > >> but with a very slow clocksource). So in the new DTS you could use > >> the timer0 clock for CPU #0, timer1 for the clocksource, and > >> timer2+ for cpus > 0. > > > > I checked the ingenic-timer driver, and it seems that the last TCU > > channel is always used as the clocksource in the driver, so it seems > > that we can only use timer2 as the clocksource in smp mode. Maybe we > > should add a note for smp is closed in the comment. And I found > > that I missed a problem, Nikolaus Schaller once reported that > > because the frequency of the tcu timer (only 16bit) used to provide > > the clocksource > > is too high, there will be a chance that the system will get stuck > > before the clocksource is switched to ost. And reducing the > > clocksource > > to 750kz can prevent it from happening. I will add this part to v4. > > When this part is added, both clockevent and clocksource will be > > 750kHz, but the 750kHz clocksource is only temporary, because it > > will then switch to the clocksource provided by ost, and ost works > > at 3MHz. > > Ok, then first change the clocksource to 750 kHz, then update it with > timer2. Sure, I will do it in v4. Thanks and best regards! > > Cheers, > -Paul > > > > > Thanks and best regards! > > > >> > >> Cheers, > >> -Paul > >> > >> > +}; > >> > + > >> > &mmc0 { > >> > status = "okay"; > >> > > >> > @@ -522,13 +533,3 @@ > >> > bias-disable; > >> > }; > >> > }; > >> > - > >> > -&tcu { > >> > - /* > >> > - * 750 kHz for the system timer and 3 MHz for the > >> > clocksource, > >> > - * use channel #0 for the system timer, #1 for the > >> > clocksource. > >> > - */ > >> > - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu > >> > TCU_CLK_TIMER1>, > >> > - <&tcu TCU_CLK_OST>; > >> > - assigned-clock-rates = <750000>, <3000000>, <3000000>; > >> > -}; > >> > -- > >> > 2.7.4 > >> > > >> > > > ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2021-06-25 16:32 UTC | newest] Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-06-24 15:06 [PATCH v3 0/4] Misc Ingenic patches 周琰杰 (Zhou Yanjie) 2021-06-24 15:06 ` [PATCH v3 1/4] MIPS: X1830: Respect cell count of common properties 周琰杰 (Zhou Yanjie) 2021-06-24 15:06 ` [PATCH v3 2/4] dt-bindings: clock: Add documentation for MAC PHY control bindings 周琰杰 (Zhou Yanjie) 2021-06-25 11:18 ` Paul Cercueil 2021-06-24 15:06 ` [PATCH v3 3/4] MIPS: Ingenic: Add MAC syscon nodes for Ingenic SoCs 周琰杰 (Zhou Yanjie) 2021-06-24 15:06 ` [PATCH v3 4/4] MIPS: CI20: Add second percpu timer for SMP 周琰杰 (Zhou Yanjie) 2021-06-25 11:31 ` Paul Cercueil 2021-06-25 12:14 ` 周琰杰 2021-06-25 15:19 ` 周琰杰 2021-06-25 15:47 ` Paul Cercueil 2021-06-25 16:32 ` 周琰杰
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