* [PATCH v3 0/2] crypto: hisilicon - some misc bugfix for SEC engine @ 2021-08-13 2:21 Kai Ye 2021-08-13 2:21 ` [PATCH v3 1/2] crypto: hisilicon/sec - fix the abnormal exiting process Kai Ye 2021-08-13 2:21 ` [PATCH v3 2/2] crypto: hisilicon/sec - modify the hardware endian configuration Kai Ye 0 siblings, 2 replies; 4+ messages in thread From: Kai Ye @ 2021-08-13 2:21 UTC (permalink / raw) To: herbert; +Cc: linux-crypto, linux-kernel, wangzhou1, yekai13 some misc bugfix for SEC engine. changes v1->v2: delete the "ifdefs", use the IS_ENABLED. changes v2->v3: fix merge conflict Kai Ye (2): crypto: hisilicon/sec - fix the abnormal exiting process crypto: hisilicon/sec - modify the hardware endian configuration drivers/crypto/hisilicon/sec2/sec.h | 5 ----- drivers/crypto/hisilicon/sec2/sec_main.c | 34 +++++++++++--------------------- 2 files changed, 11 insertions(+), 28 deletions(-) -- 2.7.4 ^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v3 1/2] crypto: hisilicon/sec - fix the abnormal exiting process 2021-08-13 2:21 [PATCH v3 0/2] crypto: hisilicon - some misc bugfix for SEC engine Kai Ye @ 2021-08-13 2:21 ` Kai Ye 2021-08-13 2:21 ` [PATCH v3 2/2] crypto: hisilicon/sec - modify the hardware endian configuration Kai Ye 1 sibling, 0 replies; 4+ messages in thread From: Kai Ye @ 2021-08-13 2:21 UTC (permalink / raw) To: herbert; +Cc: linux-crypto, linux-kernel, wangzhou1, yekai13 Because the algs registration process has added a judgment. So need to add the judgment for the abnormal exiting process. Signed-off-by: Kai Ye <yekai13@huawei.com> --- drivers/crypto/hisilicon/sec2/sec_main.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/hisilicon/sec2/sec_main.c b/drivers/crypto/hisilicon/sec2/sec_main.c index db4dbcf..45a1ddd 100644 --- a/drivers/crypto/hisilicon/sec2/sec_main.c +++ b/drivers/crypto/hisilicon/sec2/sec_main.c @@ -1020,7 +1020,8 @@ static int sec_probe(struct pci_dev *pdev, const struct pci_device_id *id) return 0; err_alg_unregister: - hisi_qm_alg_unregister(qm, &sec_devices); + if (qm->qp_num >= ctx_q_num) + hisi_qm_alg_unregister(qm, &sec_devices); err_qm_stop: sec_debugfs_exit(qm); hisi_qm_stop(qm, QM_NORMAL); -- 2.7.4 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v3 2/2] crypto: hisilicon/sec - modify the hardware endian configuration 2021-08-13 2:21 [PATCH v3 0/2] crypto: hisilicon - some misc bugfix for SEC engine Kai Ye 2021-08-13 2:21 ` [PATCH v3 1/2] crypto: hisilicon/sec - fix the abnormal exiting process Kai Ye @ 2021-08-13 2:21 ` Kai Ye 2021-08-13 5:34 ` kernel test robot 1 sibling, 1 reply; 4+ messages in thread From: Kai Ye @ 2021-08-13 2:21 UTC (permalink / raw) To: herbert; +Cc: linux-crypto, linux-kernel, wangzhou1, yekai13 When the endian configuration of the hardware is abnormal, it will cause the SEC engine is faulty that reports empty message. And it will affect the normal function of the hardware. Currently the soft configuration method can't restore the faulty device. The endian needs to be configured according to the system properties. So fix it. Signed-off-by: Kai Ye <yekai13@huawei.com> --- drivers/crypto/hisilicon/sec2/sec.h | 5 ----- drivers/crypto/hisilicon/sec2/sec_main.c | 31 +++++++++---------------------- 2 files changed, 9 insertions(+), 27 deletions(-) diff --git a/drivers/crypto/hisilicon/sec2/sec.h b/drivers/crypto/hisilicon/sec2/sec.h index 018415b..d97cf02 100644 --- a/drivers/crypto/hisilicon/sec2/sec.h +++ b/drivers/crypto/hisilicon/sec2/sec.h @@ -157,11 +157,6 @@ struct sec_ctx { struct device *dev; }; -enum sec_endian { - SEC_LE = 0, - SEC_32BE, - SEC_64BE -}; enum sec_debug_file_index { SEC_CLEAR_ENABLE, diff --git a/drivers/crypto/hisilicon/sec2/sec_main.c b/drivers/crypto/hisilicon/sec2/sec_main.c index 45a1ddd..a76542e 100644 --- a/drivers/crypto/hisilicon/sec2/sec_main.c +++ b/drivers/crypto/hisilicon/sec2/sec_main.c @@ -318,31 +318,20 @@ static const struct pci_device_id sec_dev_ids[] = { }; MODULE_DEVICE_TABLE(pci, sec_dev_ids); -static u8 sec_get_endian(struct hisi_qm *qm) +static void sec_set_endian(struct hisi_qm *qm) { u32 reg; - /* - * As for VF, it is a wrong way to get endian setting by - * reading a register of the engine - */ - if (qm->pdev->is_virtfn) { - dev_err_ratelimited(&qm->pdev->dev, - "cannot access a register in VF!\n"); - return SEC_LE; - } reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); - /* BD little endian mode */ - if (!(reg & BIT(0))) - return SEC_LE; + reg &= ~(BIT(1) | BIT(0)); + if (!IS_ENABLED(CONFIG_64BIT)) + reg |= BIT(1); - /* BD 32-bits big endian mode */ - else if (!(reg & BIT(1))) - return SEC_32BE; - /* BD 64-bits big endian mode */ - else - return SEC_64BE; + if (!IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN)) + reg |= BIT(0); + + writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); } static void sec_open_sva_prefetch(struct hisi_qm *qm) @@ -463,9 +452,7 @@ static int sec_engine_init(struct hisi_qm *qm) qm->io_base + SEC_BD_ERR_CHK_EN_REG3); /* config endian */ - reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); - reg |= sec_get_endian(qm); - writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); + sec_get_endian(qm); sec_enable_clock_gate(qm); -- 2.7.4 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v3 2/2] crypto: hisilicon/sec - modify the hardware endian configuration 2021-08-13 2:21 ` [PATCH v3 2/2] crypto: hisilicon/sec - modify the hardware endian configuration Kai Ye @ 2021-08-13 5:34 ` kernel test robot 0 siblings, 0 replies; 4+ messages in thread From: kernel test robot @ 2021-08-13 5:34 UTC (permalink / raw) To: Kai Ye, herbert Cc: kbuild-all, linux-crypto, linux-kernel, wangzhou1, yekai13 [-- Attachment #1: Type: text/plain, Size: 4230 bytes --] Hi Kai, Thank you for the patch! Yet something to improve: [auto build test ERROR on cryptodev/master] [also build test ERROR on crypto/master linux/master linus/master v5.14-rc5 next-20210812] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Kai-Ye/crypto-hisilicon-some-misc-bugfix-for-SEC-engine/20210813-102441 base: https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git master config: ia64-allmodconfig (attached as .config) compiler: ia64-linux-gcc (GCC) 10.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/0day-ci/linux/commit/3a700b467c3a65e18d9a7a2b7939c6b2fc369da7 git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Kai-Ye/crypto-hisilicon-some-misc-bugfix-for-SEC-engine/20210813-102441 git checkout 3a700b467c3a65e18d9a7a2b7939c6b2fc369da7 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-10.3.0 make.cross ARCH=ia64 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp@intel.com> All errors (new ones prefixed by >>): drivers/crypto/hisilicon/sec2/sec_main.c: In function 'sec_engine_init': >> drivers/crypto/hisilicon/sec2/sec_main.c:455:2: error: implicit declaration of function 'sec_get_endian'; did you mean 'sec_set_endian'? [-Werror=implicit-function-declaration] 455 | sec_get_endian(qm); | ^~~~~~~~~~~~~~ | sec_set_endian At top level: drivers/crypto/hisilicon/sec2/sec_main.c:321:13: warning: 'sec_set_endian' defined but not used [-Wunused-function] 321 | static void sec_set_endian(struct hisi_qm *qm) | ^~~~~~~~~~~~~~ cc1: some warnings being treated as errors vim +455 drivers/crypto/hisilicon/sec2/sec_main.c 405 406 static int sec_engine_init(struct hisi_qm *qm) 407 { 408 int ret; 409 u32 reg; 410 411 /* disable clock gate control before mem init */ 412 sec_disable_clock_gate(qm); 413 414 writel_relaxed(0x1, qm->io_base + SEC_MEM_START_INIT_REG); 415 416 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_MEM_INIT_DONE_REG, 417 reg, reg & 0x1, SEC_DELAY_10_US, 418 SEC_POLL_TIMEOUT_US); 419 if (ret) { 420 pci_err(qm->pdev, "fail to init sec mem\n"); 421 return ret; 422 } 423 424 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); 425 reg |= (0x1 << SEC_TRNG_EN_SHIFT); 426 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); 427 428 reg = readl_relaxed(qm->io_base + SEC_INTERFACE_USER_CTRL0_REG); 429 reg |= SEC_USER0_SMMU_NORMAL; 430 writel_relaxed(reg, qm->io_base + SEC_INTERFACE_USER_CTRL0_REG); 431 432 reg = readl_relaxed(qm->io_base + SEC_INTERFACE_USER_CTRL1_REG); 433 reg &= SEC_USER1_SMMU_MASK; 434 if (qm->use_sva && qm->ver == QM_HW_V2) 435 reg |= SEC_USER1_SMMU_SVA; 436 else 437 reg |= SEC_USER1_SMMU_NORMAL; 438 writel_relaxed(reg, qm->io_base + SEC_INTERFACE_USER_CTRL1_REG); 439 440 writel(SEC_SINGLE_PORT_MAX_TRANS, 441 qm->io_base + AM_CFG_SINGLE_PORT_MAX_TRANS); 442 443 writel(SEC_SAA_ENABLE, qm->io_base + SEC_SAA_EN_REG); 444 445 /* Enable sm4 extra mode, as ctr/ecb */ 446 writel_relaxed(SEC_BD_ERR_CHK_EN0, 447 qm->io_base + SEC_BD_ERR_CHK_EN_REG0); 448 /* Enable sm4 xts mode multiple iv */ 449 writel_relaxed(SEC_BD_ERR_CHK_EN1, 450 qm->io_base + SEC_BD_ERR_CHK_EN_REG1); 451 writel_relaxed(SEC_BD_ERR_CHK_EN3, 452 qm->io_base + SEC_BD_ERR_CHK_EN_REG3); 453 454 /* config endian */ > 455 sec_get_endian(qm); 456 457 sec_enable_clock_gate(qm); 458 459 return 0; 460 } 461 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org [-- Attachment #2: .config.gz --] [-- Type: application/gzip, Size: 64460 bytes --] ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2021-08-13 5:35 UTC | newest] Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-08-13 2:21 [PATCH v3 0/2] crypto: hisilicon - some misc bugfix for SEC engine Kai Ye 2021-08-13 2:21 ` [PATCH v3 1/2] crypto: hisilicon/sec - fix the abnormal exiting process Kai Ye 2021-08-13 2:21 ` [PATCH v3 2/2] crypto: hisilicon/sec - modify the hardware endian configuration Kai Ye 2021-08-13 5:34 ` kernel test robot
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