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* [v7 0/3]  Add L3 provider support for SC7280
@ 2021-08-20 11:23 Odelu Kukatla
  2021-08-20 11:23 ` [v7 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 Odelu Kukatla
                   ` (2 more replies)
  0 siblings, 3 replies; 10+ messages in thread
From: Odelu Kukatla @ 2021-08-20 11:23 UTC (permalink / raw)
  To: georgi.djakov, bjorn.andersson, evgreen
  Cc: sboyd, mdtipton, sibis, saravanak, okukatla, seansw, elder,
	linux-kernel, linux-arm-msm, linux-pm, linux-arm-msm-owner

Add Epoch Subsystem (EPSS) L3 provider support on SM7280 SoCs.

v7:
 - Addressed review comments (Georgi Djakov/Alex Elder)
 
Odelu Kukatla (3):
  dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280
  interconnect: qcom: Add EPSS L3 support on SC7280
  arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider

 .../bindings/interconnect/qcom,osm-l3.yaml         |   9 +-
 arch/arm64/boot/dts/qcom/sc7280.dtsi               |  11 ++
 drivers/interconnect/qcom/osm-l3.c                 | 138 +++++++++++++++++----
 drivers/interconnect/qcom/sc7280.h                 |  10 ++
 include/dt-bindings/interconnect/qcom,osm-l3.h     |  10 +-
 5 files changed, 153 insertions(+), 25 deletions(-)

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


^ permalink raw reply	[flat|nested] 10+ messages in thread

* [v7 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280
  2021-08-20 11:23 [v7 0/3] Add L3 provider support for SC7280 Odelu Kukatla
@ 2021-08-20 11:23 ` Odelu Kukatla
  2021-08-23 20:44   ` Rob Herring
  2021-08-20 11:23 ` [v7 2/3] interconnect: qcom: Add EPSS L3 support " Odelu Kukatla
  2021-08-20 11:23 ` [v7 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider Odelu Kukatla
  2 siblings, 1 reply; 10+ messages in thread
From: Odelu Kukatla @ 2021-08-20 11:23 UTC (permalink / raw)
  To: georgi.djakov, bjorn.andersson, evgreen, Andy Gross,
	Georgi Djakov, Rob Herring, Sibi Sankar, linux-arm-msm, linux-pm,
	devicetree, linux-kernel
  Cc: sboyd, mdtipton, saravanak, okukatla, seansw, elder, linux-arm-msm-owner

Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SC7280
SoCs.

Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
---
 .../devicetree/bindings/interconnect/qcom,osm-l3.yaml          |  9 ++++++++-
 include/dt-bindings/interconnect/qcom,osm-l3.h                 | 10 +++++++++-
 2 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
index e701524..919fce4 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
@@ -18,13 +18,20 @@ properties:
   compatible:
     enum:
       - qcom,sc7180-osm-l3
+      - qcom,sc7280-epss-l3
       - qcom,sc8180x-osm-l3
       - qcom,sdm845-osm-l3
       - qcom,sm8150-osm-l3
       - qcom,sm8250-epss-l3
 
   reg:
-    maxItems: 1
+    minItems: 1
+    maxItems: 4
+    items:
+      - description: OSM clock domain-0 base address and size
+      - description: OSM clock domain-1 base address and size
+      - description: OSM clock domain-2 base address and size
+      - description: OSM clock domain-3 base address and size
 
   clocks:
     items:
diff --git a/include/dt-bindings/interconnect/qcom,osm-l3.h b/include/dt-bindings/interconnect/qcom,osm-l3.h
index 61ef649..99534a5 100644
--- a/include/dt-bindings/interconnect/qcom,osm-l3.h
+++ b/include/dt-bindings/interconnect/qcom,osm-l3.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
- * Copyright (C) 2019 The Linux Foundation. All rights reserved.
+ * Copyright (C) 2019, 2021 The Linux Foundation. All rights reserved.
  */
 
 #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H
@@ -11,5 +11,13 @@
 
 #define MASTER_EPSS_L3_APPS	0
 #define SLAVE_EPSS_L3_SHARED	1
+#define SLAVE_EPSS_L3_CPU0	2
+#define SLAVE_EPSS_L3_CPU1	3
+#define SLAVE_EPSS_L3_CPU2	4
+#define SLAVE_EPSS_L3_CPU3	5
+#define SLAVE_EPSS_L3_CPU4	6
+#define SLAVE_EPSS_L3_CPU5	7
+#define SLAVE_EPSS_L3_CPU6	8
+#define SLAVE_EPSS_L3_CPU7	9
 
 #endif
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


^ permalink raw reply	[flat|nested] 10+ messages in thread

* [v7 2/3] interconnect: qcom: Add EPSS L3 support on SC7280
  2021-08-20 11:23 [v7 0/3] Add L3 provider support for SC7280 Odelu Kukatla
  2021-08-20 11:23 ` [v7 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 Odelu Kukatla
@ 2021-08-20 11:23 ` Odelu Kukatla
  2021-08-20 11:23 ` [v7 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider Odelu Kukatla
  2 siblings, 0 replies; 10+ messages in thread
From: Odelu Kukatla @ 2021-08-20 11:23 UTC (permalink / raw)
  To: georgi.djakov, bjorn.andersson, evgreen, Andy Gross,
	Georgi Djakov, linux-arm-msm, linux-pm, linux-kernel
  Cc: sboyd, mdtipton, sibis, saravanak, okukatla, seansw, elder,
	linux-arm-msm-owner

Add Epoch Subsystem (EPSS) L3 interconnect provider support on
SC7280 SoCs.

Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
---
 drivers/interconnect/qcom/osm-l3.c | 138 ++++++++++++++++++++++++++++++-------
 drivers/interconnect/qcom/sc7280.h |  10 +++
 2 files changed, 125 insertions(+), 23 deletions(-)

diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c
index c7af143..2e3882c 100644
--- a/drivers/interconnect/qcom/osm-l3.c
+++ b/drivers/interconnect/qcom/osm-l3.c
@@ -9,12 +9,14 @@
 #include <linux/io.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
+#include <linux/of_address.h>
 #include <linux/of_device.h>
 #include <linux/platform_device.h>
 
 #include <dt-bindings/interconnect/qcom,osm-l3.h>
 
 #include "sc7180.h"
+#include "sc7280.h"
 #include "sc8180x.h"
 #include "sdm845.h"
 #include "sm8150.h"
@@ -33,17 +35,33 @@
 
 /* EPSS Register offsets */
 #define EPSS_LUT_ROW_SIZE		4
+#define EPSS_REG_L3_VOTE		0x90
 #define EPSS_REG_FREQ_LUT		0x100
 #define EPSS_REG_PERF_STATE		0x320
+#define EPSS_CORE_OFFSET		0x4
+#define EPSS_L3_VOTE_REG(base, cpu)\
+			(((base) + EPSS_REG_L3_VOTE) +\
+			((cpu) * EPSS_CORE_OFFSET))
 
-#define OSM_L3_MAX_LINKS		1
+#define L3_DOMAIN_CNT		4
 
 #define to_osm_l3_provider(_provider) \
 	container_of(_provider, struct qcom_osm_l3_icc_provider, provider)
 
+/**
+ * struct qcom_osm_l3_icc_provider - Qualcomm specific interconnect provider
+ * @domain_base: an array of base address for each clock domain
+ * @max_state: max supported frequency level
+ * @per_core_dcvs: flag used to indicate whether the frequency scaling
+ * for each core is enabled
+ * @reg_perf_state: requested frequency level
+ * @lut_tables: an array of supported frequency levels
+ * @provider: interconnect provider of this node
+ */
 struct qcom_osm_l3_icc_provider {
-	void __iomem *base;
+	void __iomem *domain_base[L3_DOMAIN_CNT];
 	unsigned int max_state;
+	bool per_core_dcvs;
 	unsigned int reg_perf_state;
 	unsigned long lut_tables[LUT_MAX_ENTRIES];
 	struct icc_provider provider;
@@ -52,36 +70,48 @@ struct qcom_osm_l3_icc_provider {
 /**
  * struct qcom_osm_l3_node - Qualcomm specific interconnect nodes
  * @name: the node name used in debugfs
- * @links: an array of nodes where we can go next while traversing
  * @id: a unique node identifier
- * @num_links: the total number of @links
  * @buswidth: width of the interconnect between a node and the bus
+ * @domain: clock domain of the cpu node
+ * @cpu: cpu instance within its clock domain
+ * @num_links: the total number of @links
+ * @links: an array of nodes where we can go next while traversing
  */
 struct qcom_osm_l3_node {
 	const char *name;
-	u16 links[OSM_L3_MAX_LINKS];
 	u16 id;
-	u16 num_links;
 	u16 buswidth;
+	u8 domain;
+	u8 cpu;
+	u16 num_links;
+	u16 links[];
 };
 
 struct qcom_osm_l3_desc {
 	const struct qcom_osm_l3_node **nodes;
 	size_t num_nodes;
+	bool per_core_dcvs;
 	unsigned int lut_row_size;
 	unsigned int reg_freq_lut;
 	unsigned int reg_perf_state;
 };
 
-#define DEFINE_QNODE(_name, _id, _buswidth, ...)			\
+#define __DEFINE_QNODE(_name, _id, _buswidth, _domain, _cpu, ...)	\
 	static const struct qcom_osm_l3_node _name = {			\
 		.name = #_name,						\
 		.id = _id,						\
 		.buswidth = _buswidth,					\
+		.domain = _domain,					\
+		.cpu = _cpu,						\
 		.num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })),	\
 		.links = { __VA_ARGS__ },				\
 	}
 
+#define DEFINE_QNODE(_name, _id, _buswidth, ...)		\
+		__DEFINE_QNODE(_name, _id, _buswidth, 0, 0, __VA_ARGS__)
+#define DEFINE_DCVS_QNODE(_name, _id, _buswidth, _domain, _cpu, ...)		\
+		__DEFINE_QNODE(_name, _id, _buswidth, _domain, _cpu, __VA_ARGS__)
+
 DEFINE_QNODE(sdm845_osm_apps_l3, SDM845_MASTER_OSM_L3_APPS, 16, SDM845_SLAVE_OSM_L3);
 DEFINE_QNODE(sdm845_osm_l3, SDM845_SLAVE_OSM_L3, 16);
 
@@ -162,26 +192,80 @@ static const struct qcom_osm_l3_desc sm8250_icc_epss_l3 = {
 	.reg_perf_state = EPSS_REG_PERF_STATE,
 };
 
+DEFINE_DCVS_QNODE(sc7280_epss_apps_l3, SC7280_MASTER_EPSS_L3_APPS, 32, 0, 0,
+		  SC7280_SLAVE_EPSS_L3_SHARED, SC7280_SLAVE_EPSS_L3_CPU0,
+		  SC7280_SLAVE_EPSS_L3_CPU1, SC7280_SLAVE_EPSS_L3_CPU2,
+		  SC7280_SLAVE_EPSS_L3_CPU3, SC7280_SLAVE_EPSS_L3_CPU4,
+		  SC7280_SLAVE_EPSS_L3_CPU5, SC7280_SLAVE_EPSS_L3_CPU6,
+		  SC7280_SLAVE_EPSS_L3_CPU7);
+DEFINE_DCVS_QNODE(sc7280_epss_l3_shared, SC7280_SLAVE_EPSS_L3_SHARED, 32, 0, 0);
+DEFINE_DCVS_QNODE(sc7280_epss_l3_cpu0, SC7280_SLAVE_EPSS_L3_CPU0, 32, 1, 0);
+DEFINE_DCVS_QNODE(sc7280_epss_l3_cpu1, SC7280_SLAVE_EPSS_L3_CPU1, 32, 1, 1);
+DEFINE_DCVS_QNODE(sc7280_epss_l3_cpu2, SC7280_SLAVE_EPSS_L3_CPU2, 32, 1, 2);
+DEFINE_DCVS_QNODE(sc7280_epss_l3_cpu3, SC7280_SLAVE_EPSS_L3_CPU3, 32, 1, 3);
+DEFINE_DCVS_QNODE(sc7280_epss_l3_cpu4, SC7280_SLAVE_EPSS_L3_CPU4, 32, 2, 0);
+DEFINE_DCVS_QNODE(sc7280_epss_l3_cpu5, SC7280_SLAVE_EPSS_L3_CPU5, 32, 2, 1);
+DEFINE_DCVS_QNODE(sc7280_epss_l3_cpu6, SC7280_SLAVE_EPSS_L3_CPU6, 32, 2, 2);
+DEFINE_DCVS_QNODE(sc7280_epss_l3_cpu7, SC7280_SLAVE_EPSS_L3_CPU7, 32, 3, 0);
+
+static const struct qcom_osm_l3_node *sc7280_epss_l3_nodes[] = {
+	[MASTER_EPSS_L3_APPS] = &sc7280_epss_apps_l3,
+	[SLAVE_EPSS_L3_SHARED] = &sc7280_epss_l3_shared,
+	[SLAVE_EPSS_L3_CPU0] = &sc7280_epss_l3_cpu0,
+	[SLAVE_EPSS_L3_CPU1] = &sc7280_epss_l3_cpu1,
+	[SLAVE_EPSS_L3_CPU2] = &sc7280_epss_l3_cpu2,
+	[SLAVE_EPSS_L3_CPU3] = &sc7280_epss_l3_cpu3,
+	[SLAVE_EPSS_L3_CPU4] = &sc7280_epss_l3_cpu4,
+	[SLAVE_EPSS_L3_CPU5] = &sc7280_epss_l3_cpu5,
+	[SLAVE_EPSS_L3_CPU6] = &sc7280_epss_l3_cpu6,
+	[SLAVE_EPSS_L3_CPU7] = &sc7280_epss_l3_cpu7,
+};
+
+static const struct qcom_osm_l3_desc sc7280_icc_epss_l3 = {
+	.nodes = sc7280_epss_l3_nodes,
+	.num_nodes = ARRAY_SIZE(sc7280_epss_l3_nodes),
+	.per_core_dcvs = true,
+	.lut_row_size = EPSS_LUT_ROW_SIZE,
+	.reg_freq_lut = EPSS_REG_FREQ_LUT,
+	.reg_perf_state = EPSS_REG_PERF_STATE,
+};
+
+static u32 qcom_osm_l3_aggregate_peak(struct icc_node *src, struct icc_node *dst)
+{
+	struct icc_node *n;
+	u32 agg_peak = 0;
+	u32 agg_avg = 0;
+	struct qcom_osm_l3_icc_provider *qp;
+	struct icc_provider *provider;
+
+	provider = src->provider;
+	qp = to_osm_l3_provider(provider);
+
+	/* Skip aggregation when per core l3 scaling is enabled */
+	if (qp->per_core_dcvs)
+		return dst->peak_bw;
+
+	list_for_each_entry(n, &provider->nodes, node_list)
+		provider->aggregate(n, 0, n->avg_bw, n->peak_bw, &agg_avg, &agg_peak);
+
+	agg_peak = max(agg_avg, agg_peak);
+
+	return agg_peak;
+}
+
 static int qcom_osm_l3_set(struct icc_node *src, struct icc_node *dst)
 {
 	struct qcom_osm_l3_icc_provider *qp;
 	struct icc_provider *provider;
 	const struct qcom_osm_l3_node *qn;
-	struct icc_node *n;
 	unsigned int index;
-	u32 agg_peak = 0;
-	u32 agg_avg = 0;
 	u64 rate;
 
-	qn = src->data;
+	qn = dst->data;
 	provider = src->provider;
 	qp = to_osm_l3_provider(provider);
 
-	list_for_each_entry(n, &provider->nodes, node_list)
-		provider->aggregate(n, 0, n->avg_bw, n->peak_bw,
-				    &agg_avg, &agg_peak);
-
-	rate = max(agg_avg, agg_peak);
+	rate = qcom_osm_l3_aggregate_peak(src, dst);
 	rate = icc_units_to_bps(rate);
 	do_div(rate, qn->buswidth);
 
@@ -190,7 +274,10 @@ static int qcom_osm_l3_set(struct icc_node *src, struct icc_node *dst)
 			break;
 	}
 
-	writel_relaxed(index, qp->base + qp->reg_perf_state);
+	if (qp->per_core_dcvs)
+		writel_relaxed(index, EPSS_L3_VOTE_REG(qp->domain_base[qn->domain], qn->cpu));
+	else
+		writel_relaxed(index, qp->domain_base[qn->domain] + qp->reg_perf_state);
 
 	return 0;
 }
@@ -205,7 +292,7 @@ static int qcom_osm_l3_remove(struct platform_device *pdev)
 
 static int qcom_osm_l3_probe(struct platform_device *pdev)
 {
-	u32 info, src, lval, i, prev_freq = 0, freq;
+	u32 info, src, lval, i = 0, prev_freq = 0, freq;
 	static unsigned long hw_rate, xo_rate;
 	struct qcom_osm_l3_icc_provider *qp;
 	const struct qcom_osm_l3_desc *desc;
@@ -235,12 +322,15 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
 	if (!qp)
 		return -ENOMEM;
 
-	qp->base = devm_platform_ioremap_resource(pdev, 0);
-	if (IS_ERR(qp->base))
-		return PTR_ERR(qp->base);
+	while (of_get_address(pdev->dev.of_node, i, NULL, NULL)) {
+		qp->domain_base[i] = devm_platform_ioremap_resource(pdev, i);
+		if (IS_ERR(qp->domain_base[i]))
+			return PTR_ERR(qp->domain_base[i]);
+		i++;
+	}
 
 	/* HW should be in enabled state to proceed */
-	if (!(readl_relaxed(qp->base + REG_ENABLE) & 0x1)) {
+	if (!(readl_relaxed(qp->domain_base[0] + REG_ENABLE) & 0x1)) {
 		dev_err(&pdev->dev, "error hardware not enabled\n");
 		return -ENODEV;
 	}
@@ -252,7 +342,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
 	qp->reg_perf_state = desc->reg_perf_state;
 
 	for (i = 0; i < LUT_MAX_ENTRIES; i++) {
-		info = readl_relaxed(qp->base + desc->reg_freq_lut +
+		info = readl_relaxed(qp->domain_base[0] + desc->reg_freq_lut +
 				     i * desc->lut_row_size);
 		src = FIELD_GET(LUT_SRC, info);
 		lval = FIELD_GET(LUT_L_VAL, info);
@@ -271,6 +361,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
 		prev_freq = freq;
 	}
 	qp->max_state = i;
+	qp->per_core_dcvs = desc->per_core_dcvs;
 
 	qnodes = desc->nodes;
 	num_nodes = desc->num_nodes;
@@ -326,6 +417,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
 
 static const struct of_device_id osm_l3_of_match[] = {
 	{ .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 },
+	{ .compatible = "qcom,sc7280-epss-l3", .data = &sc7280_icc_epss_l3 },
 	{ .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 },
 	{ .compatible = "qcom,sm8150-osm-l3", .data = &sm8150_icc_osm_l3 },
 	{ .compatible = "qcom,sc8180x-osm-l3", .data = &sc8180x_icc_osm_l3 },
diff --git a/drivers/interconnect/qcom/sc7280.h b/drivers/interconnect/qcom/sc7280.h
index 175e400..5df7600 100644
--- a/drivers/interconnect/qcom/sc7280.h
+++ b/drivers/interconnect/qcom/sc7280.h
@@ -150,5 +150,15 @@
 #define SC7280_SLAVE_PCIE_1			139
 #define SC7280_SLAVE_QDSS_STM			140
 #define SC7280_SLAVE_TCU			141
+#define SC7280_MASTER_EPSS_L3_APPS			142
+#define SC7280_SLAVE_EPSS_L3_SHARED			143
+#define SC7280_SLAVE_EPSS_L3_CPU0			144
+#define SC7280_SLAVE_EPSS_L3_CPU1			145
+#define SC7280_SLAVE_EPSS_L3_CPU2			146
+#define SC7280_SLAVE_EPSS_L3_CPU3			147
+#define SC7280_SLAVE_EPSS_L3_CPU4			148
+#define SC7280_SLAVE_EPSS_L3_CPU5			149
+#define SC7280_SLAVE_EPSS_L3_CPU6			150
+#define SC7280_SLAVE_EPSS_L3_CPU7			151
 
 #endif
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


^ permalink raw reply	[flat|nested] 10+ messages in thread

* [v7 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider
  2021-08-20 11:23 [v7 0/3] Add L3 provider support for SC7280 Odelu Kukatla
  2021-08-20 11:23 ` [v7 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 Odelu Kukatla
  2021-08-20 11:23 ` [v7 2/3] interconnect: qcom: Add EPSS L3 support " Odelu Kukatla
@ 2021-08-20 11:23 ` Odelu Kukatla
  2021-09-03 19:06   ` Stephen Boyd
  2 siblings, 1 reply; 10+ messages in thread
From: Odelu Kukatla @ 2021-08-20 11:23 UTC (permalink / raw)
  To: georgi.djakov, bjorn.andersson, evgreen, Andy Gross, Rob Herring,
	linux-arm-msm, devicetree, linux-kernel
  Cc: sboyd, mdtipton, sibis, saravanak, okukatla, seansw, elder,
	linux-pm, linux-arm-msm-owner

Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280
SoCs.

Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sc7280.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 53a21d0..cf59b47 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -1848,6 +1848,17 @@
 			};
 		};
 
+		epss_l3: interconnect@18590000 {
+			compatible = "qcom,sc7280-epss-l3";
+			reg = <0 0x18590000 0 1000>,
+			      <0 0x18591000 0 0x100>,
+			      <0 0x18592000 0 0x100>,
+			      <0 0x18593000 0 0x100>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+			clock-names = "xo", "alternate";
+			#interconnect-cells = <1>;
+		};
+
 		cpufreq_hw: cpufreq@18591000 {
 			compatible = "qcom,cpufreq-epss";
 			reg = <0 0x18591100 0 0x900>,
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [v7 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280
  2021-08-20 11:23 ` [v7 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 Odelu Kukatla
@ 2021-08-23 20:44   ` Rob Herring
  0 siblings, 0 replies; 10+ messages in thread
From: Rob Herring @ 2021-08-23 20:44 UTC (permalink / raw)
  To: Odelu Kukatla
  Cc: elder, linux-kernel, evgreen, linux-pm, Rob Herring,
	Georgi Djakov, mdtipton, Andy Gross, linux-arm-msm-owner,
	devicetree, seansw, saravanak, sboyd, linux-arm-msm,
	bjorn.andersson, Sibi Sankar, georgi.djakov

On Fri, 20 Aug 2021 16:53:39 +0530, Odelu Kukatla wrote:
> Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SC7280
> SoCs.
> 
> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
> ---
>  .../devicetree/bindings/interconnect/qcom,osm-l3.yaml          |  9 ++++++++-
>  include/dt-bindings/interconnect/qcom,osm-l3.h                 | 10 +++++++++-
>  2 files changed, 17 insertions(+), 2 deletions(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [v7 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider
  2021-08-20 11:23 ` [v7 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider Odelu Kukatla
@ 2021-09-03 19:06   ` Stephen Boyd
  2021-09-15  5:05     ` okukatla
  0 siblings, 1 reply; 10+ messages in thread
From: Stephen Boyd @ 2021-09-03 19:06 UTC (permalink / raw)
  To: Andy Gross, Odelu Kukatla, Rob Herring, bjorn.andersson,
	devicetree, evgreen, georgi.djakov, linux-arm-msm, linux-kernel
  Cc: mdtipton, sibis, saravanak, seansw, elder, linux-pm, linux-arm-msm-owner

Quoting Odelu Kukatla (2021-08-20 04:23:41)
> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280
> SoCs.
>
> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
> ---
>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 11 +++++++++++
>  1 file changed, 11 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 53a21d0..cf59b47 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -1848,6 +1848,17 @@
>                         };
>                 };
>
> +               epss_l3: interconnect@18590000 {
> +                       compatible = "qcom,sc7280-epss-l3";
> +                       reg = <0 0x18590000 0 1000>,

Is this supposed to be 0x1000?

> +                             <0 0x18591000 0 0x100>,
> +                             <0 0x18592000 0 0x100>,
> +                             <0 0x18593000 0 0x100>;
> +                       clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
> +                       clock-names = "xo", "alternate";
> +                       #interconnect-cells = <1>;
> +               };
> +
>                 cpufreq_hw: cpufreq@18591000 {
>                         compatible = "qcom,cpufreq-epss";
>                         reg = <0 0x18591100 0 0x900>,
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>

^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [v7 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider
  2021-09-03 19:06   ` Stephen Boyd
@ 2021-09-15  5:05     ` okukatla
  2021-09-15  6:26       ` okukatla
  0 siblings, 1 reply; 10+ messages in thread
From: okukatla @ 2021-09-15  5:05 UTC (permalink / raw)
  To: Stephen Boyd
  Cc: Andy Gross, Rob Herring, bjorn.andersson, devicetree, evgreen,
	georgi.djakov, linux-arm-msm, linux-kernel, mdtipton, sibis,
	saravanak, seansw, elder, linux-pm, linux-arm-msm-owner

On 2021-09-04 00:36, Stephen Boyd wrote:
> Quoting Odelu Kukatla (2021-08-20 04:23:41)
>> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280
>> SoCs.
>> 
>> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
>> ---
>>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 11 +++++++++++
>>  1 file changed, 11 insertions(+)
>> 
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi 
>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index 53a21d0..cf59b47 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -1848,6 +1848,17 @@
>>                         };
>>                 };
>> 
>> +               epss_l3: interconnect@18590000 {
>> +                       compatible = "qcom,sc7280-epss-l3";
>> +                       reg = <0 0x18590000 0 1000>,
> 
> Is this supposed to be 0x1000?
> 
No, This is 1000 or 0x3E8.
>> +                             <0 0x18591000 0 0x100>,
>> +                             <0 0x18592000 0 0x100>,
>> +                             <0 0x18593000 0 0x100>;
>> +                       clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc 
>> GCC_GPLL0>;
>> +                       clock-names = "xo", "alternate";
>> +                       #interconnect-cells = <1>;
>> +               };
>> +
>>                 cpufreq_hw: cpufreq@18591000 {
>>                         compatible = "qcom,cpufreq-epss";
>>                         reg = <0 0x18591100 0 0x900>,
>> --
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora 
>> Forum,
>> a Linux Foundation Collaborative Project
>> 

^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [v7 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider
  2021-09-15  5:05     ` okukatla
@ 2021-09-15  6:26       ` okukatla
  2021-09-15 19:40         ` Stephen Boyd
  0 siblings, 1 reply; 10+ messages in thread
From: okukatla @ 2021-09-15  6:26 UTC (permalink / raw)
  To: Stephen Boyd
  Cc: Andy Gross, Rob Herring, bjorn.andersson, devicetree, evgreen,
	georgi.djakov, linux-arm-msm, linux-kernel, mdtipton, sibis,
	saravanak, seansw, elder, linux-pm, linux-arm-msm-owner,
	okukatla=codeaurora.org

On 2021-09-15 10:35, okukatla@codeaurora.org wrote:
> On 2021-09-04 00:36, Stephen Boyd wrote:
>> Quoting Odelu Kukatla (2021-08-20 04:23:41)
>>> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280
>>> SoCs.
>>> 
>>> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
>>> ---
>>>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 11 +++++++++++
>>>  1 file changed, 11 insertions(+)
>>> 
>>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi 
>>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>>> index 53a21d0..cf59b47 100644
>>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>>> @@ -1848,6 +1848,17 @@
>>>                         };
>>>                 };
>>> 
>>> +               epss_l3: interconnect@18590000 {
>>> +                       compatible = "qcom,sc7280-epss-l3";
>>> +                       reg = <0 0x18590000 0 1000>,
>> 
>> Is this supposed to be 0x1000?
>> 
> No, This is 1000 or 0x3E8.
We have mapped only required registers for L3 scaling, 1000/0x3E8 is 
suffice.
But i will update it to 0x1000 in next revision so that entire clock 
domain region-0 is mapped.
>>> +                             <0 0x18591000 0 0x100>,
>>> +                             <0 0x18592000 0 0x100>,
>>> +                             <0 0x18593000 0 0x100>;
>>> +                       clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc 
>>> GCC_GPLL0>;
>>> +                       clock-names = "xo", "alternate";
>>> +                       #interconnect-cells = <1>;
>>> +               };
>>> +
>>>                 cpufreq_hw: cpufreq@18591000 {
>>>                         compatible = "qcom,cpufreq-epss";
>>>                         reg = <0 0x18591100 0 0x900>,
>>> --
>>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora 
>>> Forum,
>>> a Linux Foundation Collaborative Project
>>> 

^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [v7 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider
  2021-09-15  6:26       ` okukatla
@ 2021-09-15 19:40         ` Stephen Boyd
  2021-09-16  8:00           ` okukatla
  0 siblings, 1 reply; 10+ messages in thread
From: Stephen Boyd @ 2021-09-15 19:40 UTC (permalink / raw)
  To: okukatla
  Cc: Andy Gross, Rob Herring, bjorn.andersson, devicetree, evgreen,
	georgi.djakov, linux-arm-msm, linux-kernel, mdtipton, sibis,
	saravanak, seansw, elder, linux-pm, linux-arm-msm-owner,
	okukatla=codeaurora.org

Quoting okukatla@codeaurora.org (2021-09-14 23:26:19)
> On 2021-09-15 10:35, okukatla@codeaurora.org wrote:
> > On 2021-09-04 00:36, Stephen Boyd wrote:
> >> Quoting Odelu Kukatla (2021-08-20 04:23:41)
> >>> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280
> >>> SoCs.
> >>>
> >>> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
> >>> ---
> >>>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 11 +++++++++++
> >>>  1 file changed, 11 insertions(+)
> >>>
> >>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> >>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> >>> index 53a21d0..cf59b47 100644
> >>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> >>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> >>> @@ -1848,6 +1848,17 @@
> >>>                         };
> >>>                 };
> >>>
> >>> +               epss_l3: interconnect@18590000 {
> >>> +                       compatible = "qcom,sc7280-epss-l3";
> >>> +                       reg = <0 0x18590000 0 1000>,
> >>
> >> Is this supposed to be 0x1000?
> >>
> > No, This is 1000 or 0x3E8.

Wow ok. Why is it the only size that isn't in hex format? Please try to
be consistent and use hex throughout.

> We have mapped only required registers for L3 scaling, 1000/0x3E8 is
> suffice.
> But i will update it to 0x1000 in next revision so that entire clock
> domain region-0 is mapped.

Doesn't that conflict with the cpufreq-hw device?

> >>> +                             <0 0x18591000 0 0x100>,
> >>> +                             <0 0x18592000 0 0x100>,
> >>> +                             <0 0x18593000 0 0x100>;
> >>> +                       clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc
> >>> GCC_GPLL0>;
> >>> +                       clock-names = "xo", "alternate";
> >>> +                       #interconnect-cells = <1>;
> >>> +               };
> >>> +
> >>>                 cpufreq_hw: cpufreq@18591000 {
> >>>                         compatible = "qcom,cpufreq-epss";
> >>>                         reg = <0 0x18591100 0 0x900>,

^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [v7 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider
  2021-09-15 19:40         ` Stephen Boyd
@ 2021-09-16  8:00           ` okukatla
  0 siblings, 0 replies; 10+ messages in thread
From: okukatla @ 2021-09-16  8:00 UTC (permalink / raw)
  To: Stephen Boyd
  Cc: Andy Gross, Rob Herring, bjorn.andersson, devicetree, evgreen,
	georgi.djakov, linux-arm-msm, linux-kernel, mdtipton, sibis,
	saravanak, seansw, elder, linux-pm, linux-arm-msm-owner,
	okukatla=codeaurora.org

On 2021-09-16 01:10, Stephen Boyd wrote:
> Quoting okukatla@codeaurora.org (2021-09-14 23:26:19)
>> On 2021-09-15 10:35, okukatla@codeaurora.org wrote:
>> > On 2021-09-04 00:36, Stephen Boyd wrote:
>> >> Quoting Odelu Kukatla (2021-08-20 04:23:41)
>> >>> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280
>> >>> SoCs.
>> >>>
>> >>> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
>> >>> ---
>> >>>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 11 +++++++++++
>> >>>  1 file changed, 11 insertions(+)
>> >>>
>> >>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> >>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> >>> index 53a21d0..cf59b47 100644
>> >>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> >>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> >>> @@ -1848,6 +1848,17 @@
>> >>>                         };
>> >>>                 };
>> >>>
>> >>> +               epss_l3: interconnect@18590000 {
>> >>> +                       compatible = "qcom,sc7280-epss-l3";
>> >>> +                       reg = <0 0x18590000 0 1000>,
>> >>
>> >> Is this supposed to be 0x1000?
>> >>
>> > No, This is 1000 or 0x3E8.
> 
> Wow ok. Why is it the only size that isn't in hex format? Please try to
> be consistent and use hex throughout.
> 
Sure, will update it to hex format in new revision.
>> We have mapped only required registers for L3 scaling, 1000/0x3E8 is
>> suffice.
>> But i will update it to 0x1000 in next revision so that entire clock
>> domain region-0 is mapped.
> 
> Doesn't that conflict with the cpufreq-hw device?
> 
epss_l3 maps (0x18590000, size:0x1000) region which cpufreq-hw does not 
need. I will update size to 0x1000 for this region only.

>> >>> +                             <0 0x18591000 0 0x100>,
>> >>> +                             <0 0x18592000 0 0x100>,
>> >>> +                             <0 0x18593000 0 0x100>;
>> >>> +                       clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc
>> >>> GCC_GPLL0>;
>> >>> +                       clock-names = "xo", "alternate";
>> >>> +                       #interconnect-cells = <1>;
>> >>> +               };
>> >>> +
>> >>>                 cpufreq_hw: cpufreq@18591000 {
>> >>>                         compatible = "qcom,cpufreq-epss";
>> >>>                         reg = <0 0x18591100 0 0x900>,

^ permalink raw reply	[flat|nested] 10+ messages in thread

end of thread, other threads:[~2021-09-16  8:04 UTC | newest]

Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-08-20 11:23 [v7 0/3] Add L3 provider support for SC7280 Odelu Kukatla
2021-08-20 11:23 ` [v7 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 Odelu Kukatla
2021-08-23 20:44   ` Rob Herring
2021-08-20 11:23 ` [v7 2/3] interconnect: qcom: Add EPSS L3 support " Odelu Kukatla
2021-08-20 11:23 ` [v7 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider Odelu Kukatla
2021-09-03 19:06   ` Stephen Boyd
2021-09-15  5:05     ` okukatla
2021-09-15  6:26       ` okukatla
2021-09-15 19:40         ` Stephen Boyd
2021-09-16  8:00           ` okukatla

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